public void Initialize()
{
cpu.ProgramPerfCounters(
GetPerfCtlValue(0xD9, 0, false, 0, 0), // Waiting for All Quiet
GetPerfCtlValue(0xD3, 0, false, 0, 0), // Stall for serialization
GetPerfCtlValue(0x87, 0, false, 0, 0), // Instruction fetch stall
GetPerfCtlValue(0x04, 1, false, 0, 0), // SSE Moves eliminated
GetPerfCtlValue(0xC0, 0, false, 0, 0), // Instr
GetPerfCtlValue(0x34, 0, false, 0, 0)); // FP + Load buffer stall
}
public void Initialize()
{
cpu.ProgramPerfCounters(
GetPerfCtlValue(0xC0, 0, false, 0, 0), // instructions retired
GetPerfCtlValue(0xCB, 0x4, false, 0, 0), // SSE/AVX instructions retired
GetPerfCtlValue(0xCB, 0x3, false, 0, 0), // MMX/x86 instructions retired
GetPerfCtlValue(0, 0x1, false, 0, 0), // perf_ctl_3, mux this
GetPerfCtlValue(0x1, 0, false, 0, 0), // FP scheduler empty
GetPerfCtlValue(0x5, 0xF, false, 0, 0)); // FP Serializing op
}
public void Initialize()
{
cpu.ProgramPerfCounters(
GetPerfCtlValue(0xD8, 0, false, 0, 0), // LDQ Full
GetPerfCtlValue(0xD8, 0, false, 0, 1), // STQ Full
GetPerfCtlValue(0xDD, 0, false, 0, 1), // Int PRF Full
GetPerfCtlValue(0xDB, 0b11111, false, 0, 0), // FP exceptions
GetPerfCtlValue(0xC0, 0, false, 0, 0), // Instructions
GetPerfCtlValue(0xCB, 0b111, false, 0, 0)); // FP/MMX instructions
}
public void Initialize()
{
cpu.ProgramPerfCounters(
GetPerfCtlValue(0xD7, 0, false, 0, 0), // FP Scheduler Full
GetPerfCtlValue(0xDE, 0xFF, false, 0, 1), // FP PRF Full. Does this work?
GetPerfCtlValue(0xD0, 0, false, 0, 0), // Decoder empty
GetPerfCtlValue(0x3, 0xFF, false, 0, 0), // Flops retired
GetPerfCtlValue(0xC0, 0, false, 0, 0), // Instr
GetPerfCtlValue(0x5, 0b1111, false, 0, 0)); // Serializing FP ops
}
public void Initialize()
{
cpu.ProgramPerfCounters(
GetPerfCtlValue(0x88, 0, false, 0, 0), // return stack hits
GetPerfCtlValue(0x89, 0, false, 0, 0), // return stack overflows
GetPerfCtlValue(0xC0, 0, false, 0, 0), // ret instr
GetPerfCtlValue(0xC4, 0, false, 0, 0), // ret taken branches
GetPerfCtlValue(0xC2, 0, false, 0, 0), // ret branches
GetPerfCtlValue(0xC3, 0, false, 0, 0)); // ret misp branch
}
public void Initialize()
{
cpu.ProgramPerfCounters(
GetPerfCtlValue(0xD1, 0, false, 0, 0), // All dispatch stalls
GetPerfCtlValue(0xD5, 0, false, 0, 0), // ROB full
GetPerfCtlValue(0xD6, 0, false, 0, 0), // Integer scheduler full
GetPerfCtlValue(0xC0, 0b111, false, 0, 1), // x87 ops
GetPerfCtlValue(0xC0, 0, false, 0, 0), // Instructions
GetPerfCtlValue(0x42, 0b1000, false, 0, 0)); // DC refill from L2, read data error
}
public void Initialize()
{
cpu.ProgramPerfCounters(
GetPerfCtlValue(0x32, 0, false, 0, 0), // misaligned stores
GetPerfCtlValue(0x41, 0b11, false, 0, 0), // DC Miss
GetPerfCtlValue(0x29, 3, false, 0, 0), // LS dispatch
GetPerfCtlValue(0xC0, 0, false, 0, 0), // ret instr
GetPerfCtlValue(0x40, 0, false, 1, 0), // DC access, cmask 1
GetPerfCtlValue(0x40, 0, false, 2, 0)); // DC access, cmask 2
}
public void Initialize()
{
cpu.ProgramPerfCounters(
GetPerfCtlValue(0x23, 1, false, 0, 0), // LDQ full
GetPerfCtlValue(0x23, 2, false, 0, 0), // STQ full
GetPerfCtlValue(0x43, 0, false, 0, 0), // DC fill from system
GetPerfCtlValue(0xC0, 0, false, 0, 0), // ret instr
GetPerfCtlValue(0x42, 0b1011, false, 0, 0), // DC fill from L2 or system
GetPerfCtlValue(0x40, 0, false, 0, 0)); // DC access
}
public void Initialize()
{
cpu.ProgramPerfCounters(
GetPerfCtlValue(0x80, 0, false, 0, 0), // ic fetch
GetPerfCtlValue(0x82, 0, false, 0, 0), // ic refill from L2
GetPerfCtlValue(0x83, 0, false, 0, 0), // ic refill from system
GetPerfCtlValue(0xC0, 0, false, 0, 0), // ret instr
GetPerfCtlValue(0xC1, 0, false, 0, 0), // ret uops
GetPerfCtlValue(0x21, 0, false, 0, 0)); // SMC pipeline restart
}