public override void bus_interference_count(Cmd cmd) { if (cmd == null) return; Req req = cmd.req; for (int p = 0; p < Config.N; p ++) { if (set_bank_int[p] == false && p != req.pid && meta_mctrl.proc_req_in_queue(p)) { set_bus_int[p] = true; t_interference_bus[p] ++; } } }
public override void issued_write_cmd(Cmd cmd) { Dbg.Assert(cmd.type == Cmd.TypeEnum.WRITE); uint cid = cmd.addr.cid; serve_cnt[cid]++; }
private void issue_cmd(Cmd cmd) { MemAddr addr = cmd.addr; List<Cmd> cmd_q = cmdqs[addr.rid, addr.bid]; Dbg.Assert(cmd == cmd_q[0]); cmd_q.RemoveAt(0); BankStat bank_stat = Stat.banks[addr.cid, addr.rid, addr.bid]; BusStat bus_stat = Stat.busses[addr.cid]; //writeback mode stats if (wb_mode) { if (cmd.type == Cmd.TypeEnum.READ) rds_per_wb_mode++; else if (cmd.type == Cmd.TypeEnum.WRITE) wbs_per_wb_mode++; } //string dbg; switch (cmd.type) { case Cmd.TypeEnum.ACTIVATE: activate(addr); /*dbg = String.Format("@{0,6} DRAM ACTI: Channel {1}, Rank {2}, Bank {3}, Row {4}, Col {5}", cycles, cid, addr.rid, addr.bid, addr.rowid, addr.colid);*/ //stats bank_stat.cmd_activate.Collect(); bank_stat.utilization.Collect(timing.tRCD); //shadow row-buffer id meta_mctrl.sched.count_queueing(cmd, pid_rowid_per_procrankbank[addr.rid, addr.bid]); shadow_rowid_per_procrankbank[cmd.pid, addr.rid, addr.bid] = addr.rowid; rowid_per_procrankbank[addr.rid, addr.bid] = addr.rowid; pid_rowid_per_procrankbank[addr.rid, addr.bid] = cmd.req.pid; break; case Cmd.TypeEnum.PRECHARGE: precharge(addr); /*dbg = String.Format("@{0,6} DRAM PREC: Channel {1}, Rank {2}, Bank {3}, Row {4}, Col {5}", cycles, cid, addr.rid, addr.bid, addr.rowid, addr.colid);*/ //stats bank_stat.cmd_precharge.Collect(); bank_stat.utilization.Collect(timing.tRP); break; case Cmd.TypeEnum.READ: read(addr, cmd.req.pid); /*dbg = String.Format("@{0,6} DRAM READ: Channel {1}, Rank {2}, Bank {3}, Row {4}, Col {5}", cycles, cid, addr.rid, addr.bid, addr.rowid, addr.colid);*/ //writeback mode if (wb_mode && cmd.is_drain) { Dbg.Assert(reads_to_drain > 0); reads_to_drain--; } //stats bank_stat.cmd_read.Collect(); bank_stat.utilization.Collect(timing.tCL); bus_stat.access.Collect(); bus_stat.utilization.Collect(timing.tBL); // Console.Write("HERE\n"); meta_mctrl.sched.bus_interference_count(cmd); break; case Cmd.TypeEnum.WRITE: write(addr, cmd.req.pid); //writeback mode if (!wb_mode && cmd.is_drain) { Dbg.Assert(writes_to_drain > 0); writes_to_drain--; } else { mwbmode.issued_write_cmd(cmd); } //stats bank_stat.cmd_write.Collect(); bank_stat.utilization.Collect(timing.tCL); bus_stat.access.Collect(); bus_stat.utilization.Collect(timing.tBL); break; default: //should never get here throw new System.Exception("DRAM: Invalid Cmd."); } //Debug.WriteLine(dbg); }
public bool can_schedule_cmd(Cmd cmd) { //drain reads during the first part of the writeback mode if (wb_mode && reads_to_drain > 0) { if (cmd.type == Cmd.TypeEnum.WRITE) return false; } //drain writes right after the writeback mode if (!wb_mode && writes_to_drain > 0) { if (cmd.type == Cmd.TypeEnum.READ) return false; } //DRAM timing MemAddr addr = cmd.addr; switch (cmd.type) { case Cmd.TypeEnum.ACTIVATE: return can_activate(addr); case Cmd.TypeEnum.PRECHARGE: return can_precharge(addr); case Cmd.TypeEnum.READ: return can_read(addr); case Cmd.TypeEnum.WRITE: return can_write(addr); } //should never get here throw new System.Exception("DRAM: Invalid Cmd."); }
public virtual void issued_write_cmd(Cmd cmd){}
private Req __find_best_req(int r, int b) { //no need to search for request, already outstanding commands if (cmdqs[r, b].Count > 0) { return(null); } /*** find best request ***/ List <Req> rq = readqs[r, b]; List <Req> wq = writeqs[r, b]; if (rq.Count == 0 && wq.Count == 0) { return(null); } Req best_req = null; Cmd cmd = null; //find best writeback request if (wb_mode) { best_req = meta_mctrl.find_best_wb_req(wq); if (best_req != null) { //check if best writeback request is schedulable cmd = decode_req(best_req)[0]; if (!can_schedule_cmd(cmd)) { return(null); } return(best_req); } //writeq is empty: should we let reads bypass? if (!Config.mctrl.read_bypass) { return(null); } } //find best read request best_req = meta_mctrl.find_best_rd_req(rq); /*** row-hit bypass ***/ if (Config.mctrl.row_hit_bypass) { Req hit_req = rh_finder.find_best_req(rq); if (!meta_mctrl.is_row_hit(best_req) && hit_req != null) { Bank bank = chan.ranks[r].banks[b]; Dbg.Assert(bank.ts_act != -1); long ts_pre = bank.ts_act + timing.tRAS; long speculative_ts_pre = cycles + timing.tRTP; if (speculative_ts_pre <= ts_pre) { best_req = hit_req; } } } if (best_req == null) { return(null); } //check if best request is schedulable cmd = decode_req(best_req)[0]; if (!can_schedule_cmd(cmd)) { return(null); } return(best_req); }
public void tick() { //must be the very first thing that's done cycles++; // if (cycles % 1000000 == 0) // Console.WriteLine("{0} - {1} - {2}",Sim.MLPINC,Sim.MLPDEC,Sim.MLPINC - Sim.MLPDEC); meta_mctrl.tick(cid); wbthrottle.tick(); mwbmode.tick(cid); // if (cycles % 1000000 == 0) // { // Console.WriteLine("DRAM Read Access Times: {0}", DRAMRead); // Console.WriteLine("DRAM Write Access Times:{0}",DRAMWrite); // Console.WriteLine("NVM Read Access Times: {0}",NVMRead); // Console.WriteLine("NVM Write Access Times:{0}",NVMWrite); // DRAMRead=0; // DRAMWrite=0; // NVMRead =0; // NVMWrite=0; // } //load stats for (int p = 0; p < Config.N; p++) { //read load if (rload_per_proc[p] > 0) { Stat.mctrls[cid].rbinaryloadtick_per_proc[p].Collect(); } Stat.mctrls[cid].rloadtick_per_proc[p].Collect(rload_per_proc[p]); //write load if (wload_per_proc[p] > 0) { Stat.mctrls[cid].wbinaryloadtick_per_proc[p].Collect(); } Stat.mctrls[cid].wloadtick_per_proc[p].Collect(wload_per_proc[p]); } //busy/idle stats if (rload > 0) { read_loaded_time++; if (read_unloaded_time > 0) { //Stat.mctrls[cid].read_unloaded_time.Collect(read_unloaded_time); } read_unloaded_time = 0; } else { read_unloaded_time++; if (read_loaded_time > 0) { //Stat.mctrls[cid].read_loaded_time.Collect(read_loaded_time); } read_loaded_time = 0; } /*** writeback mode ***/ update_wb_mode(); /* * if (wb_mode && cid == 0) { * Console.WriteLine("==={0}==============================================", cycles); * Console.WriteLine("Reads to Drain: {0}", reads_to_drain); * Console.WriteLine("Writes Serviced: {0}", ((DecoupledWBFullServeN) mwbmode).serve_cnt[0]); * uint r = 0; * for (uint b = 0; b < bmax; b++) { * Console.Write("{0}\t", b); * foreach (Cmd cmd in cmdqs[r, b]) { * Console.Write("{0} {1}\t", cmd.type.ToString(), can_schedule_cmd(cmd)); * } * Console.WriteLine(); * } * } */ /*** clock factor ***/ if (cycles % Config.mem.clock_factor != 0) { return; } if ((Config.proc.cache_insertion_policy == "PFA") && (cycles % (6 * Config.mem.clock_factor) == 0)) { int indexi, indexj; for (indexi = 0; indexi < rmax; indexi++) { for (indexj = 0; indexj < bmax; indexj++) { Measurement.read_MLP_cal(ref readqs[indexi, indexj]); Measurement.write_MLP_cal(ref writeqs[indexi, indexj]); Measurement.MLP_cal(ref inflightqs[indexi, indexj]); } } } /*** serve completed request ***/ if (bus_q.Count > 0 && bus_q[0].ts <= cycles) { MemAddr addr = bus_q[0].addr; bus_q.RemoveAt(0); List <Req> inflight_q = inflightqs[addr.rid, addr.bid]; Dbg.Assert(inflight_q.Count > 0); Dbg.Assert(addr == inflight_q[0].addr); Req req = inflight_q[0]; inflight_q.RemoveAt(0); if (Config.proc.cache_insertion_policy == "PFA") { Measurement.NVMBankPidDeUpdate(req); } dequeue_req(req); } Cmd best_cmd = find_best_cmd(); Req best_req = find_best_req(); //nothing to issue if (best_cmd == null && best_req == null) { if (Config.proc.cache_insertion_policy == "PFA") { CheckBusConflict(); } return; } //arbitrate between command and request bool is_issue_req = false; if (best_req != null && best_cmd == null) { is_issue_req = true; } else if (best_req == null && best_cmd != null) { is_issue_req = false; } else { if (best_req == __better_req(best_cmd.req, best_req)) { is_issue_req = true; } else { is_issue_req = false; } } //issue command or request if (is_issue_req) { if (!best_req.migrated_request) { if (Config.proc.cache_insertion_policy == "RBLA") { RowStat.UpdateDict(RowStat.NVMDict, best_req, this); } else if (Config.proc.cache_insertion_policy == "PFA") { RowStat.UpdateDict(RowStat.NVMDict, best_req, this); // Measurement.NVMBankPidEnUpdate(best_req); } } if (Config.proc.cache_insertion_policy == "PFA") { Measurement.NVMBankPidEnUpdate(best_req); } issue_req(best_req); } else { issue_cmd(best_cmd); } if (Config.proc.cache_insertion_policy == "PFA") { CheckBusConflict(); } }
private void issue_cmd(Cmd cmd) { MemAddr addr = cmd.addr; /* * if (cid == 0 && wb_mode) { * Console.Write("@{0}\t", cycles - ts_start_wbmode); * for (uint b = 0; b < addr.bid; b++) { * Console.Write("{0,4}", "-"); * } * Console.Write("{0,4}", cmd.type.ToString()[0]); * for (uint b = addr.bid; b < bmax; b++) { * Console.Write("{0,4}", "-"); * } * Console.WriteLine(); * } */ List <Cmd> cmd_q = cmdqs[addr.rid, addr.bid]; Dbg.Assert(cmd == cmd_q[0]); cmd_q.RemoveAt(0); BankStat bank_stat = Stat.banks[addr.cid, addr.rid, addr.bid]; BusStat bus_stat = Stat.busses[addr.cid]; //writeback mode stats if (wb_mode) { if (cmd.type == Cmd.TypeEnum.READ) { rds_per_wb_mode++; } else if (cmd.type == Cmd.TypeEnum.WRITE) { wbs_per_wb_mode++; } } //string dbg; switch (cmd.type) { case Cmd.TypeEnum.ACTIVATE: activate(addr); /*dbg = String.Format("@{0,6} DRAM ACTI: Channel {1}, Rank {2}, Bank {3}, Row {4}, Col {5}", * cycles, cid, addr.rid, addr.bid, addr.rowid, addr.colid);*/ //stats bank_stat.cmd_activate.Collect(); bank_stat.utilization.Collect(timing.tRCD); //shadow row-buffer id shadow_rowid_per_procrankbank[cmd.pid, addr.rid, addr.bid] = addr.rowid; break; case Cmd.TypeEnum.PRECHARGE: precharge(addr); /*dbg = String.Format("@{0,6} DRAM PREC: Channel {1}, Rank {2}, Bank {3}, Row {4}, Col {5}", * cycles, cid, addr.rid, addr.bid, addr.rowid, addr.colid);*/ //stats bank_stat.cmd_precharge.Collect(); bank_stat.utilization.Collect(timing.tRP); break; case Cmd.TypeEnum.READ: read(addr); if (Config.proc.cache_insertion_policy == "PFA") { Measurement.NVM_bus_conflict_reset(cmd.req.pid); } /*dbg = String.Format("@{0,6} DRAM READ: Channel {1}, Rank {2}, Bank {3}, Row {4}, Col {5}", * cycles, cid, addr.rid, addr.bid, addr.rowid, addr.colid);*/ //writeback mode if (wb_mode && cmd.is_drain) { Dbg.Assert(reads_to_drain > 0); reads_to_drain--; } //stats bank_stat.cmd_read.Collect(); bank_stat.utilization.Collect(timing.tCL); bus_stat.access.Collect(); bus_stat.utilization.Collect(timing.tBL); break; case Cmd.TypeEnum.WRITE: write(addr); if (Config.proc.cache_insertion_policy == "PFA") { Measurement.NVM_bus_conflict_reset(cmd.req.pid); } /*dbg = String.Format("@{0,6} DRAM WRTE: Channel {1}, Rank {2}, Bank {3}, Row {4}, Col {5}", * cycles, cid, addr.rid, addr.bid, addr.rowid, addr.colid);*/ //writeback mode if (!wb_mode && cmd.is_drain) { Dbg.Assert(writes_to_drain > 0); writes_to_drain--; } else { mwbmode.issued_write_cmd(cmd); } //stats bank_stat.cmd_write.Collect(); bank_stat.utilization.Collect(timing.tCL); bus_stat.access.Collect(); bus_stat.utilization.Collect(timing.tBL); break; default: //should never get here throw new System.Exception("DRAM: Invalid Cmd."); } //Debug.WriteLine(dbg); }
private void issue_req(Req req) { //remove request from waiting queue List <Req> q = get_q(req); Dbg.Assert(q.Contains(req)); q.Remove(req); //add to inflight queue MemAddr addr = req.addr; List <Req> inflight_q = inflightqs[addr.rid, addr.bid]; Dbg.Assert(inflight_q.Count < inflight_q.Capacity); inflight_q.Add(req); // if (inflight_q.Count != 1) // Console.WriteLine("{0}",inflight_q.Count); //add to command queue List <Cmd> cmd_q = cmdqs[addr.rid, addr.bid]; Dbg.Assert(cmd_q.Count == 0); List <Cmd> new_cmd_q = decode_req(req); Dbg.Assert(new_cmd_q.Count > 0); cmd_q.AddRange(new_cmd_q); Cmd cmd = cmd_q[0]; Dbg.Assert(cmd == new_cmd_q[0]); //meta_mctrl meta_mctrl.issue_req(req); Dbg.Assert(cmd.req.addr.rowid == req.addr.rowid); //stats BankStat bstat = Stat.banks[addr.cid, addr.rid, addr.bid]; bstat.access.Collect(); if (cmd.type == Cmd.TypeEnum.PRECHARGE || cmd.type == Cmd.TypeEnum.ACTIVATE) { //bank stat bstat.row_miss.Collect(); bstat.row_miss_perproc[req.pid].Collect(); //proc stat if (cmd.req.type == ReqType.RD) { Stat.procs[req.pid].row_hit_rate_read.Collect(0); Stat.procs[req.pid].row_miss_read.Collect(); } else { Stat.procs[req.pid].row_hit_rate_write.Collect(0); Stat.procs[req.pid].row_miss_write.Collect(); } req.hit = 2; // Power Measurement: Sim.NVM_power_statistics(req.pid, req.migrated_request, req.type, false); // if (Config.proc.cache_insertion_policy == "PFA") { // if ((!req.migrated_request) && (req.type == ReqType.RD)) Measurement.NVMMissSetRowBufferChange(req); } } else { //bank stat bstat.row_hit.Collect(); bstat.row_hit_perproc[req.pid].Collect(); //proc stat if (cmd.req.type == ReqType.RD) { Stat.procs[req.pid].row_hit_rate_read.Collect(1); Stat.procs[req.pid].row_hit_read.Collect(); } else { Stat.procs[req.pid].row_hit_rate_write.Collect(1); Stat.procs[req.pid].row_hit_write.Collect(); } req.hit = 1; // Power Measurement: Sim.NVM_power_statistics(req.pid, req.migrated_request, req.type, true); // if (Config.proc.cache_insertion_policy == "PFA") { Measurement.NVMHitSetRowBufferChange(req); } } // if (req.type == ReqType.RD && (!req.migrated_request) ) // Dbg.Assert(cmd.type == Cmd.TypeEnum.READ); //issue command if (Config.proc.cache_insertion_policy == "PFA") { Measurement.NVMSetCorePrevRowid(req); } issue_cmd(cmd); }
public override void count_queueing(Cmd cmd) { if (cmd == null) return; Req req = cmd.req; MemCtrl mctrl = meta_mctrl.get_mctrl(req); ulong shadow_rowid = mctrl.shadow_rowid_per_procrankbank[req.pid, req.addr.rid, req.addr.bid]; ulong rowid = mctrl.rowid_per_procrankbank[req.addr.rid, req.addr.bid]; if (shadow_rowid == req.addr.rowid && rowid != req.addr.rowid) { t_interference_rhit[req.pid] += 150; } }
public virtual void issued_write_cmd(Cmd cmd) { }
public virtual void bus_interference_count(Cmd cmd) { return; }
public virtual void bus_interference_count(Cmd cmd) { return; }
public virtual void count_queueing(Cmd cmd) { if (cmd == null) return; return; }