public Req get_curr_req(Bank bank)
{
MemCtrl mc = bank.mc;
List<Req> inflight_q = mc.inflightqs[bank.rid, bank.bid];
if (inflight_q.Count == 0)
return null;
return inflight_q[inflight_q.Count - 1];
}
//constructor
public Rank(MemCtrl mc, Channel chan, uint rid, uint bmax)
{
this.cid = mc.cid;
this.rid = rid;
this.mc = mc;
this.bmax = bmax;
banks = new Bank[bmax];
for (uint i = 0; i < banks.Length; i++) {
banks[i] = new Bank(mc, this, i);
}
}
public bool proc_req_in_queue(int cur_proc, Bank bank)
{
MemCtrl mc = bank.mc;
List<Req> read_q = mc.readqs[bank.rid, bank.bid];
for (int i = 0; i < read_q.Count; i ++)
{
if (read_q[i].pid == cur_proc)
{
foreach (Req r in Sim.procs[read_q[i].pid].mshr)
{
if (r.block_addr == read_q[i].block_addr) r.interference_cycles ++;
}
}
}
for (int i = 0; i < read_q.Count; i ++)
{
if (Config.stride_prefetcher_on)
{
if (!read_q[i].is_prefetch && read_q[i].pid == cur_proc) return true;
}
else
{
if (read_q[i].pid == cur_proc) return true;
}
}
return false;
}
public List<Req> get_writeq(Bank bank)
{
MemCtrl mc = get_mctrl(bank);
return mc.writeqs[bank.rid, bank.bid];
}
public List<Req> get_readq(Bank bank)
{
MemCtrl mc = get_mctrl(bank);
return mc.readqs[bank.rid, bank.bid];
}
public MemCtrl get_mctrl(Bank bank)
{
if (!is_omniscient) {
Dbg.Assert(mctrl.cid == bank.cid);
return mctrl;
}
return mctrls[bank.cid];
}
public Cmd get_curr_served_req(Bank bank)
{
MemCtrl mc = bank.mc;
List<Cmd> cmd_q = mc.cmdqs[bank.rid, bank.bid];
if (cmd_q.Count == 0)
return null;
return cmd_q[0];
}
