protected override void DoCommandAction()
{
VHDLFile union = new VHDLFile("union_interface");
foreach (string vhdlFile in Modules)
{
VHDLParser p = new VHDLParser(vhdlFile);
foreach (VHDLParserEntity entity in p.GetEntities())
{
foreach (HDLEntitySignal signal in entity.InterfaceSignals)
{
int width = signal.MSB - signal.LSB + 1;
if (!union.Entity.HasSignal(signal.SignalName))
{
union.Entity.Add(signal.SignalName, width, Objects.PortMapper.MappingKind.External);
union.Entity.SetDirection(signal.SignalName, FPGA.FPGATypes.GetPortDirectionFromString(signal.SignalDirection));
}
else
{
union.Entity.SetSignalWidth(signal.SignalName, Math.Max(width, union.Entity.GetSignalWidth(signal.SignalName)));
}
}
}
}
OutputManager.WriteOutput("entity union_interface is port (");
OutputManager.WriteOutput(union.Entity.ToString());
OutputManager.WriteOutput("end union_interface;");
}
protected override void DoCommandAction()
{
OutputManager.WriteOutput("@REM build all modules");
string config = "config.vhd";
string configNone = "config_none.vhd";
OutputManager.WriteOutput("mv " + config + " " + configNone);
OutputManager.WriteOutput("");
foreach (string t in VHDLModules)
{
int index = t.IndexOf(':');
string partialArea = t.Substring(0, index);
string vhdlModule = t.Substring(index + 1, t.Length - (index + 1));
string ucfFile = partialArea + ".ucf";;
string blockerFile = partialArea + "_blocker.xdl";;
VHDLParser p = new VHDLParser(vhdlModule);
foreach (VHDLParserEntity entity in p.GetEntities())
{
string enumType = ("build_" + entity.EntityName + "_in_" + partialArea).ToUpper();
string moduleNCD = partialArea + entity.EntityName + ".ncd";
OutputManager.WriteOutput("xcopy /Y " + ucfFile + " partial_region.ucf");
OutputManager.WriteOutput("cat " + configNone + " | sed 's/NONE/" + enumType + "/g' > " + config);
OutputManager.WriteOutput("call partial top " + Path.GetFileName(blockerFile) + " instBUFG25");
OutputManager.WriteOutput("mv top_routed.ncd " + moduleNCD);
OutputManager.WriteOutput("xdl -ncd2xdl " + moduleNCD);
OutputManager.WriteOutput("");
}
}
OutputManager.WriteOutput("mv " + configNone + " " + config);
}
protected override void DoCommandAction()
{
Dictionary <string, List <int> > signalWidths;
Dictionary <string, string> directions;
List <Tuple <string, List <int> > > interfaces;
List <string> ifSignals;
List <string> signalsForInterface;
List <string> signalsDeclarationsForMappingAndKeep;
GetSignalList(PartialAreaName, false,
out signalWidths,
out directions,
out interfaces,
out ifSignals,
out signalsForInterface,
out signalsDeclarationsForMappingAndKeep);
if (PrintAttributeDeclaration)
{
OutputManager.WriteVHDLOutput("attribute s : string;");
OutputManager.WriteVHDLOutput("attribute keep : string;");
}
List <string> declaredSignalNames = new List <string>();
VHDLParser vhdlParser = new VHDLParser(VHDLModule);
foreach (VHDLParserEntity ent in vhdlParser.GetEntities())
{
OutputManager.WriteVHDLOutput("-- declaration of signals to connect module " + ent.EntityName);
for (int i = 0; i < ent.InterfaceSignals.Count; i++)
{
string signalName = ent.InterfaceSignals[i].SignalName;
if (!signalWidths.ContainsKey(signalName))
{
OutputManager.WriteVHDLOutput("-- could not map the module signal " + ent.InterfaceSignals[i].SignalName + " to a signal in the partial area");
}
else
{
int signalWidthOfSignalNameInPartialArea = signalWidths[signalName].Count;
string signalDecl = "signal " + ent.EntityName + "_" + signalName + "_" + PartialAreaName + " : std_logic_vector(" + (signalWidthOfSignalNameInPartialArea - 1) + " downto 0) := (others => '1');";
OutputManager.WriteVHDLOutput(signalDecl);
declaredSignalNames.Add(ent.EntityName + "_" + signalName + "_" + PartialAreaName);
}
}
OutputManager.WriteVHDLOutput("");
}
foreach (string signalName in declaredSignalNames)
{
OutputManager.WriteVHDLOutput("attribute s of " + signalName + " : signal is \"yes\";");
OutputManager.WriteVHDLOutput("attribute keep of " + signalName + " : signal is \"yes\";");
}
OutputManager.WriteVHDLOutput("");
}
private IEnumerable <string> GetEntities(string partialArea)
{
foreach (string mapping in ModulesPerArea.Where(str => str.StartsWith(partialArea + ":")))
{
string[] tupel = Regex.Split(mapping, partialArea + ":");
VHDLParser vhdlParser = new VHDLParser(tupel[1]);
foreach (VHDLParserEntity ent in vhdlParser.GetEntities())
{
yield return(ent.EntityName);
}
}
}
public IEnumerable <string> GetEnumTypeValues()
{
foreach (string pr in PartialAreaNames)
{
foreach (string vhdlFile in GetVHDLFilePaths(pr))
{
VHDLParser vhdlParser = new VHDLParser(vhdlFile);
foreach (VHDLParserEntity ent in vhdlParser.GetEntities())
{
string nextEnumValue = "build_" + ent.EntityName + "_in_" + pr;
yield return(nextEnumValue);
}
}
}
}
protected override void DoCommandAction()
{
// TODO move to parser
VHDLParser vhdlParser = new VHDLParser(VHDLModule);
foreach (VHDLParserEntity ent in vhdlParser.GetEntities())
{
OutputManager.WriteVHDLOutput("-- component declaration for module " + ent.EntityName);
OutputManager.WriteVHDLOutput("component " + ent.EntityName + " is port (");
for (int i = 0; i < ent.InterfaceSignals.Count; i++)
{
// weiter: invertieren und dann auch signal mapping bei instasntiierung abgleichen
OutputManager.WriteVHDLOutput("\t" + ent.InterfaceSignals[i].WholeSignalDeclaration + (i < ent.InterfaceSignals.Count - 1 ? ";" : ");"));
}
OutputManager.WriteVHDLOutput("end component;");
OutputManager.WriteVHDLOutput("");
}
}
protected override void DoCommandAction()
{
if (!File.Exists(VHDlFile))
{
throw new ArgumentException(VHDlFile + " does not exits");
}
//open,in,East,pr0,0;
VHDLParser parser = new VHDLParser(VHDlFile);
foreach (VHDLParserEntity entity in parser.GetEntities())
{
Dictionary <FPGA.FPGATypes.Direction, StringBuilder> interfaces = new Dictionary <FPGA.FPGATypes.Direction, StringBuilder>();
foreach (HDLEntitySignal signal in entity.InterfaceSignals.Where(s => s.MetaData != null))
{
if (!interfaces.ContainsKey(signal.MetaData.Direction))
{
interfaces.Add(signal.MetaData.Direction, new StringBuilder());
}
foreach (string csvString in GetCSVString(entity, signal, signal.MetaData.Direction))
{
interfaces[signal.MetaData.Direction].AppendLine(csvString);
}
}
foreach (HDLEntitySignal signal in entity.InterfaceSignals.Where(s => s.MetaData == null))
{
}
OutputManager.WriteOutput("############################################");
OutputManager.WriteOutput("# interface derived from entity " + entity.EntityName);
OutputManager.WriteOutput("############################################");
foreach (KeyValuePair <FPGA.FPGATypes.Direction, StringBuilder> tupel in interfaces)
{
OutputManager.WriteOutput("# " + tupel.Key);
OutputManager.WriteOutput(tupel.Value.ToString());
}
OutputManager.WriteOutput("############################################");
OutputManager.WriteOutput("# end of interface for entity " + entity.EntityName);
OutputManager.WriteOutput("############################################");
}
}
protected override void DoCommandAction()
{
if (PrintBegin)
{
OutputManager.WriteVHDLOutput("begin");
OutputManager.WriteVHDLOutput("");
}
string componentPrefix = "static_placeholder_";
// out parameters to UpdateSignalData
Dictionary <string, List <int> > signalWidths;
Dictionary <string, string> directions;
List <Tuple <string, List <int> > > interfaces;
List <string> ifSignals;
List <string> signalsForInterface;
List <string> signalsDeclarationsForMappingAndKeep;
GetSignalList(PartialAreaName, false, out signalWidths, out directions, out interfaces, out ifSignals, out signalsForInterface, out signalsDeclarationsForMappingAndKeep);
// TODO move to parser
VHDLParser vhdlParser = new VHDLParser(VHDLModule);
foreach (VHDLParserEntity ent in vhdlParser.GetEntities())
{
OutputManager.WriteVHDLOutput("-- conditional instantiation of module " + ent.EntityName + " in partial area " + PartialAreaName);
string enumType = "build_" + ent.EntityName + "_in_" + PartialAreaName;
enumType = enumType.ToUpper();
OutputManager.WriteVHDLOutput("mod_sel_build_" + ent.EntityName + "_in_" + PartialAreaName + ": if module_selector = " + enumType + " generate");
OutputManager.WriteVHDLOutput("");
string prefix = ent.EntityName + "_";
//String module_name = this.ModulePrefix + this.PartialAreaNames;
string placeHolderName = componentPrefix + PartialAreaName;
OutputManager.WriteVHDLOutput("\t" + "-- the instantiation of the placeholder for the static system");
OutputManager.WriteVHDLOutput("\t" + "inst_" + componentPrefix + PartialAreaName + " : " + placeHolderName + " port map (");
for (int j = 0; j < interfaces.Count; j++)
{
string mapping = "\t" + "\t" + interfaces[j].Item1 + " => " + prefix + interfaces[j].Item1 + "_" + PartialAreaName + (j < interfaces.Count - 1 ? "," : "");
OutputManager.WriteVHDLOutput(mapping);
}
OutputManager.WriteVHDLOutput("\t" + ");");
OutputManager.WriteVHDLOutput("\t" + "-- the instantiation of module " + ent.EntityName);
OutputManager.WriteVHDLOutput("\t" + "inst_" + PartialAreaName + "_" + ent.EntityName + " : " + ent.EntityName + " port map (");
List <string> mappings = new List <string>();
for (int j = 0; j < ent.InterfaceSignals.Count; j++)
{
HDLEntitySignal s = ent.InterfaceSignals[j];
bool signalWillBeMappedToPlaceHolderSignal = interfaces.Any(tupel => tupel.Item1.Equals(s.SignalName));
if (signalWillBeMappedToPlaceHolderSignal)
{
Tuple <string, List <int> > ifElement = interfaces.FirstOrDefault(tupel => tupel.Item1.Equals(s.SignalName));
string mapping = "\t" + "\t" + s.SignalName + " => " + prefix + ifElement.Item1 + "_" + PartialAreaName + s.Range;
mappings.Add(mapping);
}
else
{
// TODO #
string mapping = "\t" + "\t" + s.SignalName + " => " + s.SignalName;
mappings.Add(mapping);
}
}
for (int j = 0; j < mappings.Count; j++)
{
OutputManager.WriteVHDLOutput(mappings[j] + (j < mappings.Count - 1 ? "," : ""));
}
OutputManager.WriteVHDLOutput("\t" + ");");
OutputManager.WriteVHDLOutput("");
OutputManager.WriteVHDLOutput("end generate;");
OutputManager.WriteVHDLOutput("");
}
if (CloseArchitecture)
{
OutputManager.WriteVHDLOutput("end architecture;");
}
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);
DesignParser parser = DesignParser.CreateDesignParser(XDLFile);
XDLContainer container = new XDLContainer();
parser.ParseDesign(container, this);
VHDLParser moduleParser = new VHDLParser(VHDLModule);
VHDLParserEntity ent = moduleParser.GetEntity(0);
Dictionary <int, List <Signal> > east = new Dictionary <int, List <Signal> >();
Dictionary <int, List <Signal> > west = new Dictionary <int, List <Signal> >();
double xCenter, yCenter;
TileSelectionManager.Instance.GetCenterOfSelection(t => TileSelectionManager.Instance.IsSelected(t.TileKey), out xCenter, out yCenter);
foreach (HDLEntitySignal signal in ent.InterfaceSignals)
{
foreach (XDLNet net in container.Nets.Where(n => n.Name.StartsWith(signal.SignalName) && ((XDLNet)n).HasIndex()).OrderBy(n => ((XDLNet)n).GetIndex()))
{
Tile fromTile;
Tile toTile;
GetSourceAndSink(container, net, out fromTile, out toTile);
GetSourceAndSink(container, net, out fromTile, out toTile);
Tile innerTile = null;
Tile outerTile = null;
string signalMode = "";
if (!TileSelectionManager.Instance.IsSelected(fromTile.TileKey) && TileSelectionManager.Instance.IsSelected(toTile.TileKey))
{
innerTile = toTile;
outerTile = fromTile;
signalMode = "in";
}
else if (TileSelectionManager.Instance.IsSelected(fromTile.TileKey) && !TileSelectionManager.Instance.IsSelected(toTile.TileKey))
{
outerTile = toTile;
innerTile = fromTile;
signalMode = "out";
}
else
{
throw new ArgumentException("Expecting an instance inside the current selection");
}
FPGATypes.InterfaceDirection dir = outerTile.TileKey.X < (int)xCenter ? FPGATypes.InterfaceDirection.East : FPGATypes.InterfaceDirection.West;
Dictionary <int, List <Signal> > signalCollection = dir.Equals(FPGATypes.InterfaceDirection.East) ? east : west;
if (!signalCollection.ContainsKey(innerTile.TileKey.Y))
{
signalCollection.Add(innerTile.TileKey.Y, new List <Signal>());
}
Signal s = new Signal();
s.Column = -1;
s.SignalDirection = dir;
s.SignalMode = signalMode;
s.SignalName = net.Name;
signalCollection[innerTile.TileKey.Y].Add(s);
// weiter: vor verlaesst das gummiband die partielle flaeche?
// vektoren nach osten oder westen?
}
}
bool interleaveEast = east.Any(t => t.Value.Count > 4);
bool interleaveWest = west.Any(t => t.Value.Count > 4);
Dictionary <FPGA.FPGATypes.Direction, Dictionary <int, List <Signal> > > interfaces = new Dictionary <FPGATypes.Direction, Dictionary <int, List <Signal> > >();
interfaces.Add(FPGATypes.Direction.East, new Dictionary <int, List <Signal> >());
interfaces[FPGATypes.Direction.East][0] = new List <Signal>();
interfaces[FPGATypes.Direction.East][1] = new List <Signal>();
interfaces.Add(FPGATypes.Direction.West, new Dictionary <int, List <Signal> >());
interfaces[FPGATypes.Direction.West][0] = new List <Signal>();
interfaces[FPGATypes.Direction.West][1] = new List <Signal>();
if (interleaveEast)
{
int columnIndex = 0;
foreach (KeyValuePair <int, List <Signal> > tupel in east)
{
foreach (Signal s in tupel.Value)
{
Signal copy = new Signal(s.SignalName, s.SignalMode, s.SignalDirection, "", columnIndex);
interfaces[FPGATypes.Direction.East][columnIndex].Add(copy);
columnIndex++;
columnIndex %= 2;
}
}
}
//ent.InterfaceSignals
}