public short ReadWord(int address) { address &= 0x00FFFFFF; int maskedAddr; if (address < 0x400000) { return((short)((RomData[address] << 8) | RomData[address + 1])); } if (address >= 0xE00000) // Work RAM { maskedAddr = address & 0xFFFE; return((short)((Ram[maskedAddr] << 8) | Ram[maskedAddr + 1])); } if (address >= 0xC00000 && address < 0xC00010) { return((short)VDP.ReadVdp(address & 0x0E)); } if (address >= 0xA10000 && address <= 0xA1001F) { return((sbyte)ReadIO(address)); } if (address == 0xA11100) // Z80 BUS status { return((short)(M68000HasZ80Bus && Z80Reset == false ? 0x0000 : 0x0100)); } Console.WriteLine("UNHANDLED READW {0:X6}", address); return(0x7DCD); }
public sbyte ReadByte(int address) { address &= 0x00FFFFFF; if (address < 0x200000) { return((sbyte)RomData[address]); } if (address < 0x400000) { if (SaveRamEnabled && address >= SaveRamStartOffset && address < SaveRamEndOffset) { if (SaveRamEveryOtherByte) { return((sbyte)SaveRAM[(address - SaveRamStartOffset) >> 1]); } else { return((sbyte)SaveRAM[address - SaveRamStartOffset]); } } return((sbyte)RomData[address]); } if (address >= 0xE00000) { return((sbyte)Ram[address & 0xFFFF]); } if (address == 0xA11100) // Z80 BUS status { //Console.WriteLine("QUERY z80 bus status. 68000 can access? " + (M68000HasZ80Bus && Z80Reset == false)); return((sbyte)(M68000HasZ80Bus && Z80Reset == false ? 0 : 1)); } if (address >= 0xA10000 && address <= 0xA1001F) { return((sbyte)ReadIO(address)); } if ((address & 0xFF0000) == 0xA00000) { return((sbyte)ReadMemoryZ80((ushort)(address & 0x7FFF))); } if (address >= 0xC00000 && address < 0xC00010) { //Console.WriteLine("byte-reading the VDP. someone is probably stupid."); ushort value = VDP.ReadVdp(address & 0x0E); if ((address & 1) == 0) // read MSB { return((sbyte)(value >> 8)); } return((sbyte)value); // read LSB } Console.WriteLine("UNHANDLED READB {0:X6}", address); return(0x7D); }
public void Restart() { if (!(Global.Emulator is SMS)) { Close(); return; } vdp = (Global.Emulator as SMS).Vdp; UpdateValues(); }
private void SyncState(Serializer ser) { ser.BeginSection("Coleco"); Cpu.SyncState(ser); VDP.SyncState(ser); PSG.SyncState(ser); ser.Sync("RAM", ref Ram, false); ser.Sync("Frame", ref frame); ser.Sync("LagCount", ref _lagCount); ser.Sync("IsLag", ref _isLag); ser.EndSection(); }
public void WriteMemoryZ80(ushort address, byte value) { if (address < 0x4000) { //Console.WriteLine("write z80 memory {0:X4}: {1:X2}",address, value); Z80Ram[address & 0x1FFF] = value; return; } if (address >= 0x4000 && address < 0x6000) { //Console.WriteLine(" === Z80 WRITES YM2612 {0:X4}:{1:X2} ===",address, value); YM2612.Write(address & 3, value, SoundCPU.TotalExecutedCycles); return; } if (address < 0x6100) { BankRegion >>= 1; BankRegion |= (value & 1) << 23; BankRegion &= 0x00FF8000; //Console.WriteLine("Bank pointing at {0:X8}",BankRegion); return; } if (address >= 0x7F00 && address < 0x7F20) { switch (address & 0x1F) { case 0x00: case 0x02: VDP.WriteVdpData((ushort)((value << 8) | value)); return; case 0x04: case 0x06: VDP.WriteVdpControl((ushort)((value << 8) | value)); return; case 0x11: case 0x13: case 0x15: case 0x17: PSG.WritePsgData(value, SoundCPU.TotalExecutedCycles); return; } } if (address >= 0x8000) { WriteByte(BankRegion | (address & 0x7FFF), (sbyte)value); return; } Console.WriteLine("UNHANDLED Z80 WRITE {0:X4}:{1:X2}", address, value); }
public void WriteWord(int address, short value) { address &= 0x00FFFFFF; if (address >= 0xE00000) // Work RAM { //Console.WriteLine("MEM[{0:X4}] change to {1:X4}", address & 0xFFFF, value); Ram[(address & 0xFFFF) + 0] = (byte)(value >> 8); Ram[(address & 0xFFFF) + 1] = (byte)value; return; } if (address >= 0xC00000) { switch (address & 0x1F) { case 0x00: case 0x02: VDP.WriteVdpData((ushort)value); return; case 0x04: case 0x06: VDP.WriteVdpControl((ushort)value); return; } } if (address == 0xA11100) // Z80 BUSREQ { M68000HasZ80Bus = (value & 0x100) != 0; //Console.WriteLine("68000 has the z80 bus: " + M68000HasZ80Bus); return; } if (address == 0xA11200) // Z80 RESET { Z80Reset = (value & 0x100) == 0; if (Z80Reset) { SoundCPU.SoftReset(); } //Console.WriteLine("z80 reset: " + Z80Reset); return; } Console.WriteLine("UNHANDLED WRITEW {0:X6}:{1:X4}", address, value); }
public void WriteByte(int address, sbyte value) { address &= 0x00FFFFFF; if (address >= 0xE00000) // Work RAM { //Console.WriteLine("MEM[{0:X4}] change from {1:X2} to {2:X2}", address & 0xFFFF, Ram[address & 0xFFFF], value); Ram[address & 0xFFFF] = (byte)value; return; } if ((address & 0xFF0000) == 0xA00000) { WriteMemoryZ80((ushort)(address & 0x7FFF), (byte)value); return; } if (address >= 0xA10000 && address <= 0xA1001F) { WriteIO(address, value); return; } if (address == 0xA11100) { M68000HasZ80Bus = (value & 1) != 0; //Console.WriteLine("68000 has the z80 bus: " + M68000HasZ80Bus); return; } if (address == 0xA11200) // Z80 RESET { Z80Reset = (value & 1) == 0; if (Z80Reset) { SoundCPU.SoftReset(); } //Console.WriteLine("z80 reset: " + Z80Reset); return; } if (address >= 0xC00000 && address < 0xC00010) { // when writing to VDP in byte mode, the LSB is duplicated into the MSB VDP.WriteVdp(address & 0x1E, (ushort)((ushort)value | ((ushort)value << 8))); return; } if (address >= 0xC00011 && address <= 0xC00017 && (address & 1) != 0) { PSG.WritePsgData((byte)value, SoundCPU.TotalExecutedCycles); return; } if (SaveRamEnabled && address >= SaveRamStartOffset && address < SaveRamEndOffset) { if (SaveRamEveryOtherByte) { SaveRAM[(address - SaveRamStartOffset) >> 1] = (byte)value; } else { SaveRAM[address - SaveRamStartOffset] = (byte)value; } SaveRamModified = true; return; } if (EepromEnabled && (address == SclAddr || address == SdaInAddr)) { WriteByteEeprom(address, (byte)value); return; } Console.WriteLine("UNHANDLED WRITEB {0:X6}:{1:X2}", address, value); }