TCLObject FileName(TCLObject source)
{
if (source?._value != null)
{
return(TCLEscaping.Default.FileName(source._value));
}
return(source);
}
/// <summary>
/// <para>
/// Connect nets and pins to debug port channels<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: connect_debug_port [-channel_start_index <arg>] [-quiet] [-verbose] <port> <nets>...
/// <br/>
/// <para>
/// Connects a signal from the netlist design to a port on an ILA debug core that was added to the<br/>
/// design using the create_debug_core command. The signal can either be connected to a<br/>
/// specific channel index on the port, or simply connected to an available channel on the port.<br/>
/// If you try to connect too many signals to a port, or there are not enough channels to support the<br/>
/// connection, the tool will return an error.<br/>
/// Additional ports can be added to a debug core through the use of the create_debug_port<br/>
/// command, and you can increase the available channels on an existing port with the<br/>
/// set_property port_width command. See the examples below.<br/>
/// You can disconnect signals from ports using the disconnect_debug_port command.<br/>
/// When the debug core has been defined and connected, you can implement the debug core as a<br/>
/// block for inclusion in the netlist design. Use the implement_debug_core command to<br/>
/// implement the core.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// </para>
/// <br/>
/// <para>
/// The following example creates a new PROBE port on the myCore debug core, increases the<br/>
/// PORT_WIDTH property of the port in order to prepare it to receive the number of signals to be<br/>
/// connected, and connects signals to the port starting at the third channel position (index 2).<br/>
/// create_debug_port myCore PROBE<br/>
/// set_property PORT_WIDTH 8 [get_debug_ports myCore/PROBE1]<br/>
/// connect_debug_port myCore/PROBE1 [get_nets [list m0_ack_o m0_cyc_i \<br/>
/// m0_err_o m0_rty_o m0_stb_i m0_we_i ]] -channel_start_index 2<br/>
/// Note: If you specify too many nets to connect to the available channels on the port, the tool will return an<br/>
/// error and will not connect the ports.<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 201<br/>
/// </para>
/// </summary>
/// <param name="port">(Required) Debug port name</param>
/// <param name="nets">(Required) List of nets or pins</param>
/// <param name="channel_start_index">(Optional) Connect nets starting at channel index</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL connect_debug_port(TCLObject port, TCLObjectList nets, String channel_start_index = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: connect_debug_port [-channel_start_index <arg>] [-quiet] [-verbose] <port> <nets>...
_tcl.Entry(_builder.connect_debug_port(port, nets, channel_start_index, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Create a new I/O port interface<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: create_interface [-parent <arg>] [-quiet] [-verbose] <name>
/// <br/>
/// <para>
/// Creates a new interface for grouping scalar or differential I/O ports.<br/>
/// </para>
/// <br/>
/// <para>
/// Create a new USB interface:<br/>
/// create_interface USB0<br/>
/// Create an Ethernet interface within the specified parent interface:<br/>
/// create_interface -parent Top_Int ENET0<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 314<br/>
/// </para>
/// </summary>
/// <param name="name">(Required) Name for new I/O port interface</param>
/// <param name="parent">(Optional) Assign new interface to this parent interface</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
/// <returns>new interface object</returns>
public TTCL create_interface(TCLObject name, String parent = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: create_interface [-parent <arg>] [-quiet] [-verbose] <name>
_tcl.Entry(_builder.create_interface(name, parent, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Create scalar or bus port<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: create_port -direction <arg> [-from <arg>] [-to <arg>] [-diff_pair] [-interface <arg>] [-quiet] [-verbose] <name> [<negative_name>]
/// <br/>
/// <para>
/// Creates a port and specifies such parameters as direction, width, single-ended or differential, and<br/>
/// optionally assigns it to an existing interface. New ports are added at the top-level of the design<br/>
/// hierarchy.<br/>
/// Bus ports can be created with increasing or decreasing bus indexes, using negative and positive<br/>
/// index values.<br/>
/// The create_port command can be used to create a new port in an I/O Planning project, or<br/>
/// while editing the netlist of an open Synthesized or Implemented design.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// Netlist editing changes the in-memory view of the netlist in the current design. It does not<br/>
/// change the files in the source fileset, or change the persistent design on the disk. Changes made<br/>
/// to the netlist may be saved to a design checkpoint using the write_checkpoint command, or<br/>
/// may be exported to a netlist file such as Verilog, VHDL, or EDIF, using the appropriate write_*<br/>
/// command.<br/>
/// Note: Netlist editing is not allowed on the elaborated RTL design.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example creates a new input port, named PORT0:<br/>
/// create_port -direction IN PORT0<br/>
/// The following example creates a new interface called Group1, and then creates a four-bit,<br/>
/// differential pair output bus using the specified interface. Since the bus ports are defined as<br/>
/// differential pairs, and only <name> is specified, the negative side ports are automatically named<br/>
/// D_BUS_N:<br/>
/// create_interface Group1<br/>
/// create_port -direction OUT -from 0 -to 3 -diff_pair -interface Group1 D_BUS<br/>
/// Note: This command results in the creation of eight ports: D_BUS[0] D_BUS_N[0] D_BUS[1] D_BUS_N[1]<br/>
/// D_BUS[2] D_BUS_N[2] D_BUS[3] D_BUS_N[3]<br/>
/// With only <name> specified, the following example creates differential pair output ports named<br/>
/// data and data_N.<br/>
/// create_port -direction OUT -diff_pair data<br/>
/// With both <name> and <negative_name> specified, the following example creates differential<br/>
/// pair output ports named data_P and data_N.<br/>
/// create_port -direction OUT -diff_pair data_P data_N<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 335<br/>
/// </para>
/// </summary>
/// <param name="direction">(Required) Direction of port. Valid arguments are IN, OUT and INOUT</param>
/// <param name="name">(Required) Name of the port</param>
/// <param name="from">(Optional) Beginning index of new bus</param>
/// <param name="to">(Optional) Ending index of new bus</param>
/// <param name="diff_pair">(Optional) Create differential pair of ports</param>
/// <param name="interface">(Optional) Assign new port to this interface</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
/// <param name="negative_name">(Optional) Optional negative name of a diff-pair</param>
/// <returns>list of port objects that were created</returns>
public TTCL create_port(String direction, TCLObject name, String from = null, String to = null, bool?diff_pair = null, String @interface = null, bool?quiet = null, bool?verbose = null, TCLObject negative_name = null)
{
// TCL Syntax: create_port -direction <arg> [-from <arg>] [-to <arg>] [-diff_pair] [-interface <arg>] [-quiet] [-verbose] <name> [<negative_name>]
_tcl.Entry(_builder.create_port(direction, name, from, to, diff_pair, @interface, quiet, verbose, negative_name));
return(_tcl);
}
/// <summary>
/// <para>
/// Deletes a list of available QoR suggestions<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: delete_qor_suggestions [-quiet] [-verbose] [<IDs>]
/// <br/>
/// <para>
/// Removes QoR suggestion objects that are currently in memory. Suggestion objects are generated<br/>
/// running the report_qor_suggestion command, without specifying -of_objects, and by<br/>
/// reading an RQS file using the read_qor_suggestions command. You can get QoR objects by<br/>
/// using the get_qor_suggestions command.<br/>
/// </para>
/// <br/>
/// <para>
/// The following deletes all the suggestion objects in memory:<br/>
/// delete_qor_suggestions [get_qor_suggestions]<br/>
/// The following deletes only the Utilization suggestions:<br/>
/// delete_qor_suggestions [get_qor_suggestions -filter {CATEGORY==Utilization}]<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 470<br/>
/// </para>
/// </summary>
/// <param name="IDs">(Required) Match suggestion names against given names</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL delete_qor_suggestions(TCLObject IDs, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: delete_qor_suggestions [-quiet] [-verbose] [<IDs>]
_tcl.Entry(_builder.delete_qor_suggestions(IDs, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Read QoR Suggestions from the given file<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: read_qor_suggestions [-quiet] [-verbose] <file>
/// <br/>
/// <para>
/// Read the specified file and extract the QoR suggestions from the file.<br/>
/// This command returns the name of the QoR file read, or returns an error if it fails.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example reads the QoR suggestions from the specified file, and then reports the<br/>
/// QoR suggestions in the open design:<br/>
/// read_qor_suggestions C:/Data/qor_results.rqs<br/>
/// report_qor_suggestions -of_objects [get_qor_suggestions]<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1174<br/>
/// </para>
/// </summary>
/// <param name="file">
/// <para>
/// (Required)<br/>
/// QoR suggestions file Values: Path to the QoR suggestions<br/>
/// file, typically ending with .rqs.<br/>
/// </para>
/// </param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL read_qor_suggestions(TCLObject file, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: read_qor_suggestions [-quiet] [-verbose] <file>
_tcl.Entry(_builder.read_qor_suggestions(file, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Generate HDL wrapper for the specified source<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: make_wrapper [-top] [-testbench] [-inst_template] [-fileset <arg>] [-import] [-force] [-quiet] [-verbose] <files>
/// <br/>
/// <para>
/// Create a Verilog or VHDL wrapper for instantiating a sub-design into the project.<br/>
/// The make_wrapper command will create a wrapper for Embedded Processor Designs from the<br/>
/// IP integrator of the Vivado Design Suite, or any IP integrator block design, as well as DSP<br/>
/// modules created in System Generator or MathWorks MatLab.<br/>
/// You can generate a wrapper to make the sub-design the top-level of a stand-alone design, or for<br/>
/// instantiating a sub-design into an existing design. You can also generate a wrapper for a<br/>
/// simulation test bench of System Generator sub-designs.<br/>
/// Note: The wrapper is generated in Verilog or VHDL according to the TARGET_LANGUAGE property on the<br/>
/// project.<br/>
/// The command returns information related to the creation of the wrappers, or returns an error if it<br/>
/// fails.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// </para>
/// <br/>
/// <para>
/// The following example creates the instantiation template to integrate the specified IP integrator<br/>
/// block design into the design hierarchy of the current project:<br/>
/// make_wrapper -inst_template -fileset [get_filesets sources_1] \<br/>
/// -files [get_files C:/Data/design_1/design_1.bd]<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1059<br/>
/// </para>
/// </summary>
/// <param name="files">(Required) Source file for which the wrapper needs to be generated</param>
/// <param name="top">(Optional) Create a top-level wrapper for the specified source</param>
/// <param name="testbench">(Optional) Create a testbench for the specified source</param>
/// <param name="inst_template">
/// <para>
/// (Optional)<br/>
/// Create an instantiation template for the specified source.<br/>
/// The template will not be added to the project and will be<br/>
/// generated for reference purposes only.<br/>
/// </para>
/// </param>
/// <param name="fileset">(Optional) Fileset name</param>
/// <param name="import">(Optional) Import generated wrapper to the project</param>
/// <param name="force">(Optional) Overwrite existing source(s)</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL make_wrapper(TCLObject files, bool?top = null, bool?testbench = null, bool?inst_template = null, String fileset = null, bool?import = null, bool?force = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: make_wrapper [-top] [-testbench] [-inst_template] [-fileset <arg>] [-import] [-force] [-quiet] [-verbose] <files>
_tcl.Entry(_builder.make_wrapper(files, top, testbench, inst_template, fileset, import, force, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// (User-written application) Convert all provided NGC files to a supported format<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: convert_ngc [-output_dir <arg>] [-format <arg>] [-add_to_project] [-force] [-quiet] [-verbose] <files>
/// <br/>
/// <para>
/// Converts provided NGC files to a supported format.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example will convert test.ngc to test.edn, with verbose messaging. The<br/>
/// test.edn file will be added to the current open project:<br/>
/// convert_ngc ./test.ngc -add_to_project -verbose<br/>
/// The following example will convert test.ngc to test.edn. The test.edn file will be placed<br/>
/// in the ./output directory. If ./output/test.edn exists it will be replaced:<br/>
/// convert_ngc ./test.ngc -output_dir output -force<br/>
/// The following example converts all NGC files in the current directory and in all sub-directories:<br/>
/// convert_ngc [ glob ./**/*.ngc ] [ glob ./*.ngc ]<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 213<br/>
/// </para>
/// </summary>
/// <param name="files">(Required) A list of NGC files to convert</param>
/// <param name="output_dir">
/// <para>
/// (Optional)<br/>
/// Directory to place all output, else the output is placed at<br/>
/// location of NGC file Default: Script output directory path<br/>
/// </para>
/// </param>
/// <param name="format">
/// <para>
/// (Optional)<br/>
/// Accepts 'Verilog' or 'EDIF' (Default: EDIF), specifies the<br/>
/// desired output format Default: EDIF<br/>
/// </para>
/// </param>
/// <param name="add_to_project">
/// <para>
/// (Optional)<br/>
/// Adds the output files to the current project, if no project is<br/>
/// open, then this option does nothing<br/>
/// </para>
/// </param>
/// <param name="force">
/// <para>
/// (Optional)<br/>
/// Force overwriting of files that already exist on disk, replaces<br/>
/// files in project if add_to_project switch was specified<br/>
/// </para>
/// </param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
/// <returns>None</returns>
public TTCL convert_ngc(TCLObject files, String output_dir = null, String format = null, bool?add_to_project = null, bool?force = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: convert_ngc [-output_dir <arg>] [-format <arg>] [-add_to_project] [-force] [-quiet] [-verbose] <files>
_tcl.Entry(_builder.convert_ngc(files, output_dir, format, add_to_project, force, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Save peripheral component to the disk.<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: write_peripheral [-quiet] [-verbose] <peripheral>
/// <br/>
/// <para>
/// Write the specified AXI peripheral object to disk in the form of the component.xml file. The<br/>
/// peripheral is written to the repository location specified by the create_peripheral<br/>
/// command, under the name specified at creation.<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1876<br/>
/// </para>
/// </summary>
/// <param name="peripheral">(Required) Peripheral object</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL write_peripheral(TCLObject peripheral, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: write_peripheral [-quiet] [-verbose] <peripheral>
_tcl.Entry(_builder.write_peripheral(peripheral, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Generate output products for peripheral object.<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: generate_peripheral [-driver] [-example_design] [-bfm_example_design] [-debug_hw_example_design] [-enable_interrupt] [-force] [-quiet] [-verbose] <peripheral>
/// <br/>
/// <para>
/// Generate the output products for the specified peripheral object. The output products are<br/>
/// written to the IP repository location specified when the IP is created by the<br/>
/// create_peripheral command, under the name of the IP as specified at creation.<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 545<br/>
/// </para>
/// </summary>
/// <param name="peripheral">(Required) peripheral object</param>
/// <param name="driver">(Optional) Generate driver for peripheral.</param>
/// <param name="example_design">(Optional) Generate all supported example designs for peripheral.</param>
/// <param name="bfm_example_design">(Optional) Generate bfm simulation example design for peripheral.</param>
/// <param name="debug_hw_example_design">(Optional) Generate debug hardware example design for peripheral.</param>
/// <param name="enable_interrupt">(Optional) Generate peripheral with interrupt suppport.</param>
/// <param name="force">(Optional) Overwrite the existing IP in the repository.</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL generate_peripheral(TCLObject peripheral, bool?driver = null, bool?example_design = null, bool?bfm_example_design = null, bool?debug_hw_example_design = null, bool?enable_interrupt = null, bool?force = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: generate_peripheral [-driver] [-example_design] [-bfm_example_design] [-debug_hw_example_design] [-enable_interrupt] [-force] [-quiet] [-verbose] <peripheral>
_tcl.Entry(_builder.generate_peripheral(peripheral, driver, example_design, bfm_example_design, debug_hw_example_design, enable_interrupt, force, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Write debug probes to a file<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: write_debug_probes [-cell <arg>] [-no_partial_ltxfile] [-force] [-quiet] [-verbose] <file>
/// <br/>
/// <para>
/// Writes a Vivado Design Suite logic analyzer probes file containing ILA debug cores and signal<br/>
/// probes added to the current design. The debug probes data file typically has a .ltx file<br/>
/// extension.<br/>
/// ILA cores are added to the design using the create_debug_core command. ILA probes are<br/>
/// added to the design using the create_debug_port command, and connected to nets in your<br/>
/// design using the connect_debug_port command.<br/>
/// The specific information and use of the debug probes file is described in the Vivado Design Suite<br/>
/// User Guide: Vivado Programming and Debugging (UG908).<br/>
/// </para>
/// <br/>
/// <para>
/// The following example write a debug probe file from the current design:<br/>
/// write_debug_probes C:/Data/designProbes.ltx<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1842<br/>
/// </para>
/// </summary>
/// <param name="file">(Required) Debug probes file name (default extension is .ltx)</param>
/// <param name="cell">(Optional) Hierarchical name of the Reconfigurable Partition Cell</param>
/// <param name="no_partial_ltxfile">(Optional) Do not generate partial LTX files</param>
/// <param name="force">(Optional) Overwrite existing file</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
/// <returns>name of the output file</returns>
public TTCL write_debug_probes(TCLObject file, String cell = null, bool?no_partial_ltxfile = null, bool?force = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: write_debug_probes [-cell <arg>] [-no_partial_ltxfile] [-force] [-quiet] [-verbose] <file>
_tcl.Entry(_builder.write_debug_probes(file, cell, no_partial_ltxfile, force, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Apply trigger at startup init values to an ILA core in the design<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: apply_hw_ila_trigger [-ila_cell <arg>] [-quiet] [-verbose] [<file>]
/// <br/>
/// <para>
/// Apply a trigger configuration file to the bitstream of a design, to support ILA trigger at startup.<br/>
/// This command is used to configure the trigger settings of an ILA core in a design bitstream (.bit)<br/>
/// file, so that the ILA debug core is armed to trigger on events immediately after device<br/>
/// configuration and startup. This allows data to be captured from the earliest stages of device<br/>
/// activity, which would not be possible through the use of the Hardware Manager feature of the<br/>
/// Vivado Design Suite, and the run_hw_ila command.<br/>
/// The apply_hw_ila_trigger command reads a trigger configuration file written by<br/>
/// run_hw_ila -file and applies the various trigger settings to the ILA core in the implemented<br/>
/// design. The trigger configuration for the ILA core then become part of the bitstream written by<br/>
/// write_bitstream, that is used to program the Xilinx FPGA device.<br/>
/// The process for using the trigger at startup feature includes the following steps:<br/>
/// 1. From the Hardware Manager, use run_hw_ila -file to export the trigger register map<br/>
/// file for the ILA core.<br/>
/// 2. Open the implemented design, or the implemented design checkpoint.<br/>
/// 3. Use the apply_hw_ila_trigger command to apply the trigger settings to the in-memory<br/>
/// design.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// 4. Use the write_bitstream command to write the bitstream with the applied trigger<br/>
/// configuration file.<br/>
/// Note: Be sure to use the write_bitstream command, and not the Flow Navigator commands in the<br/>
/// Vivado IDE.<br/>
/// 5. Return to the Hardware Manager, and use program_hw_device to program the hw_device<br/>
/// using the new bitstream file.<br/>
/// Once programmed, the new ILA core should immediately arm at startup. In the Vivado logic<br/>
/// analyzer feature, you should see the "Trigger Capture Status" for the ILA core is now populated<br/>
/// with captured data samples if trigger events or capture conditions have occurred. Refer to the<br/>
/// Vivado Design Suite User Guide: Vivado Programming and Debugging (UG908) for more information.<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 106<br/>
/// </para>
/// </summary>
/// <param name="ila_cell">(Optional) Apply trigger settings to this ila cell</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
/// <param name="file">(Optional) ILA startup trigger settings file</param>
public TTCL apply_hw_ila_trigger(String ila_cell = null, bool?quiet = null, bool?verbose = null, TCLObject file = null)
{
// TCL Syntax: apply_hw_ila_trigger [-ila_cell <arg>] [-quiet] [-verbose] [<file>]
_tcl.Entry(_builder.apply_hw_ila_trigger(ila_cell, quiet, verbose, file));
return(_tcl);
}
/// <summary>
/// <para>
/// Get a list of debug ports in the current design<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: get_debug_ports [-filter <arg>] [-of_objects <args>] [-regexp] [-nocase] [-quiet] [-verbose] [<patterns>]
/// <br/>
/// <para>
/// Gets a list of ports defined on ILA debug cores in the current project that match a specified<br/>
/// search pattern. The default command gets a list of all debug ports in the project.<br/>
/// Debug ports are defined when ILA debug cores are created with the create_debug_core<br/>
/// command. Ports can be added to existing debug cores with the create_debug_port<br/>
/// command.<br/>
/// Note: To improve memory and performance, the get_* commands return a container list of a single type<br/>
/// of objects (e.g. cells, nets, pins, or ports). You can add new objects to the list (using lappend for instance),<br/>
/// but you can only add the same type of object that is currently in the list. Adding a different type of object,<br/>
/// or string, to the list is not permitted and will result in a Tcl error.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// </para>
/// <br/>
/// <para>
/// The following command gets a list of the ports from the ILA debug cores in the current project,<br/>
/// with a PORT_WIDTH property of 8:<br/>
/// get_debug_ports -filter {PORT_WIDTH==8}<br/>
/// The following example gets the properties attached to the specified debug port:<br/>
/// report_property [get_debug_ports myCore/PROBE1]<br/>
/// Note: The debug port is defined by the core_name/port_name combination.<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 672<br/>
/// </para>
/// </summary>
/// <param name="filter">(Optional) Filter list with expression</param>
/// <param name="of_objects">(Optional) Get ports of these debug cores</param>
/// <param name="regexp">(Optional) Patterns are full regular expressions</param>
/// <param name="nocase">(Optional) Perform case-insensitive matching (valid only when -regexp specified)</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
/// <param name="patterns">(Optional) Match debug ports against patterns Default: *</param>
/// <returns>list of debug_port objects</returns>
public TTCL get_debug_ports(String filter = null, TCLParameterList of_objects = null, bool?regexp = null, bool?nocase = null, bool?quiet = null, bool?verbose = null, TCLObject patterns = null)
{
// TCL Syntax: get_debug_ports [-filter <arg>] [-of_objects <args>] [-regexp] [-nocase] [-quiet] [-verbose] [<patterns>]
_tcl.Entry(_builder.get_debug_ports(filter, of_objects, regexp, nocase, quiet, verbose, patterns));
return(_tcl);
}
/// <summary>
/// <para>
/// Disconnect nets and pins from debug port channels<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: disconnect_debug_port [-channel_index <arg>] [-quiet] [-verbose] <port>
/// <br/>
/// <para>
/// Disconnect signals from the debug ports.<br/>
/// Signals from the Netlist Design are connected to ports of a ILA debug core using the<br/>
/// connect_debug_port command.<br/>
/// A port can also be deleted from the debug core rather than simply disconnected by using the<br/>
/// delete_debug_port command.<br/>
/// If you need to determine the specific name of a port on a debug core, use the<br/>
/// get_debug_ports command to list all ports on a core. You can also use the<br/>
/// report_debug_core command to list all of the cores in the projects, and their specific<br/>
/// parameters.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example disconnects only the specified channel index from the PROBE1 port of<br/>
/// myCore:<br/>
/// disconnect_debug_port -channel_index 2 myCore/PROBE1<br/>
/// If you do not specify the channel_index, all of the channels of the specified port will be<br/>
/// disconnected, as in the following example:<br/>
/// disconnect_debug_port myCore/PROBE1<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 494<br/>
/// </para>
/// </summary>
/// <param name="port">(Required) Debug port name</param>
/// <param name="channel_index">(Optional) Disconnect the net at channel index</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL disconnect_debug_port(TCLObject port, String channel_index = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: disconnect_debug_port [-channel_index <arg>] [-quiet] [-verbose] <port>
_tcl.Entry(_builder.disconnect_debug_port(port, channel_index, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Create a new debug port<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: create_debug_port [-quiet] [-verbose] <name> <type>
/// <br/>
/// <para>
/// Defines a new port to be added to an existing Vivado ILA debug core that was added to the<br/>
/// design using the create_debug_core command. The port provides connection points on an<br/>
/// ILA core to attach nets from the design for debugging.<br/>
/// When a new debug core is created using the create_debug_core command, it includes a clk<br/>
/// and probe port by default. However, you can add trigger input/output port types as well. Refer<br/>
/// to the Vivado Design Suite User Guide: Programming and Debugging (UG908) for more information<br/>
/// on port types and purpose.<br/>
/// A port can have one or more connection points to support one or more nets to debug. As a<br/>
/// default new ports are defined as having a width of 1, allowing only one net to be attached. You<br/>
/// can change the port width of probe ports to support multiple signals using the set_property<br/>
/// port_width command (see Examples).<br/>
/// Note: clk, trig_in, trig_in_ack, trig_out, and trig_out_ack ports can only have a width of 1.<br/>
/// You can connect signals to ports using the connect_debug_port command, modify existing<br/>
/// probe connections using modify_debug_ports, and disconnect signals with the<br/>
/// disconnect_debug_port command.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// </para>
/// <br/>
/// <para>
/// The following example creates a new debug core, and then adds an additional probe port to the<br/>
/// core, then sets the width of that new port to 8, and connects signals to the probe port:<br/>
/// create_debug_core myCore ila<br/>
/// create_debug_port myCore probe<br/>
/// set_property PORT_WIDTH 8 myCore/probe1<br/>
/// connect_debug_port -channel_start_index 1 myCore/probe1 \<br/>
/// {m1_cyc_i m1_ack_o m1_err_o m1_rty_o}<br/>
/// Note: Recall that the ILA core is created with a clk and probe port by default, so the new probe port is<br/>
/// automatically numbered as probe1.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 258<br/>
/// </para>
/// </summary>
/// <param name="name">(Required) Name of the debug core instance</param>
/// <param name="type">(Required) Type of the new debug port</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
/// <returns>new debug_port object</returns>
public TTCL create_debug_port(TCLObject name, TCLObject type, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: create_debug_port [-quiet] [-verbose] <name> <type>
_tcl.Entry(_builder.create_debug_port(name, type, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// (User-written application) Create and write a single design checkpoint and stub files for a Block<br/>
/// Design (BD), for use with third party synthesis tools. Perform synthesis as necessary.<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: export_bd_synth [-force] [-keep] [-verbose] [-quiet] <file>
/// <br/>
/// <para>
/// Runs synthesis for a block design (.bd), integrates the design along with any needed sub-designs<br/>
/// (e.g. out-of-context synthesized IP), and writes out a single design checkpoint (.dcp) of the<br/>
/// entire synthesized design, as well as HDL stub files, for use in other synthesis tools. The output<br/>
/// files will be placed in the same directory as the source BD file.<br/>
/// </para>
/// <br/>
/// <para>
/// The following command will generate a synthesis checkpoint, with stub files, for the specified<br/>
/// block design:<br/>
/// export_bd_synth [get_files block_1.bd]<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 515<br/>
/// </para>
/// </summary>
/// <param name="file">(Required) The Block Design file to write a synthesized checkpoint for</param>
/// <param name="force">(Optional) Overwrite existing design checkpoint and stub files</param>
/// <param name="keep">(Optional) Keep the temporary directory and project</param>
/// <param name="verbose">(Optional) Print verbose messaging</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <returns>(none) An error will be thrown if the command is not successful</returns>
public TTCL export_bd_synth(TCLObject file, bool?force = null, bool?keep = null, bool?verbose = null, bool?quiet = null)
{
// TCL Syntax: export_bd_synth [-force] [-keep] [-verbose] [-quiet] <file>
_tcl.Entry(_builder.export_bd_synth(file, force, keep, verbose, quiet));
return(_tcl);
}
/// <summary>
/// <para>
/// (User-written application) Export Tcl script for re-creating the current project<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: write_project_tcl [-paths_relative_to <arg>] [-origin_dir_override <arg>] [-target_proj_dir <arg>] [-force] [-all_properties] [-no_copy_sources] [-no_ip_version] [-absolute_path] [-dump_project_info] [-use_bd_files] [-internal] [-validate] [-quiet] [-verbose] <file>
/// <br/>
/// <para>
/// Creates a Tcl script to recreate the current project.<br/>
/// The generated script will contain the Tcl commands for creating the project, setting the project<br/>
/// type, creating filesets, adding/importing source files, defining runs and run properties.<br/>
/// IMPORTANT! The new project will be created in the current working directory (CWD) where the<br/>
/// generated Tcl script is sourced from. The script written out by write_project_tcl should be sourced<br/>
/// in the same directory from which it was created. If you source the script from a different directory, you<br/>
/// should first set the <origin_dir_loc> variable in Tcl shell to this alternate directory, or edit the script to<br/>
/// define the <origin_dir> variable in the script in order to maintain the relative path between the CWD and<br/>
/// the source files referenced in the script.<br/>
/// This Tcl project script and the various design sources can be stored in a version control system<br/>
/// for source file management and project archival.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example exports Tcl script named recreate.tcl for the current project:<br/>
/// write_project_tcl recreate.tcl<br/>
/// The following example exports a Tcl script named recreate.tcl for the current project in<br/>
/// the ./script directory and specifies the /tmp/test directory for the create_project<br/>
/// command. When the recreate.tcl script is run in the Vivado Tcl shell, the project will be re-created in /tmp/test directory:<br/>
/// write_project_tcl -target_proj_dir "/tmp/test" ./script/recreate.tcl<br/>
/// The following command exports Tcl script for the current project and writes all the properties,<br/>
/// both default or non-default values:<br/>
/// write_project_tcl -all_properties recreate.tcl<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// The following command exports Tcl script for the current project and adds files that are local in<br/>
/// this project. The recreated project will reference these files:<br/>
/// write_project_tcl -no_copy_sources -use_bd_files recreate.tcl<br/>
/// IMPORTANT! The -use_bd_files switch is required for use with -no_copy_sources in designs<br/>
/// with block diagrams.<br/>
/// The following command exports recreate.tcl script for the current project in the current<br/>
/// working directory, creates a new project in ./my_test directory, prints the list of files in the<br/>
/// new project, prints the current project settings and then closes the newly created project:<br/>
/// open_project ./test/test.xpr<br/>
/// write_project_tcl -force recreate.tcl<br/>
/// close_project<br/>
/// file mkdir my_test<br/>
/// cd my_test<br/>
/// source ../recreate.tcl<br/>
/// get_files -of_objects [get_filesets sources_1]<br/>
/// report_property [current_project]<br/>
/// close_project<br/>
/// The following command creates a new project named bft_test, adds files to the project, sets the<br/>
/// fileset property, exports a tcl script named bft.tcl in the current working directory, creates a<br/>
/// new project in ./my_bft directory, prints the list of files in the new project (test_1.v and<br/>
/// test_2.v), prints the "verilog_define" property value and then closes the newly created project:<br/>
/// create_project bft_test ./bft_test<br/>
/// add_files test_1.v<br/>
/// add_files test_2.v<br/>
/// set_property verilog_define {a=10} [get_filesets sources_1]<br/>
/// write_project_tcl -force bft.tcl<br/>
/// close_project<br/>
/// file mkdir my_bft<br/>
/// cd my_bft<br/>
/// source ../bft.tcl<br/>
/// get_files -of_objects [get_filesets sources_1]<br/>
/// get_property verilog_define [get_filesets sources_1]<br/>
/// close_project<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1878<br/>
/// </para>
/// </summary>
/// <param name="file">(Required) Name of the tcl script file to generate</param>
/// <param name="paths_relative_to">
/// <para>
/// (Optional)<br/>
/// Override the reference directory variable for source file<br/>
/// relative paths Default: Script output directory path<br/>
/// </para>
/// </param>
/// <param name="origin_dir_override">
/// <para>
/// (Optional)<br/>
/// Set 'origin_dir' directory variable to the specified value<br/>
/// (Default is value specified with the -paths_relative_to switch)<br/>
/// Default: None<br/>
/// </para>
/// </param>
/// <param name="target_proj_dir">
/// <para>
/// (Optional)<br/>
/// Directory where the project needs to be restored Default:<br/>
/// Current project directory path<br/>
/// </para>
/// </param>
/// <param name="force">(Optional) Overwrite existing tcl script file</param>
/// <param name="all_properties">(Optional) Write all properties (default & non-default) for the project object(s)</param>
/// <param name="no_copy_sources">
/// <para>
/// (Optional)<br/>
/// Do not import sources even if they were local in the original<br/>
/// project Default: 1<br/>
/// </para>
/// </param>
/// <param name="no_ip_version">
/// <para>
/// (Optional)<br/>
/// Flag to not include the IP version as part of the IP VLNV in<br/>
/// create_bd_cell commands. Default: 1<br/>
/// </para>
/// </param>
/// <param name="absolute_path">(Optional) Make all file paths absolute wrt the original project directory</param>
/// <param name="dump_project_info">(Optional) Write object values</param>
/// <param name="use_bd_files">(Optional) Use BD sources directly instead of writing out procs to create them</param>
/// <param name="internal">(Optional) Print basic header information in the generated tcl script</param>
/// <param name="validate">
/// <para>
/// (Optional)<br/>
/// Runs a validate script before recreating the project. To test if<br/>
/// the files and paths refrenced in the tcl file exists or not.<br/>
/// </para>
/// </param>
/// <param name="quiet">(Optional) Execute the command quietly, returning no messages from the command.</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
/// <returns>true (0) if success, false (1) otherwise</returns>
public TTCL write_project_tcl(TCLObject file, String paths_relative_to = null, String origin_dir_override = null, String target_proj_dir = null, bool?force = null, bool?all_properties = null, bool?no_copy_sources = null, bool?no_ip_version = null, bool?absolute_path = null, bool?dump_project_info = null, bool?use_bd_files = null, bool? @internal = null, bool?validate = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: write_project_tcl [-paths_relative_to <arg>] [-origin_dir_override <arg>] [-target_proj_dir <arg>] [-force] [-all_properties] [-no_copy_sources] [-no_ip_version] [-absolute_path] [-dump_project_info] [-use_bd_files] [-internal] [-validate] [-quiet] [-verbose] <file>
_tcl.Entry(_builder.write_project_tcl(file, paths_relative_to, origin_dir_override, target_proj_dir, force, all_properties, no_copy_sources, no_ip_version, absolute_path, dump_project_info, use_bd_files, @internal, validate, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Add a new bus interface to a peripheral.<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: add_peripheral_interface -interface_mode <arg> -axi_type <arg> [-quiet] [-verbose] <name> <peripheral>
/// <br/>
/// <para>
/// Add an AXI bus interface to a peripheral created with the create_peripheral command.<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 57<br/>
/// </para>
/// </summary>
/// <param name="interface_mode">(Required) Mode of an interface, supported option - master,slave.</param>
/// <param name="axi_type">(Required) Type of a axi interface, supported option - lite,full,stream.</param>
/// <param name="name">(Required) Name to initialize the newly added element e.g S1_AXI, M1_AXI</param>
/// <param name="peripheral">(Required) Peripheral object</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL add_peripheral_interface(String interface_mode, String axi_type, TCLObject name, TCLObject peripheral, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: add_peripheral_interface -interface_mode <arg> -axi_type <arg> [-quiet] [-verbose] <name> <peripheral>
_tcl.Entry(_builder.add_peripheral_interface(interface_mode, axi_type, name, peripheral, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Import simulation data in saif format<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: read_saif [-strip_path <arg>] [-no_strip] [-out_file <arg>] [-quiet] [-verbose] <file>
/// <br/>
/// <para>
/// Reads a Switching Activity Interchange Format (SAIF) file for use during power analysis by the<br/>
/// report_power command, or power optimization by power_opt_design. The read_saif<br/>
/// command will annotate the design nodes with activity from the SAIF file and estimate power<br/>
/// appropriately.<br/>
/// Running report_power or power_opt_design after reading the SAIF file will use the activity<br/>
/// rates from the specified file during optimization and analysis.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example:<br/>
/// read_saif -strip_path design/top/F1 C:/Data/design1.saif<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1176<br/>
/// </para>
/// </summary>
/// <param name="file">(Required) Specifies the name of the SAIF file to be read</param>
/// <param name="strip_path">
/// <para>
/// (Optional)<br/>
/// Specifies the name of the instance of the current design as<br/>
/// it appears in the SAIF file<br/>
/// </para>
/// </param>
/// <param name="no_strip">(Optional) Do not strip first two levels of hierarchy from SAIF file</param>
/// <param name="out_file">
/// <para>
/// (Optional)<br/>
/// Specifies the name of the output file that contains nets that<br/>
/// could not be matched<br/>
/// </para>
/// </param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL read_saif(TCLObject file, String strip_path = null, bool?no_strip = null, String out_file = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: read_saif [-strip_path <arg>] [-no_strip] [-out_file <arg>] [-quiet] [-verbose] <file>
_tcl.Entry(_builder.read_saif(file, strip_path, no_strip, out_file, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Create a peripheral with a VLNV.<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: create_peripheral [-dir <arg>] [-quiet] [-verbose] <vendor> <library> <name> <version>
/// <br/>
/// <para>
/// Create an AXI peripheral to add to the IP repository with the specified VLNV attribute.<br/>
/// The AXI peripheral that is created is just a framework until interfaces have been added to the<br/>
/// peripheral using the add_peripheral_interface command, and the peripheral has been<br/>
/// generated using the generate_peripheral command.<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 329<br/>
/// </para>
/// </summary>
/// <param name="vendor">(Required) Vendor, for example xilinx.com</param>
/// <param name="library">(Required) Library, for example ip</param>
/// <param name="name">(Required) Name, for example myip</param>
/// <param name="version">(Required) Version, for example 1.4</param>
/// <param name="dir">
/// <para>
/// (Optional)<br/>
/// Directory path for remote Peripheral to be created and<br/>
/// managed outside the project<br/>
/// </para>
/// </param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL create_peripheral(TCLObject vendor, TCLObject library, TCLObject name, TCLObject version, String dir = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: create_peripheral [-dir <arg>] [-quiet] [-verbose] <vendor> <library> <name> <version>
_tcl.Entry(_builder.create_peripheral(vendor, library, name, version, dir, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Create DSP source for Xilinx System Generator and add to the source fileset<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: create_sysgen [-quiet] [-verbose] <name>
/// <br/>
/// <para>
/// Create a DSP sub-module for use in the current project, and add it to the source files.<br/>
/// This command will launch System Generator for DSP to let you design the hardware portion of<br/>
/// your system design. System Generator is a DSP design tool from Xilinx that allows the RTL<br/>
/// source files, Simulink® and MATLAB® software models, and C/C++ components of a DSP system<br/>
/// to come together in a single simulation and implementation environment.<br/>
/// For more information on using specific features of the tool refer to System Generator for DSP<br/>
/// Getting Started Guide (UG639).<br/>
/// You can also add existing DSP model files (.mdl) from System Generator into the current project<br/>
/// using the add_files command.<br/>
/// The command returns the name of the DSP module created and added to the project.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example launches System Generator and allows you to define and configure the<br/>
/// specified DSP module:<br/>
/// create_sysgen DSP_mod1<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 365<br/>
/// </para>
/// </summary>
/// <param name="name">(Required) Sub module name</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
/// <returns>Name for the new sub module</returns>
public TTCL create_sysgen(TCLObject name, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: create_sysgen [-quiet] [-verbose] <name>
_tcl.Entry(_builder.create_sysgen(name, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Get a list of Methodology rule check objects<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: get_methodology_checks [-regexp] [-nocase] [-filter <arg>] [-abbrev <arg>] [-quiet] [-verbose] [<patterns>]
/// <br/>
/// <para>
/// Gets a list of the currently defined methodology checks. This list includes the factory defined<br/>
/// methodology checks for process and timing.<br/>
/// Note: To improve memory and performance, the get_* commands return a container list of a single type<br/>
/// of objects (e.g. cells, nets, pins, or ports). You can add new objects to the list (using lappend for instance),<br/>
/// but you can only add the same type of object that is currently in the list. Adding a different type of object,<br/>
/// or string, to the list is not permitted and will result in a Tcl error.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// </para>
/// <br/>
/// <para>
/// The following command gets a list of all synthesis methodology checks:<br/>
/// get_methodology_checks SYNTH*<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 829<br/>
/// </para>
/// </summary>
/// <param name="regexp">(Optional) Patterns are full regular expressions</param>
/// <param name="nocase">(Optional) Perform case-insensitive matching. (valid only when -regexp specified)</param>
/// <param name="filter">(Optional) Filter list with expression</param>
/// <param name="abbrev">(Optional) Get the largest ID for this abbrev</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
/// <param name="patterns">(Optional) Match the 'rule_check' objects against patterns. Default: *</param>
/// <returns>list of Methodology rule_check objects</returns>
public TTCL get_methodology_checks(bool?regexp = null, bool?nocase = null, String filter = null, String abbrev = null, bool?quiet = null, bool?verbose = null, TCLObject patterns = null)
{
// TCL Syntax: get_methodology_checks [-regexp] [-nocase] [-filter <arg>] [-abbrev <arg>] [-quiet] [-verbose] [<patterns>]
_tcl.Entry(_builder.get_methodology_checks(regexp, nocase, filter, abbrev, quiet, verbose, patterns));
return(_tcl);
}
/// <summary>
/// <para>
/// Write QoR Suggestions to the given file<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: write_qor_suggestions [-strategy_dir <arg>] [-tcl_output_dir <arg>] [-force] [-of_objects <args>] [-quiet] [-verbose] <file>
/// <br/>
/// <para>
/// Write the QoR suggestions generated by the report_qor_suggestions command. You can<br/>
/// combine the suggestions from the latest report with suggestions read into the design with<br/>
/// read_qor_suggestions so that you can manage all suggestions in a single RQS file.<br/>
/// To write out specific QoR suggestions, use the -of_objects option. When this is not specified,<br/>
/// all suggestions will be written.<br/>
/// The recommended way to manage suggestions is using RQS objects. However, it is possible to<br/>
/// view and execute the commands using Tcl. Specifying the -tcl_output_dir option writes Tcl<br/>
/// scripts for the automated suggestions that are property based.<br/>
/// Implementation strategies that use machine learning to analyze the design can be generated<br/>
/// running report_qor_suggestions. If you specify the -strategy_dir option, multiple Tcl<br/>
/// files and one RQS file will be written for each strategy. The Tcl files aid integration into project or<br/>
/// non project flows. The main RQS file should not be used as the suggestions are contained in the<br/>
/// run specific files along with strategy information.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// This command returns the name of the output file created when successful, or returns an error if<br/>
/// it fails.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example reports QoR suggestions, then writes non-strategy suggestions to the<br/>
/// specified file.<br/>
/// report_qor_suggestions<br/>
/// write_qor_suggestions C:/Data/qor_results.rqs<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// The following example reports QoR suggestions, then writes both strategy and non-strategy<br/>
/// suggestions. It will create one RQS file for each strategy suggestion that exists, generating up to<br/>
/// three by default. Into each RQS file, it writes one strategy suggestion and all non-strategy<br/>
/// suggestions. This behavior means that for subsequent runs one RQS file per run is required.<br/>
/// report_qor_suggestions<br/>
/// write_qor_suggestions -strategy_dir C:/Data/strategy_dir C:/Data/<br/>
/// qor_suggestions.rqs<br/>
/// To make use of strategy suggestions, the directive for each implementation command<br/>
/// (opt_design, place_design, phys_opt_design, and route_design) must be set to RQS.<br/>
/// This can be configured automatically in project mode by sourcing the project mode Tcl script<br/>
/// generated for each RQS file in the strategy_dir. There is also a non-project example Tcl script<br/>
/// that demonstrates this requirement.<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1883<br/>
/// </para>
/// </summary>
/// <param name="file">
/// <para>
/// (Required)<br/>
/// QoR suggestions file Values: A filename with alphanumeric<br/>
/// characters and .rqs extension.<br/>
/// </para>
/// </param>
/// <param name="strategy_dir">
/// <para>
/// (Optional)<br/>
/// Directory to create Strategy RQS & TCL files Values: If<br/>
/// passed a directory path, for each strategy suggested one set<br/>
/// of RQS and TCL files will be generated.<br/>
/// </para>
/// </param>
/// <param name="tcl_output_dir">
/// <para>
/// (Optional)<br/>
/// Directory to create TCL files Values: TCL files for the QoR<br/>
/// suggestions will be generated in the provided directory.<br/>
/// </para>
/// </param>
/// <param name="force">(Optional) Overwrite existing suggestions file</param>
/// <param name="of_objects">(Optional) List of QoR suggestion objects</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL write_qor_suggestions(TCLObject file, String strategy_dir = null, String tcl_output_dir = null, bool?force = null, TCLParameterList of_objects = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: write_qor_suggestions [-strategy_dir <arg>] [-tcl_output_dir <arg>] [-force] [-of_objects <args>] [-quiet] [-verbose] <file>
_tcl.Entry(_builder.write_qor_suggestions(file, strategy_dir, tcl_output_dir, force, of_objects, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Get a list of Methodology violations from a previous report_methodology run<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: get_methodology_violations [-name <arg>] [-regexp] [-filter <arg>] [-nocase] [-quiet] [-verbose] [<patterns>]
/// <br/>
/// <para>
/// Gets a list of violation objects found in the design when the report_methodology command<br/>
/// is run. The properties of individual violation objects can be queried using report_property or<br/>
/// list_property commands for details of the violation.<br/>
/// Violation objects are associated with the cells, nets, pins, or ports in the current design, or sites<br/>
/// on the current device. The design objects associated with a methodology violation object can be<br/>
/// obtained using the -of_objects option of the appropriate get_* command, such as<br/>
/// get_cells, or get_nets for instance.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// Note: To improve memory and performance, the get_* commands return a container list of a single type<br/>
/// of objects (e.g. cells, nets, pins, or ports). You can add new objects to the list (using lappend for instance),<br/>
/// but you can only add the same type of object that is currently in the list. Adding a different type of object,<br/>
/// or string, to the list is not permitted and will result in a Tcl error.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example reports the methodology violations found in the current design, then<br/>
/// returns a list of all those violations:<br/>
/// report_methodology<br/>
/// get_methodology_violations<br/>
/// The following example generates list of violations in the named methodology report, and then<br/>
/// gets the pins associated with any violations found:<br/>
/// report_methodology -name method_1<br/>
/// get_pins -of_objects [get_methodology_violations -name method_1]<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 832<br/>
/// </para>
/// </summary>
/// <param name="name">(Optional) Get the results with this name</param>
/// <param name="regexp">(Optional) Patterns are full regular expressions</param>
/// <param name="filter">(Optional) Filter list with expression</param>
/// <param name="nocase">(Optional) Perform case-insensitive matching (valid only when -regexp specified)</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
/// <param name="patterns">
/// <para>
/// (Optional)<br/>
/// Match methodology_violations against patterns Default: *<br/>
/// Values: The default search pattern is the wildcard *, or .*<br/>
/// when -regexp is specified.<br/>
/// </para>
/// </param>
/// <returns>list of Methodology violation objects</returns>
public TTCL get_methodology_violations(String name = null, bool?regexp = null, String filter = null, bool?nocase = null, bool?quiet = null, bool?verbose = null, TCLObject patterns = null)
{
// TCL Syntax: get_methodology_violations [-name <arg>] [-regexp] [-filter <arg>] [-nocase] [-quiet] [-verbose] [<patterns>]
_tcl.Entry(_builder.get_methodology_violations(name, regexp, filter, nocase, quiet, verbose, patterns));
return(_tcl);
}
/// <summary>
/// <para>
/// Get a list of available QoR suggestions<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: get_qor_suggestions [-filter <arg>] [-quiet] [-verbose] [<IDs>]
/// <br/>
/// <para>
/// Get existing QoR suggestion objects created by the report_qor_suggestions command, or<br/>
/// read into the design using read_qor_suggestions. The selected QoR objects can be written<br/>
/// to a file using the write_qor_suggestions command. The suggestions created by the report<br/>
/// command remain in memory until delete_qor_suggestions is run, or until it is overwritten<br/>
/// by another report.<br/>
/// This command returns a list of existing QoR suggestion objects from the open design, or returns<br/>
/// an error if it fails.<br/>
/// </para>
/// <br/>
/// <para>
/// To return an individual suggestion, you can supply the full ID:<br/>
/// get_qor_suggestions RQS_CLOCK-5_1-1<br/>
/// Due to the naming style of suggestions, wildcard searches do NOT work directly. However you<br/>
/// can use the filter command with -regexp to use wildcards as follows:<br/>
/// filter -regexp [get_qor_suggestions] {NAME =~ RQS_CLOCK.*}<br/>
/// You can also filter suggestions objects within a given category. Available categories include:<br/>
/// Timing, Congestion, Utilization, XDC, Clocking, and Strategy. For example, the following returns<br/>
/// suggestions related to the Timing category:<br/>
/// get_qor_suggestions -filter {CATEGORY==Timing}<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 904<br/>
/// </para>
/// </summary>
/// <param name="filter">(Optional) Filter list with expression</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
/// <param name="IDs">(Optional) Match suggestion names against given names</param>
/// <returns>list of qor suggestion objects</returns>
public TTCL get_qor_suggestions(String filter = null, bool?quiet = null, bool?verbose = null, TCLObject IDs = null)
{
// TCL Syntax: get_qor_suggestions [-filter <arg>] [-quiet] [-verbose] [<IDs>]
_tcl.Entry(_builder.get_qor_suggestions(filter, quiet, verbose, IDs));
return(_tcl);
}
/// <summary>
/// <para>
/// Get one or more DRC/METHODOLOGY/CDC message waivers<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: get_waivers [-type <arg>] [-id <arg>] [-of_objects <args>] [-regexp] [-filter <arg>] [-nocase] [-quiet] [-verbose] [<patterns>]
/// <br/>
/// <para>
/// The create_waiver command lets you select individual DRC, methodology, or CDC violations<br/>
/// or rule checks that can be waived for a design, letting you move forward in the design flow. The<br/>
/// get_waivers command lets you query the defined waiver objects in the current design.<br/>
/// A waiver must be specified for an individual DRC or methodology violation, or for a specific DRC<br/>
/// or methodology check, or for a CDC path. The waiver must be assigned to a specific object, or<br/>
/// specific violation ID, or for paths using -from/-to arguments. You can format the<br/>
/// get_waivers command to return the specific types of waivers you are looking for, or waivers<br/>
/// associated with specific objects.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// You can report the waivers defined in the current design with report_waivers, and remove<br/>
/// waivers from the design using delete_waivers.<br/>
/// </para>
/// <br/>
/// <para>
/// This example gets any waivers in the current design:<br/>
/// get_waivers<br/>
/// The following example gets all DRC check waivers:<br/>
/// get_waivers -type DRC *<br/>
/// The following example gets all waivers associated with the specified objects:<br/>
/// get_waivers -of_objects [get_ports {src_in* dest_out*}]<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 957<br/>
/// </para>
/// </summary>
/// <param name="type">(Optional) Type of waiver - DRC, METHODOLOGY, CDC, ALL</param>
/// <param name="id">(Optional) ID of the DRC/METHODOLOGY/CDC message being waived</param>
/// <param name="of_objects">
/// <para>
/// (Optional)<br/>
/// List of objects (cells, nets, pins, sites, etc.) for which DRC/<br/>
/// METHODLOGY/CDC waiver(s) were set<br/>
/// </para>
/// </param>
/// <param name="regexp">(Optional) Patterns are full regular expressions</param>
/// <param name="filter">(Optional) Filter list with expression</param>
/// <param name="nocase">(Optional) Perform case-insensitive matching (valid only when -regexp specified)</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
/// <param name="patterns">
/// <para>
/// (Optional)<br/>
/// Match waiver names against patterns Default: * Values: The<br/>
/// default search pattern is the wildcard *, or .* when -regexp<br/>
/// is specified.<br/>
/// </para>
/// </param>
/// <returns>waivers</returns>
public TTCL get_waivers(String type = null, String id = null, TCLParameterList of_objects = null, bool?regexp = null, String filter = null, bool?nocase = null, bool?quiet = null, bool?verbose = null, TCLObject patterns = null)
{
// TCL Syntax: get_waivers [-type <arg>] [-id <arg>] [-of_objects <args>] [-regexp] [-filter <arg>] [-nocase] [-quiet] [-verbose] [<patterns>]
_tcl.Entry(_builder.get_waivers(type, id, of_objects, regexp, filter, nocase, quiet, verbose, patterns));
return(_tcl);
}
/// <summary>
/// <para>
/// Set user columns on one or more package pins<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: set_package_pin_val [-quiet] [-verbose] <column> <value> <package_pins>...
/// <br/>
/// <para>
/// Create user-defined package pin attributes and assign values to specific pins on the package.<br/>
/// User-defined pin attributes can be defined in a CSV file and imported into an I/O Pin Planning<br/>
/// project using read_csv, or can be edited in the project using this command.<br/>
/// Note: Use the set_property command to set tool-defined properties of a package pin.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example creates a new user-defined column in the Package Pins view, and assigns<br/>
/// the value true to the specified pin:<br/>
/// set_package_pin_val -column track1 -value true -package_pins AK27<br/>
/// The following example creates a user-defined column called Test, then assigns the value RED to<br/>
/// all "AK" package pins, then changes the value to GREEN for the three specified pins:<br/>
/// set_package_pin_val -column Test -value RED \<br/>
/// -package_pins [get_package_pins AK*]<br/>
/// set_package_pin_val -column Test -value GREEN \<br/>
/// -package_pins {AK1 AK2 AK3}<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1670<br/>
/// </para>
/// </summary>
/// <param name="column">(Required) User column name</param>
/// <param name="value">(Required) Value to set</param>
/// <param name="package_pins">(Required) Package pin names</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL set_package_pin_val(TCLObject column, TCLObject value, TCLObjectList package_pins, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: set_package_pin_val [-quiet] [-verbose] <column> <value> <package_pins>...
_tcl.Entry(_builder.set_package_pin_val(column, value, package_pins, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Write out one or more DRC/METHODOLOGY/CDC message waivers in command form<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: write_waivers [-type <arg>] [-objects <args>] [-return_string] [-force] [-quiet] [-verbose] [<file>]
/// <br/>
/// <para>
/// To save waivers from one design session to the next, you must use write_waivers to create<br/>
/// an XDC file of the waiver commands, and read_xdc to read those waivers back into the design<br/>
/// when it is reopened.<br/>
/// </para>
/// <br/>
/// <para>
/// This example writes all waivers in the current design:<br/>
/// write_waivers C:/Data/design_waivers.xdc<br/>
/// The following example writes only DRC type waivers:<br/>
/// write_waivers -type DRC C:/Data/drc_waivers.xdc<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1898<br/>
/// </para>
/// </summary>
/// <param name="file">(Required) Name of file to write waivers</param>
/// <param name="type">(Optional) Type of waiver(s) - ALL, DRC, METHODOLOGY, CDC to write</param>
/// <param name="objects">(Optional) List of DRC/METHODOLOGY/CDC waiver objects to be written</param>
/// <param name="return_string">(Optional) Return report results as a string object</param>
/// <param name="force">(Optional) Overwrite existing file</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL write_waivers(TCLObject file, String type = null, TCLParameterList objects = null, bool?return_string = null, bool?force = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: write_waivers [-type <arg>] [-objects <args>] [-return_string] [-force] [-quiet] [-verbose] [<file>]
_tcl.Entry(_builder.write_waivers(file, type, objects, return_string, force, quiet, verbose));
return(_tcl);
}
public TCLCommandObjectParameter(TCLObject value)
{
_value = value;
}
/// <summary>
/// <para>
/// (User-written application) Copy a run from an already existing run, source-run, to a new copy of<br/>
/// that run, destination-run.<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: copy_run [-parent_run <arg>] [-verbose] -name <arg> [-quiet] <run>
/// <br/>
/// <para>
/// Copies an existing synthesis or implementation run.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example will copy synth_1 run into a new synth_2 run:<br/>
/// copy_run -name synth_2 [get_runs synth_1]<br/>
/// The following example will copy the impl_1 run into a new run called impl_2, and assign synth_2<br/>
/// as the parent of the new run:<br/>
/// copy_run -name impl_2 [get_runs impl_1] -parent_run synth_2<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 220<br/>
/// </para>
/// </summary>
/// <param name="name">(Required) Specify the name of the new run</param>
/// <param name="run">(Required) The run to be copied, accepts name or run object</param>
/// <param name="parent_run">
/// <para>
/// (Optional)<br/>
/// Specify the synthesis run for the new implementation run,<br/>
/// accepts name or run object (Default: same as source run)<br/>
/// Default: None<br/>
/// </para>
/// </param>
/// <param name="verbose">(Optional) Print detailed information as the copy progresses</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <returns>The new run object</returns>
public TTCL copy_run(String name, TCLObject run, String parent_run = null, bool?verbose = null, bool?quiet = null)
{
// TCL Syntax: copy_run [-parent_run <arg>] [-verbose] -name <arg> [-quiet] <run>
_tcl.Entry(_builder.copy_run(name, run, parent_run, verbose, quiet));
return(_tcl);
}
