public XilinxAdderSubtracter() { TASite = new TransactionSite(this); Generator = EGenerator.Adder_Subtracter_11_0; Atype = ESignedness.Signed; Btype = ESignedness.Signed; Awidth = 20; AddMode = EAddMode.Add; AinitValue = 0; Bconstant = false; Bvalue = "00000000000000000000"; Bwidth = 20; BorrowSense = ESense.ActiveLow; HasBypass = false; BypassSense = ESense.ActiveHigh; BypassCePriority = ECeOverridesBypass.CeOverridesBypass; HasCarryIn = false; HasCE = false; Implementation = EImplementation.Fabric; Latency = 2; LatencyConfiguration = ELatencyConfiguration.Manual; OutWidth = 20; HasSCLR = false; HasConstantInput = false; ConstantInputValue = StdLogicVector._0s(Bwidth); HasSSET = false; SyncCePriority = ESyncOverridesCe.SyncOverridesCe; SyncCtrlPriority = ERsetOverridesSet.RsetOverridesSet; }
private void CreateSelSymbol(IAutoBinder binder, bool registered) { int count = NumSymbols; if (count < 2) { return; } // This code will create a one-hot decoding var selSymbols = new StdLogicVector[NumSymbols]; _selSymbols = selSymbols; for (int i = 0; i < NumSymbols; i++) { StdLogicVector sym = StdLogicVector._0s(NumSymbols); sym[i] = '1'; selSymbols[i] = sym; } var signal = binder.GetSignal(EPortUsage.Default, "MUXSymbol" + Order, null, selSymbols[0]); _symbol = signal.Descriptor; if (registered) { var dsignal = binder.GetSignal(EPortUsage.Default, "MUXReg" + Order, null, selSymbols[0]); _symbold = dsignal.Descriptor; } }
protected async Task <StdLogicVector> MasterRead(StdLogicVector addr) { ip2bus_mstrd_req.Next = '1'; ip2bus_mstwr_req.Next = '0'; ip2bus_mst_type.Next = '0'; ip2bus_mst_addr.Next = addr; ip2bus_mst_be.Next = StdLogicVector._1s(NativeDataWidth / 8); ip2bus_mst_length.Next = StdLogicVector._0s(LengthWidth); ip2bus_mst_lock.Next = '0'; ip2bus_mst_reset.Next = '0'; ip2bus_mstrd_dst_rdy_n.Next = '0'; ip2bus_mstrd_dst_dsc_n.Next = '1'; do { await Tick; } while (bus2ip_mst_cmdack.Cur != '1'); ip2bus_mstrd_req.Next = '0'; do { await Tick; } while (bus2ip_mst_cmplt.Cur != '1'); ip2bus_mstrd_dst_rdy_n.Next = '1'; return(bus2ip_mstrd_d.Cur); }
public void CreateControlpath(FlowMatrix flowSpec, string procName) { int ncsteps = flowSpec.NumCSteps; string report = _mcd.ComputeEncoding(flowSpec, _maxSelWidth); _curCW = (SLVSignal)_binder.GetSignal <StdLogicVector>(EPortUsage.Default, "CurCW", null, StdLogicVector._0s(_mcd.CWWidth)); var clkInst = _binder.GetSignal <StdLogic>(EPortUsage.Clock, "Clk", null, '0'); if (_staged) { _mcd.CreateStagedDecoder(_binder, _curCW, (SLSignal)clkInst, _registered); } else { _mcd.CreateDecoder(_binder, _curCW); } CreateROM(ncsteps); for (int cstep = 0; cstep < ncsteps; cstep++) { var cw = _mcd.Encode(cstep, flowSpec.GetFlow(cstep)); _romIf.PreWrite(StdLogicVector.FromUInt((uint)cstep, _pc.Size), cw); } var syncTempl = new SyncTemplate(this); var syncFunc = syncTempl.GetAlgorithm(); _binder.CreateProcess(SystemSharp.Components.Process.EProcessKind.Triggered, syncFunc, clkInst.Descriptor); _host.Descriptor.GetDocumentation().Documents.Add(new Document(procName + "_HMA_report.txt", report)); }
protected async Task WriteBus(int reg, StdLogicVector be, StdLogicVector data) { _sig_Bus2IP_WrCE.Next = StdLogicVector.OneHot(user_logic.NumRegs, user_logic.NumRegs - reg - 1); _sig_Bus2IP_BE.Next = be; _sig_Bus2IP_Data.Next = data; for (int t = 0; t < 100; t++) { await Tick; if (_sig_IP2Bus_WrAck.Cur == '1' || _sig_IP2Bus_Error.Cur == '1') { break; } } if (_sig_IP2Bus_Error.Cur == '1') { Console.WriteLine("Bus write error @reg " + reg); } if (_sig_IP2Bus_Error.Cur == '0' && _sig_IP2Bus_WrAck.Cur == '0') { Console.WriteLine("Timeout @reg " + reg); } _sig_Bus2IP_WrCE.Next = StdLogicVector._0s(user_logic.NumRegs); _sig_Bus2IP_BE.Next = StdLogicVector._0s(user_logic.SLVDWidth / 8); _sig_Bus2IP_Data.Next = StdLogicVector.Xs(user_logic.SLVDWidth); }
private object Create0(TypeDescriptor type) { var slv = StdLogicVector.Serialize(type.GetSampleInstance()); slv = StdLogicVector._0s(slv.Size); return(StdLogicVector.Deserialize(slv, type.CILType)); }
protected override IEnumerable <TAVerb> RealizeDefault() { ISignalSource <StdLogicVector>[] ops = Enumerable.Repeat( SignalSource.Create(StdLogicVector._0s(_host.WordWidth)), _host.NumWords).ToArray(); return(_host.TASite.Concat(ops, SignalSink.Nil <StdLogicVector>())); }
/// <summary> /// Replaces all value-flows transferring don't-care values by real values. /// </summary> /// <remarks> /// The semantics of the don't-care symbol admit any such symbol to be replaced with any other symbol, e.g. '0' or '1' /// without changing the behavior. However, if we blindly replace any don't care symbol with - let's say - logical zeroes, /// we won't perform optimally, since we might introduce unnecessary multiplexers. Therefore, the method first tries to /// find existing non-don't-care value-flows as suitable replacement candidates. Only if no such is found, it arbitrarily /// chooses to replace don't-cares with logical zeroes. /// </remarks> public void ReplaceDontCares() { var picks = new Dictionary <SignalRef, Flow>(); foreach (var target in FlowTargets) { Flow pick = GetFlowsTo(target) .Where(f => !IsDontCareFlow(f)) .FirstOrDefault(); if (pick == null) { ValueFlow vflow = (ValueFlow)GetFlowsTo(target).First(); StdLogicVector data = (StdLogicVector)vflow.Value; pick = new ValueFlow(StdLogicVector._0s(data.Size), target); } picks[target] = pick; } var allGraphs = _graphs.Concat(Enumerable.Repeat(_neutral, 1)); foreach (FlowGraph g in allGraphs) { var pflow = g.ToFlow(); foreach (Flow flow in pflow.Flows) { if (IsDontCareFlow(flow)) { Flow pick = picks[flow.Target]; g.Add(pick); } } } }
private bool TryGetConstSLV(XILInstr instr, TypeDescriptor rtype, out StdLogicVector constSLV) { switch (instr.Name) { case InstructionCodes.LdConst: { object constValue = instr.Operand; constSLV = StdLogicVector.Serialize(constValue); } break; case InstructionCodes.Ld0: { object sample = rtype.GetSampleInstance(); StdLogicVector slv = StdLogicVector.Serialize(sample); constSLV = StdLogicVector._0s(slv.Size); } break; default: { constSLV = ""; return(false); } } return(true); }
/// <summary> /// Constructs a new instance. /// </summary> /// <param name="inputWidth">bit-width of operand</param> /// <param name="hiOffset">high slice offset</param> /// <param name="loOffset">low slice offset</param> /// <param name="signed">whether operand is signed</param> public Slicer(int inputWidth, int hiOffset, int loOffset, bool signed) { Contract.Requires <ArgumentOutOfRangeException>(hiOffset - loOffset >= -1); InputWidth = inputWidth; HiOffset = hiOffset; LoOffset = loOffset; IsSigned = signed; TASite = new SlicerTransactionSite(this); int msb = signed ? inputWidth - 2 : inputWidth - 1; int hiPadWidth = Math.Max(hiOffset, msb) - Math.Max(loOffset, msb + 1) + 1; int loPadWidth = Math.Min(hiOffset, -1) - Math.Min(loOffset, 0) + 1; _hiSlice = Math.Min(msb, hiOffset); _loSlice = Math.Max(0, loOffset); if (_loSlice > _hiSlice) { // degenerate case: actually no portion of input word is used _hiSlice = -1; _loSlice = 0; } _hiPad0 = StdLogicVector._0s(hiPadWidth); _hiPad1 = StdLogicVector._1s(hiPadWidth); _loPad = StdLogicVector._0s(loPadWidth); Debug.Assert(hiPadWidth + loPadWidth + _hiSlice - _loSlice == hiOffset - loOffset); }
protected async Task <StdLogicVector> ReadBus(int reg) { StdLogicVector value; _sig_Bus2IP_RdCE.Next = StdLogicVector.OneHot(user_logic.NumRegs, user_logic.NumRegs - reg - 1); for (int t = 0; t < 100; t++) { await Tick; if (_sig_IP2Bus_RdAck.Cur == '1' || _sig_IP2Bus_Error.Cur == '1') { break; } } if (_sig_IP2Bus_Error.Cur == '1') { Console.WriteLine("Bus read error @reg " + reg); } if (_sig_IP2Bus_Error.Cur == '0' && _sig_IP2Bus_RdAck.Cur == '0') { Console.WriteLine("Timeout @reg " + reg); } _sig_Bus2IP_RdCE.Next = StdLogicVector._0s(user_logic.NumRegs); value = _sig_IP2Bus_Data.Cur; return(value); }
protected override IEnumerable <TAVerb> RealizeDefault() { return(_host.TASite.RShift( SignalSource.Create(StdLogicVector._0s(_host.DataWidth)), SignalSource.Create(StdLogicVector._0s(_host.ShiftWidth)), SignalSink.Nil <StdLogicVector>())); }
private TAVerb NopVerb() { return(Verb(ETVMode.Locked, _host.BrP.Dual.Drive(SignalSource.Create <StdLogicVector>("0")), _host.BrN.Dual.Drive(SignalSource.Create <StdLogicVector>("1")), _host.AltAddr.Dual.Drive(SignalSource.Create(StdLogicVector._0s(_host.AddrWidth))))); }
/// <summary> /// Constructs a new testbechn. /// </summary> /// <param name="userLogic">component under test</param> public AXILiteSlaveUserLogicTestbench(AXILiteSlaveUserLogic userLogic) { user_logic = userLogic; _sig_Bus2IP_Clk = new SLSignal(); _sig_Bus2IP_Resetn = new SLSignal() { InitialValue = '0' }; _sig_Bus2IP_Data = new SLVSignal(userLogic.SLVDWidth) { InitialValue = StdLogicVector.Xs(userLogic.SLVDWidth) }; _sig_Bus2IP_BE = new SLVSignal(userLogic.SLVDWidth / 8) { InitialValue = StdLogicVector._0s(userLogic.SLVDWidth / 8) }; _sig_Bus2IP_RdCE = new SLVSignal(userLogic.NumRegs) { InitialValue = StdLogicVector._0s(userLogic.NumRegs) }; _sig_Bus2IP_WrCE = new SLVSignal(userLogic.NumRegs) { InitialValue = StdLogicVector._0s(userLogic.NumRegs) }; _sig_IP2Bus_Data = new SLVSignal(userLogic.SLVDWidth) { InitialValue = StdLogicVector._0s(userLogic.SLVDWidth) }; _sig_IP2Bus_RdAck = new SLSignal() { InitialValue = '0' }; _sig_IP2Bus_WrAck = new SLSignal() { InitialValue = '0' }; _sig_IP2Bus_Error = new SLSignal() { InitialValue = '0' }; userLogic.Bus2IP_Clk = _sig_Bus2IP_Clk; userLogic.Bus2IP_BE = _sig_Bus2IP_BE; userLogic.Bus2IP_Clk = _sig_Bus2IP_Clk; userLogic.Bus2IP_Data = _sig_Bus2IP_Data; userLogic.Bus2IP_RdCE = _sig_Bus2IP_RdCE; userLogic.Bus2IP_Resetn = _sig_Bus2IP_Resetn; userLogic.Bus2IP_WrCE = _sig_Bus2IP_WrCE; userLogic.IP2Bus_Data = _sig_IP2Bus_Data; userLogic.IP2Bus_Error = _sig_IP2Bus_Error; userLogic.IP2Bus_RdAck = _sig_IP2Bus_RdAck; userLogic.IP2Bus_WrAck = _sig_IP2Bus_WrAck; _clockGen = new Clock(new Time(10.0, ETimeUnit.ns)) { Clk = _sig_Bus2IP_Clk }; }
private StdLogicVector CreateVector() { StdLogicVector[] r = new StdLogicVector[4]; r[0] = StdLogicVector._0s(MaxWidth); r[1] = StdLogicVector._1s(MaxWidth); r[2] = StdLogicVector.DCs(MaxWidth); r[3] = StdLogicVector.Xs(MaxWidth); return(r[0].Concat(r[1].Concat(r[2].Concat(r[3])))); }
public StdLogicVector Encode(int cstep, ParFlow cstepFlow) { var cword = StdLogicVector._0s(CWWidth); ParFlow allFlow = new ParFlow(FlowSpec.NeutralFlow); allFlow.Integrate(cstepFlow); Encode(cstep, allFlow, ref cword); return(cword); }
/// <summary> /// Converts a double value to its binary encoding, given a floating point format. /// </summary> /// <param name="value">The value to be encoded</param> /// <param name="fmt">The floating point format to be assumed</param> /// <returns>The binary encoding</returns> public static StdLogicVector ToSLV(this double value, FloatFormat fmt) { StdLogicVector sign; StdLogicVector exponent; StdLogicVector mantissa; if (double.IsInfinity(value)) { sign = double.IsNegativeInfinity(value) ? (StdLogicVector)"1" : (StdLogicVector)"0"; exponent = StdLogicVector._1s(fmt.ExponentWidth); mantissa = StdLogicVector._0s(fmt.FractionWidth); } else if (double.IsNaN(value)) { sign = (StdLogicVector)"0"; exponent = StdLogicVector._1s(fmt.ExponentWidth); mantissa = StdLogicVector._1s(fmt.FractionWidth); } else { sign = value < 0.0 ? (StdLogicVector)"1" : (StdLogicVector)"0"; double absvalue = Math.Abs(value); int exp = 0; while (absvalue >= 2.0) { absvalue *= 0.5; exp++; } while (absvalue > 0.0 && absvalue < 1.0) { absvalue *= 2.0; exp--; } if (absvalue == 0.0) { return(StdLogicVector._0s(fmt.TotalWidth)); } else if (exp <= -fmt.Bias) { // denomalized exponent = StdLogicVector._0s(fmt.ExponentWidth); absvalue *= (double)(1L << (fmt.FractionWidth + 1)); long mant = (long)absvalue; mantissa = StdLogicVector.FromLong(mant, fmt.FractionWidth); } else { absvalue -= 1.0; absvalue *= (double)(1L << fmt.FractionWidth); long mant = (long)absvalue; mantissa = StdLogicVector.FromLong(mant, fmt.FractionWidth); exponent = StdLogicVector.FromLong(exp + fmt.Bias, fmt.ExponentWidth); } } return(sign.Concat(exponent.Concat(mantissa))); }
private void MakeVectors(int value1, int width1, int value2, int width2, out StdLogicVector r1, out StdLogicVector r2) { StdLogicVector v1 = StdLogicVector.FromLong(value1, width1); StdLogicVector v2 = StdLogicVector.FromLong(value2, width2); StdLogicVector v = v1.Concat(v2).Concat(StdLogicVector._0s(2 * MaxWidth - width1 - width2)); r1 = v[2 * MaxWidth - 1, MaxWidth]; r2 = v[MaxWidth - 1, 0]; }
private void Processing() { StdLogicVector result = StdLogicVector._0s(OutputWidth); for (int i = 0; i < NumWords; i++) { result[WordWidth * (i + 1) - 1, WordWidth *i] = Ops[i].Cur; } R.Next = result; }
/// <summary> /// Converts a binary encoding, given as an StdLogicVector with respect to a floating point format to its /// double representation. /// </summary> /// <param name="slv">The binary encoding</param> /// <param name="fmt">The floating point format to be assumed</param> /// <returns>The double representation</returns> public static double ToFloat(this StdLogicVector slv, FloatFormat fmt) { if (slv.Size != fmt.TotalWidth) { throw new ArgumentException("Vector does not match specified floating point format"); } slv = slv.ProperValue; StdLogicVector mantissa = slv[fmt.FractionWidth - 1, 0]; StdLogicVector exponent = slv[fmt.FractionWidth + fmt.ExponentWidth - 1, fmt.FractionWidth]; StdLogic sign = slv[fmt.FractionWidth + fmt.ExponentWidth]; int exp = (int)exponent.ULongValue - fmt.Bias; if (exponent.Equals(StdLogicVector._0s(fmt.ExponentWidth))) { // denormalized long mant = mantissa.LongValue; double result = (double)mant * Math.Pow(2.0, exp - 1); return(result); } else if (exponent.Equals(StdLogicVector._1s(fmt.ExponentWidth))) { // Infinity / NaN if (mantissa.Equals(StdLogicVector._0s(fmt.FractionWidth))) { // infinity if (sign == '1') { return(double.NegativeInfinity); } else { return(double.PositiveInfinity); } } else { // NaN return(double.NaN); } } else { // normalized StdLogicVector number = StdLogicVector._1s(1).Concat(mantissa); ulong mant = number.ULongValue; double result = (double)mant * Math.Pow(2.0, exp - fmt.FractionWidth); if (sign == '1') { result = -result; } return(result); } }
private void CreateState(int ncsteps) { int pcWidth = MathExt.CeilLog2(ncsteps); _pc = (SLVSignal)_binder.GetSignal(EPortUsage.State, "State", null, StdLogicVector._0s(pcWidth)); _altAddr = (SLVSignal)_binder.GetSignal(EPortUsage.Default, "BCU_AltAddr", null, StdLogicVector._0s(pcWidth)); _rdEn = (SLSignal)_binder.GetSignal(EPortUsage.Default, "ROM_RdEn", null, StdLogic._1); _brP = (SLVSignal)_binder.GetSignal <StdLogicVector>(EPortUsage.Default, "BCU_BrP", null, "0"); _brN = (SLVSignal)_binder.GetSignal <StdLogicVector>(EPortUsage.Default, "BCU_BrN", null, "1"); _rst = (SLSignal)_binder.GetSignal(EPortUsage.Default, "BCU_Rst", null, StdLogic._1); }
private void PrepareBCU(int ncsteps) { _bcu.AddrWidth = MathExt.CeilLog2(ncsteps); _bcu.StartupAddr = StdLogicVector._0s(_bcu.AddrWidth); _bcu.Clk = (SLSignal)_binder.GetSignal(EPortUsage.Clock, "Clk", null, null); _bcu.Rst = _rst; _bcu.BrP = _brP; _bcu.BrN = _brN; _bcu.AltAddr = _altAddr; _bcu.OutAddr = _pc; }
/// <summary> /// Constructs a new instance. /// </summary> /// <param name="floatWidth">total bit-width of input floating-point number /// (actual partitioning between exponent and mantissa bits does not matter)</param> /// <param name="outFormat">desired fixed-point output format</param> public FloatSignAsSigned(int floatWidth, FixFormat outFormat) { FloatWidth = floatWidth; OutFormat = outFormat; _outM1 = SFix.FromDouble(-1.0, outFormat.IntWidth, outFormat.FracWidth).SLVValue; _out0 = SFix.FromDouble(0.0, outFormat.IntWidth, outFormat.FracWidth).SLVValue; _out1 = SFix.FromDouble(1.0, outFormat.IntWidth, outFormat.FracWidth).SLVValue; _zeros = StdLogicVector._0s(floatWidth - 1); TASite = new TransactionSite(this); }
public override StdLogicVector[] SerializeInstance(object instance) { Array array = (Array)instance; IEnumerable <object> elements = array.Cast <object>(); int rank = Strides.Length; int[] curSrcIndex = new int[rank]; int curDstIndex = 0; int curSubIndex = 0; StdLogicVector[] result = Enumerable.Repeat( StdLogicVector._0s(WordSize), array.GetLength(0) * (int)Strides[0]) .ToArray(); foreach (object element in elements) { StdLogicVector[] elementData = ElementLayout.SerializeInstance(element); curDstIndex = 0; for (int i = 0; i < rank; i++) { curDstIndex += (int)Strides[i] * curSrcIndex[i]; } if (SubStride == 0) { Array.Copy(elementData, 0, result, curDstIndex, elementData.Length); } else { Debug.Assert(elementData.Length == 1); result[curDstIndex][(curSubIndex + 1) * (int)SubStride - 1, curSubIndex *(int)SubStride] = elementData[0][(int)SubStride - 1, 0]; if (++curSubIndex == ElementsPerWord) { curSubIndex = 0; } else { continue; } } for (int i = rank - 1; i >= 0; i--) { if (++curSrcIndex[i] == array.GetLength(i)) { curSrcIndex[i] = 0; } else { break; } } } return(result); }
private void HandleLdelemFixAFixI(XILSInstr xilsi) { FixedArrayRef far = (FixedArrayRef)xilsi.StaticOperand; Array array = far.ArrayObj; long[] indices = far.Indices; var preds = RemapPreds(xilsi.Preds); MemoryMappedStorage mms = GetDataLayout(array); ArrayMemoryLayout layout = mms.Layout as ArrayMemoryLayout; if (layout.ElementsPerWord > 1) { throw new NotImplementedException("Multiple elements per word not yet implemented"); } MemoryRegion region = mms.Region; IMarshalInfo minfo = region.MarshalInfo; TypeDescriptor dwType = minfo.GetRawWordType(); for (uint i = 0; i < layout.WordsPerElement; i++) { Unsigned addr = ComputeConstAddress(array, indices, i); Emit(_iset.LdConst(addr) .CreateStk(0, TypeDescriptor.GetTypeOf(addr))); Emit(_iset.RdMem(region) .CreateStk(preds, 1, TypeDescriptor.GetTypeOf(addr), dwType)); } uint concatTypeSize = minfo.WordSize * layout.WordsPerElement; TypeDescriptor concatType = TypeDescriptor.GetTypeOf( StdLogicVector._0s(concatTypeSize)); if (layout.WordsPerElement > 1) { TypeDescriptor[] stackTypes = new TypeDescriptor[layout.WordsPerElement + 1]; for (uint i = 0; i < layout.WordsPerElement; i++) { stackTypes[i] = dwType; } stackTypes[layout.WordsPerElement] = concatType; Emit(_iset.Concat().CreateStk((int)layout.WordsPerElement, stackTypes)); } TypeDescriptor elemTypeRaw = TypeDescriptor.GetTypeOf( StdLogicVector._0s((int)layout.ElementLayout.SizeInBits)); if (concatTypeSize != layout.ElementLayout.SizeInBits) { Emit(_iset.Convert().CreateStk(1, concatType, elemTypeRaw)); } TypeDescriptor elemType = layout.ElementLayout.LayoutedType; Emit(_iset.Convert().CreateStk(1, elemTypeRaw, elemType)); }
public void CreateStagedDecoder(IAutoBinder binder, SLVSignal cwSignal, SLSignal clkSignal, bool registered) { var valWordInit = StdLogicVector._0s(_vcf.ValueWordWidth); var rcwSignal = (SLVSignal)binder.GetSignal(EPortUsage.Default, "D1_CW", null, valWordInit); var rcwSignalDesc = rcwSignal.Descriptor; SLVSignal rrcwSignal = null; if (registered) { rrcwSignal = (SLVSignal)binder.GetSignal(EPortUsage.Default, "D2_CW", null, valWordInit); } var syncBuilder = new DefaultAlgorithmBuilder(); syncBuilder.If(clkSignal.ToSignalRef(SignalRef.EReferencedProperty.RisingEdge)); syncBuilder.Store(rcwSignal.ToSignalRef(SignalRef.EReferencedProperty.Next), ((ISignal)cwSignal[_vcf.ValueWordWidth - 1, 0]).ToSignalRef(SignalRef.EReferencedProperty.Cur)); if (registered) { syncBuilder.Store(rrcwSignal.ToSignalRef(SignalRef.EReferencedProperty.Next), rcwSignal.ToSignalRef(SignalRef.EReferencedProperty.Cur)); } foreach (var ms in _strings) { ms.AssembleStagedDecoderSync(binder, syncBuilder, cwSignal, registered); } syncBuilder.EndIf(); var syncFunc = syncBuilder.Complete(); syncFunc.Name = "cwdecode_sync"; binder.CreateProcess(SystemSharp.Components.Process.EProcessKind.Triggered, syncFunc, clkSignal.Descriptor); var combBuilder = new DefaultAlgorithmBuilder(); var sensitivity = new HashSet <ISignalOrPortDescriptor>(); sensitivity.Add(cwSignal.Descriptor); sensitivity.Add(rcwSignalDesc); if (registered) { sensitivity.Add(rrcwSignal.Descriptor); } foreach (var ms in _strings) { ms.AssembleStagedDecoderComb(combBuilder, registered ? rrcwSignal : rcwSignal, sensitivity, registered); } var combFunc = combBuilder.Complete(); combFunc.Name = "cwdecode_comb"; binder.CreateProcess(SystemSharp.Components.Process.EProcessKind.Triggered, combFunc, sensitivity.ToArray()); }
/// <summary> /// Constructs a new instance. /// </summary> /// <param name="inIntWidth">operand integer bits</param> /// <param name="fracWidth">operand and result fractional bits /// (operand and result automatically have same number of fractional bits)</param> /// <param name="outIntWidth">result integer bits</param> public FixFPMod1(int inIntWidth, int fracWidth, int outIntWidth) { Contract.Requires(inIntWidth >= 2 && outIntWidth >= 2); InIntWidth = inIntWidth; OutIntWidth = outIntWidth; FracWidth = fracWidth; _zeroes = StdLogicVector._0s(FracWidth); _padZeroes = StdLogicVector._0s(OutIntWidth - 1); _padOnes = StdLogicVector._1s(OutIntWidth - 1); TASite = new FPMod1TransactionSite(this); }
private void HandleStoreVar(XILSInstr xilsi) { var var = (Variable)xilsi.StaticOperand; var mms = GetVariableLayout(var); Unsigned addr = mms.BaseAddress; var addrType = TypeDescriptor.GetTypeOf(addr); int addrSize = addr.Size; var rawWordType = Mapper.MarshalInfo.GetRawWordType(); uint concatSize = (uint)(mms.Size * Mapper.MarshalInfo.WordSize); var concatType = TypeDescriptor.GetTypeOf(StdLogicVector._0s(concatSize)); var valueType = var.Type; var slvValue = Marshal.SerializeForHW(valueType.GetSampleInstance()); var rawValueType = TypeDescriptor.GetTypeOf(slvValue); if (!rawValueType.Equals(valueType)) { Emit(_iset.Convert().CreateStk(1, valueType, rawValueType)); } if (!rawValueType.Equals(concatType)) { Emit(_iset.Convert().CreateStk(1, rawValueType, concatType)); } int shiftSize = MathExt.CeilLog2(concatSize); if (mms.Layout.Size > 1) { Emit(_iset.Dup().CreateStk(1, concatType, concatType, concatType)); } Unsigned shift = Unsigned.FromULong(Mapper.MarshalInfo.WordSize, shiftSize); TypeDescriptor shiftType = TypeDescriptor.GetTypeOf(shift); for (ulong i = 0; i < mms.Layout.Size; i++) { if (!rawWordType.Equals(concatType)) { Emit(_iset.Convert().CreateStk(1, concatType, rawWordType)); } Emit(_iset.WrMemFix(Mapper.DefaultRegion, addr).CreateStk(1, rawWordType)); if (i < mms.Layout.Size - 1) { if (i + 1 < mms.Layout.Size - 1) { Emit(_iset.Dup().CreateStk(1, concatType, concatType, concatType)); } Emit(_iset.LdConst(shift).CreateStk(0, shiftType)); Emit(_iset.RShift().CreateStk(1, concatType, concatType)); } addr = (addr + Unsigned.FromULong(1, 1)).Resize(addrSize); } }
protected override void PreInitialize() { if (StartupAddr.Size != AddrWidth) { throw new InvalidOperationException("BCU: Invalid startup address"); } _lastAddr = new SLVSignal(StdLogicVector._0s(AddrWidth)); _outAddr = new SLVSignal(AddrWidth); if (Latency > 1) { _rstPat = StdLogicVector._1s(Latency - 1); _rstq = new SLVSignal(_rstPat); } }
/// <summary> /// Constructs a new instance. /// </summary> /// <param name="dataWidth">bit-width of operand</param> /// <param name="pipelineDepth">number of pipeline stages, i.e. computation latency</param> public Shifter(int dataWidth, int pipelineDepth) { DataWidth = dataWidth; ShiftWidth = MathExt.CeilLog2(dataWidth); PipelineDepth = pipelineDepth; _y = new SLVSignal(DataWidth); _pad = StdLogicVector._0s(DataWidth); _pipe = new RegPipe(PipelineDepth, DataWidth); Bind(() => { _pipe.Clk = Clk; _pipe.Din = _y; _pipe.Dout = Y; }); TASite = new ShifterTransactor(this); }