private void GenerateBuiltInComponents()
{
ProtoCore.VHDL.AST.ModuleNode module = null;
ProtoCore.VHDL.Utils.FunctionCallToComponentMap = new Dictionary <string, string>();
// ALU signals
// Port entries
ProtoCore.VHDL.AST.PortEntryNode reset = new ProtoCore.VHDL.AST.PortEntryNode("reset", ProtoCore.VHDL.AST.PortEntryNode.Direction.In, 1);
List <ProtoCore.VHDL.AST.PortEntryNode> listPortEntry = new List <ProtoCore.VHDL.AST.PortEntryNode>();
listPortEntry.Add(reset);
listPortEntry.Add(new ProtoCore.VHDL.AST.PortEntryNode(ProtoCore.VHDL.Constants.ComponentName.ALU.OpSignal1, ProtoCore.VHDL.AST.PortEntryNode.Direction.In, 32));
listPortEntry.Add(new ProtoCore.VHDL.AST.PortEntryNode(ProtoCore.VHDL.Constants.ComponentName.ALU.OpSignal2, ProtoCore.VHDL.AST.PortEntryNode.Direction.In, 32));
listPortEntry.Add(new ProtoCore.VHDL.AST.PortEntryNode(ProtoCore.VHDL.Constants.ComponentName.ALU.OpSignalResult, ProtoCore.VHDL.AST.PortEntryNode.Direction.Out, 32));
// ALU add
module = CreateModule(ProtoCore.VHDL.Constants.ComponentName.ALU.Add, true);
module.Entity = new ProtoCore.VHDL.AST.EntityNode(ProtoCore.VHDL.Constants.ComponentName.ALU.Add, listPortEntry);
ProtoCore.VHDL.Utils.FunctionCallToComponentMap.Add(ProtoCore.DSASM.Op.GetOpFunction(ProtoCore.DSASM.Operator.add), ProtoCore.VHDL.Constants.ComponentName.ALU.Add);
// ALU sub
module = CreateModule(ProtoCore.VHDL.Constants.ComponentName.ALU.Sub, true);
module.Entity = new ProtoCore.VHDL.AST.EntityNode(ProtoCore.VHDL.Constants.ComponentName.ALU.Add, listPortEntry);
ProtoCore.VHDL.Utils.FunctionCallToComponentMap.Add(ProtoCore.DSASM.Op.GetOpFunction(ProtoCore.DSASM.Operator.sub), ProtoCore.VHDL.Constants.ComponentName.ALU.Sub);
// ALU mul
module = CreateModule(ProtoCore.VHDL.Constants.ComponentName.ALU.Mul, true);
module.Entity = new ProtoCore.VHDL.AST.EntityNode(ProtoCore.VHDL.Constants.ComponentName.ALU.Add, listPortEntry);
ProtoCore.VHDL.Utils.FunctionCallToComponentMap.Add(ProtoCore.DSASM.Op.GetOpFunction(ProtoCore.DSASM.Operator.mul), ProtoCore.VHDL.Constants.ComponentName.ALU.Mul);
// ALU div
module = CreateModule(ProtoCore.VHDL.Constants.ComponentName.ALU.Div, true);
module.Entity = new ProtoCore.VHDL.AST.EntityNode(ProtoCore.VHDL.Constants.ComponentName.ALU.Add, listPortEntry);
ProtoCore.VHDL.Utils.FunctionCallToComponentMap.Add(ProtoCore.DSASM.Op.GetOpFunction(ProtoCore.DSASM.Operator.div), ProtoCore.VHDL.Constants.ComponentName.ALU.Div);
}
public ProtoCore.VHDL.AST.ModuleNode CreateAndAppendTopModule()
{
ProtoCore.VHDL.AST.ModuleNode module = CreateAndAppendDefaultModule(TopLevelModuleName);
module.IsTopModule = true;
return(module);
}
