private bool Print(int incr1, int incr2, FPGATypes.Placement placement1, FPGATypes.Placement placement2, IdentifierManager.RegexTypes filterType, int[] sliceIndeces, string groupName)
{
string filter = IdentifierManager.Instance.GetRegex(filterType);
Tile tile1 = TileSelectionManager.Instance.GetSelectedTile(filter, placement1);
Tile tile2 = TileSelectionManager.Instance.GetSelectedTile(filter, placement2);
if (tile1 == null || tile2 == null)
{
return(false);
}
if (tile1.Slices.Count == 0 || tile2.Slices.Count == 0)
{
return(false);
}
switch (FPGA.FPGA.Instance.BackendType)
{
case FPGATypes.BackendType.ISE:
// Virtex 6 hard coded
if (FPGA.FPGA.Instance.Family == FPGATypes.FPGAFamily.Virtex6 && filterType == IdentifierManager.RegexTypes.BRAM)
{
if (tile1.Slices.Count != 3 || tile2.Slices.Count != 3)
{
throw new ArgumentException("Unexpected number of slices in Virtex6 RAM tile");
}
string lowerLeftSlice = tile1.Slices[0].ToString();
string upperRightSlice = tile2.Slices[1].ToString();
string firstLine = "AREA_GROUP \"" + groupName + "\"" + " RANGE = " + lowerLeftSlice + ":" + upperRightSlice + "; # generated_by_GoAhead";
OutputManager.WriteUCFOutput(firstLine);
string lowerLeftRAMB36Slice = tile1.Slices[2].ToString();
string upperRightRAMB36Slice = tile2.Slices[2].ToString();
string secondLine = "AREA_GROUP \"" + groupName + "\"" + " RANGE = " + lowerLeftRAMB36Slice + ":" + upperRightRAMB36Slice + "; # generated_by_GoAhead";
OutputManager.WriteUCFOutput(secondLine);
}
else if (FPGA.FPGA.Instance.Family == FPGATypes.FPGAFamily.Virtex6 && filterType == IdentifierManager.RegexTypes.DSP)
{
if (tile1.Slices.Count != 3 || tile2.Slices.Count != 3)
{
throw new ArgumentException("Unexpected number of slices in Virtex6 DSP tile");
}
string lowerLeftSlice = tile1.Slices[0].ToString();
string upperRightSlice = tile2.Slices[1].ToString();
string firstLine = "AREA_GROUP \"" + groupName + "\"" + " RANGE = " + lowerLeftSlice + ":" + upperRightSlice + "; # generated_by_GoAhead";
OutputManager.WriteUCFOutput(firstLine);
}
else
{
// other devices "genericly"
for (int i = 0; i < sliceIndeces.Length; i += 2)
{
string lowerLeftSlice = tile1.Slices[sliceIndeces[i + incr1]].ToString();
string upperRightSlice = tile2.Slices[sliceIndeces[i + incr2]].ToString();
string secondLine = "AREA_GROUP \"" + groupName + "\"" + " RANGE = " + lowerLeftSlice + ":" + upperRightSlice + "; # generated_by_GoAhead";
OutputManager.WriteUCFOutput(secondLine);
}
}
break;
case FPGATypes.BackendType.Vivado:
for (int i = 0; i < sliceIndeces.Length; i += 2) // why < Length?
{
string lowerLeftSlice = tile1.Slices[sliceIndeces[i + incr1]].ToString();
string upperRightSlice = tile2.Slices[sliceIndeces[i + incr2]].ToString();
string secondLine = "resize_pblock [get_pblocks " + groupName + "] -add {" + lowerLeftSlice + ":" + upperRightSlice + "}; # generated_by_GoAhead";
OutputManager.WriteTCLOutput(secondLine);
}
break;
}
return(true);
}
private List <Tile> GetAnchors(FPGA.FPGATypes.InterfaceDirection dir, int columns, bool streaming, out List <Tile> tilesToReleaseWiresOn)
{
List <Tile> result = new List <Tile>();
tilesToReleaseWiresOn = new List <Tile>();
FPGATypes.Placement placement = 0;
switch (dir)
{
case FPGATypes.InterfaceDirection.East: { placement = FPGATypes.Placement.UpperRight; break; }
case FPGATypes.InterfaceDirection.West: { placement = FPGATypes.Placement.UpperLeft; break; }
default: { throw new ArgumentException("Can not hanlde direction " + dir); }
}
Tile anchor = TileSelectionManager.Instance.GetUserSelectedTile(
IdentifierManager.Instance.GetRegex(IdentifierManager.RegexTypes.CLB),
IslandName,
placement);
// move this way to collect anchors for columns
int xIncrement = 0;
int yIncrement = 0;
switch (dir)
{
case FPGATypes.InterfaceDirection.East: { xIncrement = -1; yIncrement = 0; break; }
case FPGATypes.InterfaceDirection.West: { xIncrement = 1; yIncrement = 0; break; }
}
xIncrement *= m_columnStepWidth;
yIncrement *= m_columnStepWidth;
// for module anchors move the anchors out of the partial area
if (BuildTarget == Target.Module)
{
if (m_islandName.Equals("pr5"))
{
}
int xAnchorShift = 0;
int yAnchorShift = 0;
switch (dir)
{
case FPGATypes.InterfaceDirection.East: { xAnchorShift = 1; yAnchorShift = 0; break; }
case FPGATypes.InterfaceDirection.West: { xAnchorShift = -1; yAnchorShift = 0; break; }
}
xAnchorShift *= m_columnStepWidth;
yAnchorShift *= m_columnStepWidth;
// TODO here, we assume double lines
Tile start = anchor;
for (int column = 0; column < columns; column++)
{
// besser mit DoubleLine (parameter) von Anker auf den naechsten CLB gehen
/*
* do
* {
* anchor = Search.Navigator.GetNextCLB(anchor, xAnchorShift, yAnchorShift, tilesToReleaseWiresOn);
* }
* while (Math.Abs(start.LocationX - anchor.LocationX) % 2 != 0);
* */
anchor = Navigator.GetNextCLB(anchor, xAnchorShift, yAnchorShift, tilesToReleaseWiresOn);
anchor = Navigator.GetNextCLB(anchor, xAnchorShift, yAnchorShift, tilesToReleaseWiresOn);
}
}
// first anchor
result.Add(anchor);
Tile current = anchor;
// start with 1 as we have the anchor added already
for (int column = 1; column < columns; column++)
{
current = Navigator.GetNextCLB(current, xIncrement, yIncrement, tilesToReleaseWiresOn);
result.Add(current);
}
// East 0 1 2
// West 2 1 0 -> Reverse
if (dir == FPGATypes.InterfaceDirection.East)
{
result.Reverse();
}
return(result);
}
