public void Sbfm_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)][Random(2)] ulong Xn,
[Values(0u, 31u, 32u, 63u)][Random(0u, 63u, 2)] uint immr,
[Values(0u, 31u, 32u, 63u)][Random(0u, 63u, 2)] uint imms)
{
uint Opcode = 0x93400000; // SBFM X0, X0, #0, #0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Xn));
Base.Sbfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
}
public void Orr_N0_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)][Random(2)] ulong Xn,
[Values(0u, 15u, 16u, 30u)][Random(0u, 30u, 2)] uint imms, // <imm>
[Values(0u, 15u, 16u, 31u)][Random(0u, 31u, 2)] uint immr) // <imm>
{
uint Opcode = 0xB2000000; // ORR X0, X0, #0x100000001
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
Bits Op = new Bits(Opcode);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
AArch64.X((int)Rn, new Bits(Xn));
Base.Orr_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
if (Rd != 31)
{
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
ulong SP = AArch64.SP(64).ToUInt64();
Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP));
}
}
public void Bfm_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Random(2)] uint _Wd,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)][Random(2)] uint Wn,
[Values(0u, 15u, 16u, 31u)][Random(0u, 31u, 2)] uint immr,
[Values(0u, 15u, 16u, 31u)][Random(0u, 31u, 2)] uint imms)
{
uint Opcode = 0x33000000; // BFM W0, W0, #0, #0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
AThreadState ThreadState = SingleOpcode(Opcode, X0: _Wd, X1: Wn, X31: _W31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rd, new Bits(_Wd));
AArch64.X((int)Rn, new Bits(Wn));
Base.Bfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
}
else
{
Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
}
}
public void Umulh_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(2u, 31u)] uint Rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)][Random(16)] ulong Xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)][Random(16)] ulong Xm)
{
uint Opcode = 0x9BC07C00; // UMULH X0, X0, X0
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Xn));
AArch64.X((int)Rm, new Bits(Xm));
Base.Umulh(Op[20, 16], Op[9, 5], Op[4, 0]);
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
CompareAgainstUnicorn();
}
public void Eor_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)][Random(2)] uint Wn,
[Values(0u, 15u, 16u, 30u)][Random(0u, 30u, 2)] uint imms, // <imm>
[Values(0u, 15u, 16u, 31u)][Random(0u, 31u, 2)] uint immr) // <imm>
{
uint Opcode = 0x52000000; // EOR W0, W0, #0x1
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
Bits Op = new Bits(Opcode);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
AArch64.X((int)Rn, new Bits(Wn));
Base.Eor_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
if (Rd != 31)
{
uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
}
else
{
uint WSP = AArch64.SP(32).ToUInt32();
Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP));
}
}
public void Movn_64bit([Values(0u, 31u)] uint Rd,
[Values(0u, 65535u)][Random(0u, 65535u, 128)] uint imm,
[Values(0u, 16u, 32u, 48u)] uint shift)
{
uint Opcode = 0x92800000; // MOVN X0, #0, LSL #0
Opcode |= ((Rd & 31) << 0);
Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X31: _X31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
Base.Movn(Op[31], Op[22, 21], Op[20, 5], Op[4, 0]);
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
CompareAgainstUnicorn();
}
public void Movk_32bit([Values(0u, 31u)] uint Rd,
[Random(12)] uint _Wd,
[Values(0u, 65535u)][Random(0u, 65535u, 10)] uint imm,
[Values(0u, 16u)] uint shift)
{
uint Opcode = 0x72800000; // MOVK W0, #0, LSL #0
Opcode |= ((Rd & 31) << 0);
Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
AThreadState ThreadState = SingleOpcode(Opcode, X0: _Wd, X31: _W31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rd, new Bits(_Wd));
Base.Movk(Op[31], Op[22, 21], Op[20, 5], Op[4, 0]);
uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
}
else
{
Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
}
CompareAgainstUnicorn();
}
public void Clz_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)][Random(256)] ulong Xn)
{
uint Opcode = 0xDAC01000; // CLZ X0, X0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Xn));
Base.Clz(Op[31], Op[9, 5], Op[4, 0]);
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
}
public void Cls_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)][Random(256)] uint Wn)
{
uint Opcode = 0x5AC01400; // CLS W0, W0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Wn));
Base.Cls(Op[31], Op[9, 5], Op[4, 0]);
uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
}
else
{
Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
}
}
public void Madd_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(2u, 31u)] uint Rm,
[Values(3u, 31u)] uint Ra,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)][Random(2)] uint Wn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)][Random(2)] uint Wm,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)][Random(2)] uint Wa)
{
uint Opcode = 0x1B000000; // MADD W0, W0, W0, W0
Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Wa, X31: _W31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Wn));
AArch64.X((int)Rm, new Bits(Wm));
AArch64.X((int)Ra, new Bits(Wa));
Base.Madd(Op[31], Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]);
uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
}
else
{
Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
}
}
public void Msub_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(2u, 31u)] uint Rm,
[Values(3u, 31u)] uint Ra,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)][Random(2)] ulong Xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)][Random(2)] ulong Xm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)][Random(2)] ulong Xa)
{
uint Opcode = 0x9B008000; // MSUB X0, X0, X0, X0
Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X3: Xa, X31: _X31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Xn));
AArch64.X((int)Rm, new Bits(Xm));
AArch64.X((int)Ra, new Bits(Xa));
Base.Msub(Op[31], Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]);
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
}
public void Subs_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)][Random(8)] uint Wn_WSP,
[Values(0u, 4095u)][Random(0u, 4095u, 10)] uint imm,
[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
{
uint Opcode = 0x71000000; // SUBS W0, W0, #0, LSL #0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
Bits Op = new Bits(Opcode);
AThreadState ThreadState;
if (Rn != 31)
{
ThreadState = SingleOpcode(Opcode, X1: Wn_WSP);
AArch64.X((int)Rn, new Bits(Wn_WSP));
}
else
{
ThreadState = SingleOpcode(Opcode, X31: Wn_WSP);
AArch64.SP(new Bits(Wn_WSP));
}
Base.Subs_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]);
if (Rd != 31)
{
uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
}
else
{
uint _W31 = AArch64.SP(32).ToUInt32();
Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
}
Assert.Multiple(() =>
{
Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
});
CompareAgainstUnicorn();
}
public void Adds_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)][Random(8)] ulong Xn_SP,
[Values(0u, 4095u)][Random(0u, 4095u, 10)] uint imm,
[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
{
uint Opcode = 0xB1000000; // ADDS X0, X0, #0, LSL #0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
Bits Op = new Bits(Opcode);
AThreadState ThreadState;
if (Rn != 31)
{
ThreadState = SingleOpcode(Opcode, X1: Xn_SP);
AArch64.X((int)Rn, new Bits(Xn_SP));
}
else
{
ThreadState = SingleOpcode(Opcode, X31: Xn_SP);
AArch64.SP(new Bits(Xn_SP));
}
Base.Adds_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]);
if (Rd != 31)
{
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
ulong _X31 = AArch64.SP(64).ToUInt64();
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
Assert.Multiple(() =>
{
Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
});
CompareAgainstUnicorn();
}
public void Sub_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)][Random(8)] uint Wn_WSP,
[Values(0u, 4095u)][Random(0u, 4095u, 10)] uint imm,
[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
{
uint Opcode = 0x51000000; // SUB W0, W0, #0, LSL #0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
Bits Op = new Bits(Opcode);
AThreadState ThreadState;
if (Rn != 31)
{
ThreadState = SingleOpcode(Opcode, X1: Wn_WSP);
AArch64.X((int)Rn, new Bits(Wn_WSP));
}
else
{
ThreadState = SingleOpcode(Opcode, X31: Wn_WSP);
AArch64.SP(new Bits(Wn_WSP));
}
Base.Sub_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]);
if (Rd != 31)
{
uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
}
else
{
uint WSP = AArch64.SP(32).ToUInt32();
Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP));
}
CompareAgainstUnicorn();
}
public void Add_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)][Random(8)] ulong Xn_SP,
[Values(0u, 4095u)][Random(0u, 4095u, 10)] uint imm,
[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
{
uint Opcode = 0x91000000; // ADD X0, X0, #0, LSL #0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
Bits Op = new Bits(Opcode);
AThreadState ThreadState;
if (Rn != 31)
{
ThreadState = SingleOpcode(Opcode, X1: Xn_SP);
AArch64.X((int)Rn, new Bits(Xn_SP));
}
else
{
ThreadState = SingleOpcode(Opcode, X31: Xn_SP);
AArch64.SP(new Bits(Xn_SP));
}
Base.Add_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]);
if (Rd != 31)
{
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
ulong SP = AArch64.SP(64).ToUInt64();
Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP));
}
CompareAgainstUnicorn();
}
public void Ands_N1_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)][Random(2)] ulong Xn,
[Values(0u, 31u, 32u, 62u)][Random(0u, 62u, 2)] uint imms, // <imm>
[Values(0u, 31u, 32u, 63u)][Random(0u, 63u, 2)] uint immr) // <imm>
{
uint Opcode = 0xF2400000; // ANDS X0, X0, #0x1
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
Bits Op = new Bits(Opcode);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
AArch64.X((int)Rn, new Bits(Xn));
Base.Ands_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
if (Rd != 31)
{
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
Assert.Multiple(() =>
{
Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
});
CompareAgainstUnicorn();
}
public void Ands_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)][Random(2)] uint Wn,
[Values(0u, 15u, 16u, 30u)][Random(0u, 30u, 2)] uint imms, // <imm>
[Values(0u, 15u, 16u, 31u)][Random(0u, 31u, 2)] uint immr) // <imm>
{
uint Opcode = 0x72000000; // ANDS W0, W0, #0x1
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
Bits Op = new Bits(Opcode);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
AArch64.X((int)Rn, new Bits(Wn));
Base.Ands_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
if (Rd != 31)
{
Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
}
else
{
Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
}
Assert.Multiple(() =>
{
Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
});
CompareAgainstUnicorn();
}
public void Umaddl_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(2u, 31u)] uint Rm,
[Values(3u, 31u)] uint Ra,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)][Random(2)] uint Wn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)][Random(2)] uint Wm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)][Random(2)] ulong Xa)
{
uint Opcode = 0x9BA00000; // UMADDL X0, W0, W0, X0
Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Xa, X31: _X31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Wn));
AArch64.X((int)Rm, new Bits(Wm));
AArch64.X((int)Ra, new Bits(Xa));
Base.Umaddl(Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]);
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
CompareAgainstUnicorn();
}