/// <summary>
/// Execute a command
/// </summary>
private string Command(string cmd)
{
try
{
string[] tokens = cmd.Split(new string[] { " " }, StringSplitOptions.RemoveEmptyEntries);
if (tokens.Length == 0)
{
return("");
}
switch (tokens[0])
{
case "?":
case "h":
return(Environment.NewLine +
"p - Dump the content of the PLA table" + Environment.NewLine +
"p [#] - For a given PLA entry # (dec) show opcodes that trigger it" + Environment.NewLine +
"m [#] - Match opcode # (hex) with a PLA entry (or match 0-FF)" + Environment.NewLine +
"g - Generate a Verilog PLA module" + Environment.NewLine +
"t [#] <#> - Show opcode table in various ways" + Environment.NewLine +
" 0 - Display number of PLA entries that trigger on each opcode" + Environment.NewLine +
" 1 - For each opcode, display all PLA entry numbers that trigger" + Environment.NewLine +
" <#> - Add a * to opcodes for which the specified PLA entry triggers" + Environment.NewLine +
"q 101000... Query PLA table string" + Environment.NewLine +
"c - Clear the screen");
case "p": if (tokens.Length > 1)
{
MatchOpcodes(modifier, tokens[1]);
}
else
{
pla.Dump();
}
break;
case "m": MatchPLA(tokens.Length > 1 ? tokens[1] : "");
break;
case "g": pla.GenVerilogPla();
break;
case "c": BtClearClick(null, null);
break;
case "t":
{
int arg1 = 0, arg2 = -1;
if (tokens.Length > 1)
{
arg1 = ScanNumber(tokens[1], 10);
}
if (tokens.Length > 2)
{
arg2 = ScanNumber(tokens[2], 10);
}
if (arg1 == 0 || arg1 == 1)
{
List <int> tagged = pla.Table(modifier, arg1, arg2);
DumpOpcodeTable(tagged);
}
else
{
ClassLog.Log("Invalid table number!");
}
}
break;
case "q": pla.QueryPla(tokens[1].Trim());
break;
default:
return("?");
}
}
catch (Exception ex)
{
ClassLog.Log("Error: " + ex.Message);
}
return(string.Empty);
}
/// <summary>
/// Read the master PLA table from a text file
/// </summary>
public bool Load(string filename)
{
// Read each line of the file into a string array. Each element
// of the array is one line of the file.
ClassLog.Log("Loading PLA: " + filename);
try
{
string[] lines = File.ReadAllLines(filename);
pla.Clear();
foreach (string line in lines)
{
if (line[0] == '#')
{
continue;
}
var p = new ClassPlaEntry();
if (p.Init(line))
{
pla.Add(p);
}
}
}
catch (Exception ex)
{
ClassLog.Log(ex.Message);
return(false);
}
ClassLog.Log(string.Format("Total {0} PLA lines", pla.Count()));
////============================================================
//// Ignore duplicate PLA entries
//IgnoredPla.Add(98); // Duplicate of 37
//IgnoredPla.Add(94); // Duplicate of 12 and 18
//IgnoredPla.Add(93); // Duplicate of 11 and 19
//IgnoredPla.Add(90); // Duplicate of 26
//IgnoredPla.Add(87); // Duplicate of 83
//IgnoredPla.Add(71); // Duplicate of 25
//IgnoredPla.Add(63); // Duplicate of 17
//IgnoredPla.Add(60); // Duplicate of 15
//IgnoredPla.Add(41); // Duplicate of 3
//IgnoredPla.Add(36); // Duplicate of 8
//IgnoredPla.Add(32); // Duplicate of 4
//IgnoredPla.Add(19); // Duplicate of 11 and 93
//IgnoredPla.Add(18); // Duplicate of 12 and 94
////============================================================
//// Special signals (not instructions)
//IgnoredPla.Add(91); // This signal goes along block IN/OUT instructions.
//IgnoredPla.Add(75); // This signal specifies a decrement operation for PLA 53, 66 and 105. Otherwise, it is an increment.
//IgnoredPla.Add(55); // This signal specifies (HL) addressing for all CB-table instructions, PLA entries 70, 72, 73, 74.
//IgnoredPla.Add(44); // This signal specifies a regular CB opcode (ignoring IX/IY).
//IgnoredPla.Add(33); // This signal specifies whether the register is being loaded or stored to memory for PLA entry 31.
//IgnoredPla.Add(28); // This signal specifies the OUT operation for PLA 37. Otherwise, it is operation.
//IgnoredPla.Add(27); // This signal goes along individual IN/OUT instructions in the ED table.
//IgnoredPla.Add(16); // This signal specifies a PUSH operation for PLA23. Otherwise, it is a POP operation.
//IgnoredPla.Add(13); // This signal specifies whether the value is being loaded or stored for PLA entries 8, 30 and 38.
//IgnoredPla.Add(0); // This signal specifies *not* to repeat block instructions.
////============================================================
//// Ignore our own reserved entries
//IgnoredPla.Add(107);
//IgnoredPla.Add(106);
//============================================================
// Remove op-bits so we the output is more readable
IgnoredPla.Add(99);
IgnoredPla.Add(100);
IgnoredPla.Add(101);
IgnoredPla.Add(102);
IgnoredPla.Add(103);
IgnoredPla.Add(104);
// Remove ALU operation entries so the output is more readable
IgnoredPla.Add(88);
IgnoredPla.Add(86);
IgnoredPla.Add(85);
IgnoredPla.Add(84);
IgnoredPla.Add(80);
IgnoredPla.Add(79);
IgnoredPla.Add(78);
IgnoredPla.Add(76);
//============================================================
// Signals not used in the Timings spreadsheet. For those, PLA table entries are not generated.
// This list is used only when generating the PLA table.
NotUsedPla.Add(67); // This signal defines a specific in(), but we use in/out pla[27] + pla[34]
NotUsedPla.Add(62); // This signal is issued for all CB opcodes
NotUsedPla.Add(54); // This signal specifies every CB with IX/IY
NotUsedPla.Add(22); // This signal specifies CB prefix w/o IX/IY
NotUsedPla.Add(14); // This signal specifies a decrement operation for PLA 9. Otherwise, it is an increment.
NotUsedPla.Add(4); // This signal goes along instructions that access I and R register (PLA 57 and 83).
//============================================================
// Mark all PLA entries we decided to ignore
foreach (var p in pla)
{
if (IgnoredPla.Contains <int>(p.N))
{
p.Ignored = true;
}
}
return(true);
}