public override SparcInstruction Decode(uint wInstr, SparcDisassembler dasm)
{
uint i = ((wInstr >> 25) & 0xF) + offset;
SparcInstruction instr = branchOps[i].Decode(wInstr, dasm);
instr.InstructionClass |= ((wInstr & (1u << 29)) != 0) ? InstrClass.Annul : 0;
return(instr);
}
public override SparcInstruction Decode(SparcDisassembler dasm, uint wInstr)
{
uint i = ((wInstr >> 25) & 0xF) + offset;
SparcInstruction instr = branchOps[i].Decode(dasm, wInstr);
if ((wInstr & (1u << 29)) != 0)
{
instr.Annul = true;
}
return(instr);
}
public override SparcInstruction Decode(uint wInstr, SparcDisassembler dasm)
{
foreach (var m in mutators)
{
if (!m(wInstr, dasm))
{
return(invalid.Decode(wInstr, dasm));
}
}
return(new SparcInstruction
{
Mnemonic = code,
InstructionClass = iclass,
Operands = dasm.ops.ToArray()
});
}
public virtual SparcInstruction Decode(SparcDisassembler dasm, uint wInstr)
{
foreach (var m in mutators)
{
if (!m(wInstr, dasm))
{
return(invalid.Decode(dasm, wInstr));
}
}
return(new SparcInstruction
{
Opcode = code,
IClass = iclass,
Op1 = dasm.ops.Count > 0 ? dasm.ops[0] : null,
Op2 = dasm.ops.Count > 1 ? dasm.ops[1] : null,
Op3 = dasm.ops.Count > 2 ? dasm.ops[2] : null,
});
}
public override SparcInstruction Decode(SparcDisassembler dasm, uint wInstr)
{
return(fpOprecs[(wInstr >> 5) & 0x1FF].Decode(dasm, wInstr));
}
public virtual SparcInstruction Decode(SparcDisassembler dasm, uint wInstr)
{
if (fmt == null)
{
return new SparcInstruction {
Opcode = code
}
}
;
var ops = new List <MachineOperand>();
int i = 0;
while (i != fmt.Length)
{
char c = fmt[i++];
if (c == ',')
{
continue;
}
switch (c)
{
default: throw new NotSupportedException(string.Format("Format {0} not supported.", c));
case 'r': // Register reference
ops.Add(GetRegisterOperand(wInstr, ref i));
break;
case 'f': // FPU register
ops.Add(GetFpuRegisterOperand(wInstr, ref i));
break;
case 'A':
ops.Add(GetAlternateSpaceOperand(wInstr, GetOperandSize(ref i)));
break;
case 'I': // 22-bit immediate value
ops.Add(GetImmOperand(wInstr, 22));
break;
case 'J':
ops.Add(GetAddressOperand(dasm.imageReader.Address, wInstr));
break;
case 'M':
ops.Add(GetMemoryOperand(wInstr, GetOperandSize(ref i)));
break;
case 'R': // Register or simm13.
// if 's', return a signed immediate operand where relevant.
ops.Add(GetRegImmOperand(wInstr, fmt[i++] == 's', 13));
break;
case 'S': // Register or uimm5
ops.Add(GetRegImmOperand(wInstr, false, 6));
break;
case 'T': // trap number
ops.Add(GetRegImmOperand(wInstr, false, 7));
break;
case '%':
ops.Add(GetRegByName(ref i));
break;
}
}
return(new SparcInstruction
{
Opcode = code,
Op1 = ops.Count > 0 ? ops[0] : null,
Op2 = ops.Count > 1 ? ops[1] : null,
Op3 = ops.Count > 2 ? ops[2] : null,
});
}
private static bool nyi(uint wInstr, SparcDisassembler dasm)
{
dasm.NotYetImplemented(wInstr, "NYI");
return(false);
}
// trap number
private static bool T(uint wInstr, SparcDisassembler dasm)
{
dasm.ops.Add(GetRegImmOperand(wInstr, false, 7));
return(true);
}
private static bool JJ(uint wInstr, SparcDisassembler dasm)
{
dasm.ops.Add(new AddressOperand((dasm.imageReader.Address - 4) + ((int)wInstr << 2)));
return(true);
}
private static bool J(uint wInstr, SparcDisassembler dasm)
{
dasm.ops.Add(GetAddressOperand(dasm.imageReader.Address, wInstr));
return(true);
}
// 22-bit immediate value
private static bool I(uint wInstr, SparcDisassembler dasm)
{
dasm.ops.Add(GetImmOperand(wInstr, 22));
return(true);
}
internal static bool J19(uint wInstr, SparcDisassembler dasm)
{
dasm.ops.Add(GetAddressOperand(dasm.imageReader.Address, wInstr, 19));
return(true);
}
public override SparcInstruction Decode(SparcDisassembler dasm, uint wInstr)
{
return(fpDecoders[(wInstr >> 4) & 0xFF].Decode(dasm, wInstr));
}
// 22-bit immediate value
internal static bool I(uint wInstr, SparcDisassembler dasm)
{
dasm.ops.Add(GetImmOperand(wInstr, 22));
return true;
}