public SchedGPARBS(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
{
bankLoad = new int[Config.Ng,Config.memory.numRanks,Config.memory.numBanks];
maxBankLoad = new int[Config.Ng];
totalLoad = new int[Config.Ng];
overallRank = new int[Config.Ng];
}
/* HWA CODE */
// Override this for other algorithms
virtual protected bool schedMaskCheck(SchedBuf tgt)
{
if (Config.sched.hwa_str_priority)
{
if (Config.sched.hwa_priority_per_bank)
{
int bank_id = tgt.mreq.bank_index;
if (bank_reserve[bank_id] == int.MaxValue)
{
return(true);
}
else if (getPriority(tgt) >= bank_reserve_priority[bank_id])
{
return(true);
}
else
{
return(false);
}
}
else
{
return(schedMask[tgt.mreq.request.requesterID]);
}
}
else
{
return(true);
}
}
public SchedTCMwithPriorHWA(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
{
rank = new int[Config.Ng];
service = new double[Config.Ng];
curr_service = new double[Config.Ng];
service_bank_cnt = new uint[Config.Ng];
mpki = new double[Config.Ng];
prev_cache_miss = new ulong[Config.Ng];
prev_inst_cnt = new ulong[Config.Ng];
rbl = new double[Config.Ng];
shadow_row_hits = new ulong[Config.Ng];
blp = new double[Config.Ng];
blp_sample_sum = new uint[Config.Ng];
quantum_cycles_left = Config.sched.quantum_cycles;
nice = new int[Config.Ng];
shuffle_cycles_left = Config.sched.shuffle_cycles;
this.chan = chan;
log_cnt = 0;
req_num = new int[Config.Ng];
buf_num = new int[Config.Ng];
hwa_prior = new int[Config.HWANum];
memreq_cnt = new int[Config.Ng];
for( int i = 0; i < Config.Ng; i++ )
memreq_cnt[i] = 0;
}
// Override this for other algorithms
override protected SchedBuf Pick(SchedBuf winner, SchedBuf candidate)
{
if (winner == null)
{
winner = candidate;
}
else if (!winner.Urgent && candidate.Urgent) // urgent wins over non-urgent
{
winner = candidate;
}
else if (winner.Urgent && candidate.Urgent && candidate.IsOlderThan(winner))
{
winner = candidate;
}
else if (winner.FromGPU && !candidate.FromGPU) // cores win over GPU
{
winner = candidate;
}
else if (winner.IsWrite && !candidate.IsWrite) // reads win over writes
{
winner = candidate;
}
else if (!winner.IsRowBufferHit && candidate.IsRowBufferHit) // prev not RB hit
{
winner = candidate;
}
else if (candidate.IsOlderThan(winner))
{
winner = candidate;
}
return(winner);
}
// Override this for other algorithms
override protected SchedBuf Pick(SchedBuf winner, SchedBuf candidate)
{
if (winner == null)
{
winner = candidate;
}
else if (!winner.Urgent && candidate.Urgent)
{
winner = candidate;
}
else if (winner.Urgent && candidate.Urgent && candidate.IsOlderThan(winner))
{
winner = candidate;
}
else if (ch.triggerCPUPrio && winner.mreq.from_GPU && !candidate.mreq.from_GPU) //Priritize CPU if GPU is not bursty
{
winner = candidate;
}
else if (!winner.IsRowBufferHit && candidate.IsRowBufferHit) // prev not RB hit
{
winner = candidate;
}
else if (candidate.IsOlderThan(winner))
{
winner = candidate;
}
return(winner);
}
// Override this for other algorithms
override protected SchedBuf Pick(SchedBuf winner, SchedBuf candidate)
{
if (winner == null)
{
winner = candidate;
}
else if (!winner.Urgent && candidate.Urgent)
{
winner = candidate;
}
else if (winner.Urgent && candidate.Urgent && candidate.IsOlderThan(winner))
{
winner = candidate;
}
else if (!winner.marked && candidate.marked)
{
winner = candidate;
}
else if (!winner.IsRowBufferHit && candidate.IsRowBufferHit) // prev not RB hit
{
winner = candidate;
}
else if (winner.rank > candidate.rank)
{
winner = candidate;
}
else if (candidate.IsOlderThan(winner))
{
winner = candidate;
}
return(winner);
}
override protected SchedBuf Pick(SchedBuf winner, SchedBuf candidate)
{
if(winner == null)
winner = candidate;
MemoryRequest req1 = winner.mreq;
MemoryRequest req2 = candidate.mreq;
bool marked1 = req1.is_marked;
bool marked2 = req2.is_marked;
if (marked1 ^ marked2) {
if (marked1) return winner;
else return candidate;
}
int rank1 = rank[req1.request.requesterID];
int rank2 = rank[req2.request.requesterID];
if (rank1 != rank2) {
if (rank1 > rank2) return winner;
else return candidate;
}
bool hit1 = winner.IsRowBufferHit;
bool hit2 = candidate.IsRowBufferHit;
if (hit1 ^ hit2) {
if (hit1) return winner;
else return candidate;
}
if (candidate.IsOlderThan(winner)) return candidate;
else return winner;
}
// public bool[] schedMask;
// public int[] bank_reserve;
// public int data_bus_reserved_priority;
// public bool[] bank_reserved_rowhit;
public DualSlackSchedule(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
{
mpki = new double[Config.Ng];
prev_cache_miss = new ulong[Config.Ng];
prev_inst_cnt = new ulong[Config.Ng];
top_index_in_buf = new int[Config.Ng];
oldest_when_arrived = new ulong[Config.Ng];
quantum_cycles_left = Config.sched.quantum_cycles;
if( bw_required == null )
bw_required = new int[Config.Ng];
if( bw_allocated == null )
bw_allocated = new int[Config.Ng];
if( bw_consumed == null )
bw_consumed = new int[Config.Ng];
if( rank == null )
rank = new int[Config.Ng];
bw_consumed_per_sched = new int[Config.Ng];
if( shared_req_per_core == 0 )
get_effective_req_sum();
priority = new int[Config.Ng];
// schedMask = new bool[Config.Ng];
// bank_reserve = new int[Config.memory.numBanks];
// bank_reserved_rowhit = new bool[Config.memory.numBanks];
// data_bus_reserved_priority = 0;
}
// Override this for other algorithms
override protected SchedBuf Pick(SchedBuf winner, SchedBuf candidate)
{
getMPKI();
if (winner == null)
{
winner = candidate;
}
else if (mpki[winner.mreq.request.requesterID] < mpki[candidate.mreq.request.requesterID])
{
winner = candidate;
}
else if (mpki[winner.mreq.request.requesterID] == mpki[candidate.mreq.request.requesterID])
{
if (!winner.Urgent && candidate.Urgent)
{
winner = candidate;
}
else if (winner.Urgent && candidate.Urgent && candidate.IsOlderThan(winner))
{
winner = candidate;
}
else if (!winner.IsRowBufferHit && candidate.IsRowBufferHit) // prev not RB hit
{
winner = candidate;
}
else if (candidate.IsOlderThan(winner))
{
winner = candidate;
}
}
return(winner);
}
public bool RequestCanIssue(SchedBuf buf)
{
ulong pageIndex = buf.mreq.shift_row;
// uint burst = buf.burstLength;
if (IsOpen(pageIndex))
{
if (buf.mreq.isWrite)
{
return((nextWrite <= Now) && mem.BusAvailable(cDQS, buf.burstLength));
}
else
{
return((nextRead <= Now) && mem.BusAvailable(cCAS, buf.burstLength));
}
}
else if (IsClosed) // need to issue activation
{
return((nextActivation <= Now) && (rank.nextActivation <= Now));
}
else // conflict
{
return(nextPrecharge <= Now);
}
}
// Override this for other algorithms
override protected SchedBuf Pick(SchedBuf winner, SchedBuf candidate)
{
if(winner == null)
winner = candidate;
else if(!candidate.IsOlderThan(winner))
winner = candidate;
return winner;
}
private long remainingTime(SchedBuf tgt)
{
long time;
time = (long)Simulator.network.nodes[tgt.mreq.request.requesterID].cpu.deadLine +
(long)Simulator.network.nodes[tgt.mreq.request.requesterID].cpu.deadLineCnt -
(long)Simulator.CurrentRound;
return(time);
}
// public bool[] schedMask;
// public int[] bank_reserve;
// public int data_bus_reserved_priority;
// public bool[] bank_reserved_rowhit;
public SchedFRFCFSDeadLine(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
{
hwa_prior = new int[Config.HWANum];
deadline_prior = new int[Config.Ng];
// schedMask = new bool[Config.Ng];
// bank_reserve = new int[Config.memory.numBanks];
// bank_reserved_rowhit = new bool[Config.memory.numBanks];
// data_bus_reserved_priority = 0;
}
public ATLAS(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
{
rank = new int[Config.Ng];
service_bank_cnt = new uint[Config.Ng];
curr_service = new double[Config.Ng];
service = new double[Config.Ng];
this.chan = chan;
quantum_cycles_left = Config.sched.quantum_cycles;
}
private long remainingTime( SchedBuf tgt )
{
long time;
time = (long)Simulator.network.nodes[tgt.mreq.request.requesterID].cpu.deadLine +
(long)Simulator.network.nodes[tgt.mreq.request.requesterID].cpu.deadLineCnt -
(long)Simulator.CurrentRound;
return(time);
}
override protected SchedBuf Pick(SchedBuf winner, SchedBuf candidate)
{
if(winner == null)
winner = candidate;
else
{
int winner_id = winner.mreq.request.requesterID;
int candidate_id = candidate.mreq.request.requesterID;
int winner_priority = getPriority(winner_id);
int candidate_priority = getPriority(candidate_id);
if( winner_priority < candidate_priority )
{
winner = candidate;
}
else if( winner_priority == candidate_priority )
{
if( Simulator.network.nodes[winner.mreq.request.requesterID].cpu.is_HWA() &&
Simulator.network.nodes[candidate.mreq.request.requesterID].cpu.is_HWA() )
{
int winner_rank = Simulator.QoSCtrl.getHwaRank(winner.mreq.request.requesterID);
int candidate_rank = Simulator.QoSCtrl.getHwaRank(candidate.mreq.request.requesterID);
if( winner_rank > candidate_rank )
return winner;
else if( winner_rank < candidate_rank )
return candidate;
}
if(( winner.index == top_index_in_buf[winner_id] ) &&
( candidate.index != top_index_in_buf[candidate_id] ))
return winner;
else if(( winner.index != top_index_in_buf[winner_id] ) &&
( candidate.index == top_index_in_buf[candidate_id] ))
return candidate;
if( winner_id != candidate_id )
{
if( bw_required[winner_id] <= bw_required[candidate_id] ) return winner;
return candidate;
}
if(!winner.Urgent && candidate.Urgent)
winner = candidate;
else if(winner.Urgent && candidate.Urgent && candidate.IsOlderThan(winner))
winner = candidate;
else if(winner.Urgent && !candidate.Urgent)
winner = winner;
else if(!winner.IsRowBufferHit && candidate.IsRowBufferHit) // prev not RB hit
winner = candidate;
else if(winner.IsRowBufferHit && !candidate.IsRowBufferHit )
winner = winner;
else if(candidate.IsOlderThan(winner))
winner = candidate;
}
}
return winner;
}
// Override this for other algorithms
override protected SchedBuf Pick(SchedBuf winner, SchedBuf candidate)
{
if(winner == null)
winner = candidate;
else if(winner.IsRowBufferHit && !candidate.IsRowBufferHit) // prev not RB hit
winner = candidate;
else if(!candidate.IsOlderThan(winner))
winner = candidate;
return winner;
}
// Override this for other algorithms
override protected SchedBuf Pick(SchedBuf winner, SchedBuf candidate)
{
if (winner == null)
{
winner = candidate;
}
else
{
if (Simulator.network.nodes[winner.mreq.request.requesterID].cpu.is_HWA() &&
Simulator.network.nodes[candidate.mreq.request.requesterID].cpu.is_HWA())
{
if (winner.mreq.request.requesterID == candidate.mreq.request.requesterID)
{
if (candidate.IsOlderThan(winner))
{
winner = candidate;
}
}
else if (getPriority(winner.mreq.request.requesterID) < getPriority(candidate.mreq.request.requesterID))
{
winner = candidate;
}
// else if( remainingTime(winner) > remainingTime(candidate) )
// winner = candidate;
}
else if (Simulator.network.nodes[winner.mreq.request.requesterID].cpu.is_HWA())
{
}
else if (Simulator.network.nodes[candidate.mreq.request.requesterID].cpu.is_HWA())
{
winner = candidate;
}
else
{
if (!winner.Urgent && candidate.Urgent)
{
winner = candidate;
}
else if (winner.Urgent && candidate.Urgent && candidate.IsOlderThan(winner))
{
winner = candidate;
}
else if (!winner.IsRowBufferHit && candidate.IsRowBufferHit) // prev not RB hit
{
winner = candidate;
}
else if (candidate.IsOlderThan(winner))
{
winner = candidate;
}
}
}
return(winner);
}
// Override this for other algorithms
override protected SchedBuf Pick(SchedBuf winner, SchedBuf candidate)
{
if (winner == null)
{
winner = candidate;
}
else if (candidate.IsOlderThan(winner))
{
winner = candidate;
}
return(winner);
}
// Override this for other algorithms
override protected SchedBuf Pick(SchedBuf winner, SchedBuf candidate)
{
if (winner == null)
{
winner = candidate;
}
else
{
int winner_priority = getPriority(winner.mreq.request.requesterID);
int candidate_priority = getPriority(candidate.mreq.request.requesterID);
if (winner_priority < candidate_priority)
{
winner = candidate;
}
else if (winner_priority == candidate_priority)
{
if (Simulator.QoSCtrl.is_HWA(winner.mreq.request.requesterID) &&
Simulator.QoSCtrl.is_HWA(candidate.mreq.request.requesterID))
{
// if( Simulator.network.nodes[winner.mreq.request.requesterID].cpu.is_HWA() &&
// Simulator.network.nodes[candidate.mreq.request.requesterID].cpu.is_HWA() ){
if (winner.mreq.request.requesterID == candidate.mreq.request.requesterID)
{
if (candidate.IsOlderThan(winner))
{
winner = candidate;
}
}
}
if (!winner.Urgent && candidate.Urgent)
{
winner = candidate;
}
else if (winner.Urgent && candidate.Urgent && candidate.IsOlderThan(winner))
{
winner = candidate;
}
else if (!winner.IsRowBufferHit && candidate.IsRowBufferHit) // prev not RB hit
{
winner = candidate;
}
else if (candidate.IsOlderThan(winner))
{
winner = candidate;
}
}
}
return(winner);
}
// Override this for other algorithms
override protected SchedBuf Pick(SchedBuf winner, SchedBuf candidate)
{
if(winner == null)
winner = candidate;
else if(!winner.Urgent && candidate.Urgent)
winner = candidate;
else if(winner.Urgent && candidate.Urgent && candidate.IsOlderThan(winner))
winner = candidate;
else if(winner.mreq.from_GPU && !candidate.mreq.from_GPU)
winner = candidate;
else if(!winner.IsRowBufferHit && candidate.IsRowBufferHit) // prev not RB hit
winner = candidate;
else if(candidate.IsOlderThan(winner))
winner = candidate;
return winner;
}
// Override this for other algorithms
override protected SchedBuf Pick(SchedBuf winner, SchedBuf candidate)
{
if(winner == null)
winner = candidate;
else if(!winner.Urgent && candidate.Urgent)
winner = candidate;
else if(winner.Urgent && candidate.Urgent && candidate.IsOlderThan(winner))
winner = candidate;
else if(ch.triggerCPUPrio && winner.mreq.from_GPU && !candidate.mreq.from_GPU) //Priritize CPU if GPU is not bursty
winner = candidate;
else if(!winner.IsRowBufferHit && candidate.IsRowBufferHit) // prev not RB hit
winner = candidate;
else if(candidate.IsOlderThan(winner))
winner = candidate;
return winner;
}
// Override this for other algorithms
virtual protected SchedBuf Pick(SchedBuf winner, SchedBuf candidate)
{
if (winner == null)
{
winner = candidate;
}
else if (!winner.IsRowBufferHit && candidate.IsRowBufferHit) // prev not RB hit
{
winner = candidate;
}
else if (candidate.IsOlderThan(winner))
{
winner = candidate;
}
return(winner);
}
// Override this for other algorithms
override protected SchedBuf Pick(SchedBuf winner, SchedBuf candidate)
{
if (winner == null)
{
winner = candidate;
}
MemoryRequest req1 = winner.mreq;
MemoryRequest req2 = candidate.mreq;
int rank1 = rank[req1.request.requesterID];
int rank2 = rank[req2.request.requesterID];
if (rank1 != rank2)
{
if (rank1 > rank2)
{
return(winner);
}
else
{
return(candidate);
}
}
bool hit1 = winner.IsRowBufferHit;
bool hit2 = candidate.IsRowBufferHit;
if (hit1 ^ hit2)
{
if (hit1)
{
return(winner);
}
else
{
return(candidate);
}
}
if (candidate.IsOlderThan(winner))
{
return(candidate);
}
else
{
return(winner);
}
}
public bool RequestCanIssue(SchedBuf buf)
{
ulong pageIndex = buf.mreq.shift_row;
// uint burst = buf.burstLength;
if(IsOpen(pageIndex))
{
if(buf.mreq.isWrite)
return (nextWrite <= Now) && mem.BusAvailable(cDQS,buf.burstLength);
else
return (nextRead <= Now) && mem.BusAvailable(cCAS,buf.burstLength);
}
else if(IsClosed) // need to issue activation
return (nextActivation <= Now) && (rank.nextActivation <= Now);
else // conflict
return nextPrecharge <= Now;
}
// Override this for other algorithms
override protected SchedBuf Pick(SchedBuf winner, SchedBuf candidate)
{
if(winner == null)
winner = candidate;
else if(!winner.Urgent && candidate.Urgent)
winner = candidate;
else if(winner.Urgent && candidate.Urgent && candidate.IsOlderThan(winner))
winner = candidate;
else if(!winner.marked && candidate.marked)
winner = candidate;
else if(!winner.IsRowBufferHit && candidate.IsRowBufferHit) // prev not RB hit
winner = candidate;
else if(winner.rank > candidate.rank)
winner = candidate;
else if(candidate.IsOlderThan(winner))
winner = candidate;
return winner;
}
// Override this for other algorithms
override protected SchedBuf Pick(SchedBuf winner, SchedBuf candidate)
{
if(winner == null)
winner = candidate;
else if(!winner.Urgent && candidate.Urgent) // urgent wins over non-urgent
winner = candidate;
else if(winner.Urgent && candidate.Urgent && candidate.IsOlderThan(winner))
winner = candidate;
else if(winner.FromGPU && !candidate.FromGPU) // cores win over GPU
winner = candidate;
else if(winner.IsWrite && !candidate.IsWrite) // reads win over writes
winner = candidate;
else if(!winner.IsRowBufferHit && candidate.IsRowBufferHit) // prev not RB hit
winner = candidate;
else if(candidate.IsOlderThan(winner))
winner = candidate;
return winner;
}
public SchedTCMDeadLine(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
{
rank = new int[Config.Ng];
service = new double[Config.Ng];
curr_service = new double[Config.Ng];
service_bank_cnt = new uint[Config.Ng];
mpki = new double[Config.Ng];
prev_cache_miss = new ulong[Config.Ng];
prev_inst_cnt = new ulong[Config.Ng];
rbl = new double[Config.Ng];
shadow_row_hits = new ulong[Config.Ng];
blp = new double[Config.Ng];
blp_sample_sum = new uint[Config.Ng];
quantum_cycles_left = Config.sched.quantum_cycles;
nice = new int[Config.Ng];
shuffle_cycles_left = Config.sched.shuffle_cycles;
this.chan = chan;
Console.WriteLine("TCM Parameter Quantum:{0}, shuffle:{1}", quantum_cycles_left, shuffle_cycles_left );
Console.WriteLine("Exception Check!!");
catchflag = 0;
hwa_prior = new int[Config.HWANum];
deadline_prior = new int[Config.Ng];
mem_intensity_req_cnt = new int[Config.Ng];
mem_nonintensity_req_cnt = new int[Config.Ng];
next_cnt_disable = new bool[Config.Ng];
for( int i = 0; i < Config.Ng; i++ )
{
mem_intensity_req_cnt[i] = 0;
mem_nonintensity_req_cnt[i] = 0;
next_cnt_disable[i] = false;
}
}
// Override this for other algorithms
override protected SchedBuf Pick(SchedBuf winner, SchedBuf candidate)
{
if(winner == null)
winner = candidate;
else if(winner.mreq.request.requesterID > candidate.mreq.request.requesterID)
winner = candidate;
else if(winner.mreq.request.requesterID == candidate.mreq.request.requesterID)
{
if(!winner.Urgent && candidate.Urgent)
winner = candidate;
else if(winner.Urgent && candidate.Urgent && candidate.IsOlderThan(winner))
winner = candidate;
else if(!winner.IsRowBufferHit && candidate.IsRowBufferHit) // prev not RB hit
winner = candidate;
else if(candidate.IsOlderThan(winner))
winner = candidate;
}
return winner;
}
virtual protected bool schedResultMaskChk(SchedBuf tgt)
{
if (Config.sched.hwa_str_priority && Config.sched.hwa_priority_per_bank)
{
if (tgt.IsRowBufferHit)
{
int priority = getPriority(tgt);
if (priority >= data_bus_reserved_priority)
{
return(true);
}
else
{
// Console.WriteLine("Winner(pri:{0} is Masked by pri:{1}", priority, data_bus_reserved_priority );
return(false);
}
}
}
return(true);
}
private double deadlinePriority(SchedBuf tgt)
{
if (!Simulator.QoSCtrl.is_HWA(tgt.mreq.request.requesterID))
// if( !Simulator.network.nodes[tgt.mreq.request.requesterID].cpu.is_HWA() )
{
return(1);
}
if ((Simulator.network.nodes[tgt.mreq.request.requesterID].cpu.deadLineReq == 0) ||
(Simulator.network.nodes[tgt.mreq.request.requesterID].cpu.deadLine == 0))
{
return(1);
}
double progress = (double)Simulator.network.nodes[tgt.mreq.request.requesterID].cpu.deadLineReqCnt /
(double)Simulator.network.nodes[tgt.mreq.request.requesterID].cpu.deadLineReq;
double target_progress = (double)(Simulator.CurrentRound - Simulator.network.nodes[tgt.mreq.request.requesterID].cpu.deadLineCnt) /
(double)Simulator.network.nodes[tgt.mreq.request.requesterID].cpu.deadLine;
/* Console.WriteLine("ID:{0},{1:x}",tgt.mreq.request.requesterID, tgt.mreq.request.address );
* Console.WriteLine("{0},{1},{2},{3}",
* Simulator.network.nodes[tgt.mreq.request.requesterID].cpu.deadLineReqCnt,
* Simulator.network.nodes[tgt.mreq.request.requesterID].cpu.deadLineReq,
* ( Simulator.CurrentRound - Simulator.network.nodes[tgt.mreq.request.requesterID].cpu.deadLineCnt ),
* Simulator.network.nodes[tgt.mreq.request.requesterID].cpu.deadLine ); */
if (progress > target_progress)
{
// Console.WriteLine("HWA:0 progress {0}, target_progress {1}", progress, target_progress );
return(0);
}
else if (target_progress > 0.9)
{
// Console.WriteLine("HWA:2 progress {0}, target_progress {1}", progress, target_progress );
return(2);
}
else
{
// Console.WriteLine("HWA:1 progress {0:f}, target_progress {1:f}", progress, target_progress );
return(1);
}
}
// Override this for other algorithms
override protected SchedBuf Pick(SchedBuf winner, SchedBuf candidate)
{
if(winner == null)
winner = candidate;
MemoryRequest req1 = winner.mreq;
MemoryRequest req2 = candidate.mreq;
double rank1 = blp[req1.request.requesterID];
double rank2 = blp[req2.request.requesterID];
if (rank1 != rank2) {
if (rank1 > rank2) return winner;
else return candidate;
}
bool hit1 = winner.IsRowBufferHit;
bool hit2 = candidate.IsRowBufferHit;
if (hit1 ^ hit2) {
if (hit1) return winner;
else return candidate;
}
if (candidate.IsOlderThan(winner)) return candidate;
else return winner;
}
public SchedTCM(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
{
rank = new int[Config.Ng];
service = new double[Config.Ng];
curr_service = new double[Config.Ng];
service_bank_cnt = new uint[Config.Ng];
mpki = new double[Config.Ng];
prev_cache_miss = new ulong[Config.Ng];
prev_inst_cnt = new ulong[Config.Ng];
rbl = new double[Config.Ng];
shadow_row_hits = new ulong[Config.Ng];
blp = new double[Config.Ng];
blp_sample_sum = new uint[Config.Ng];
quantum_cycles_left = Config.sched.quantum_cycles;
nice = new int[Config.Ng];
shuffle_cycles_left = Config.sched.shuffle_cycles;
this.chan = chan;
}
/* HWA CODE END */
// Override this for other algorithms
virtual public void Tick()
{
mem.Tick();
#if PACKETDUMP
Console.WriteLine("In sched.tick");
#endif
/* HWA CODE Comment Out */
/*
* SchedBuf winner = null;
*/
/* HWA Code Comment Out End */
/* HWA CODE */
winner = null;
schedMaskPrepare();
/* HWA CODE END */
for (int i = 0; i < buf.Length; i++)
{
#if PACKETDUMP
Console.WriteLine("buf_valid = {0}, buf_busy = {1}, buf_morecommand = {2}, buf num = {3}", buf[i].Valid, buf[i].moreCommands, buf[i].Busy);
#endif
// if( buf[i].Valid && buf[i].moreCommands)
// {
// int req_id = buf[i].mreq.request.requesterID;
// int bank_id = buf[i].mreq.bank_index;
// Console.WriteLine("SchedBuf{0}/{6}, pid:{1}, bank_id:{4}, pr:{2}, rowhit:{3}, marked:{5},, address={7:X}", i, req_id, 0, buf[i].IsRowBufferHit, bank_id, buf[i].marked, chan.mem_id, buf[i].mreq.request.address);
// }
if (buf[i].Valid && buf[i].moreCommands && !buf[i].Busy)
{
bool DBAvailable = buf[i].IsWrite ? (chan.writeRequests < chan.maxWrites) : (chan.readRequests < chan.maxReads);
#if PACKETDUMP
Console.WriteLine("in scheduler, DB_avail = {0}, at buffer location {1}, iswrite = {2}", DBAvailable, i, buf[i].IsWrite);
#endif
/* HWA CODE */
// if(DBAvailable && mem.RequestCanIssue(buf[i]))
if (DBAvailable && mem.RequestCanIssue(buf[i]) && schedMaskCheck(buf[i]))
/* HWA CODE END */
{
/* HWA CODE */
SchedBuf winner_bak = winner;
/* HWA CODE END */
winner = Pick(winner, buf[i]);
/* HWA CODE */
if (winner != null)
{
if (winner != buf[i])
{
buf[i].wait_num++;
// if( buf[i].mreq.request.requesterID == 17 )
// Console.WriteLine("WinnerID:{0}", winner.mreq.request.requesterID );
}
else if (winner_bak != null)
{
winner_bak.wait_num++;
}
}
/* HWA CODE END */
}
}
}
// if( winner != null )
// Console.WriteLine("ch:{2}, pid:{0}, bufid:{1}, selected-pre", winner.mreq.request.requesterID, winner.index, chan.mem_id );
if (winner != null)
{
if (!schedResultMaskChk(winner))
{
winner = null; //
}
}
if (winner != null)
{
// Console.WriteLine("ch:{2}, pid:{0}, bufid:{1}, selected", winner.mreq.request.requesterID, winner.index, chan.mem_id );
if (winner.whenStarted == ulong.MaxValue)
{
winner.whenStarted = Simulator.CurrentRound;
}
if (winner.Urgent)
{
Simulator.stats.DRAMUrgentCommandsPerSrc[winner.mreq.request.requesterID].Add();
}
Simulator.stats.DRAMCommandsPerSrc[winner.mreq.request.requesterID].Add();
postMethodForWinner(winner);
mem.IssueCommand(winner);
if (!winner.moreCommands && winner.marked)
{
MarkCompleted(winner);
}
chan.lastBankActivity[winner.mreq.rank_index, winner.mreq.bank_index] = Now;
lastIssue = Now;
/* HWA CODE */
if (!winner.moreCommands)
{
if (Simulator.network.nodes[winner.mreq.request.requesterID].cpu.is_HWA())
{
chan.HWAUnIssueRequests--;
}
chan.unIssueRequestsPerCore[winner.mreq.request.requesterID]--;
if (!winner.mreq.isWrite)
{
chan.unIssueReadRequestsPerCore[winner.mreq.request.requesterID]--;
}
Simulator.QoSCtrl.bw_increment(winner.mreq.request.requesterID, chan.mem_id, chan.id);
Simulator.QoSCtrl.mem_req_issue(winner.mreq.request.requesterID, winner.mreq.request.address, chan.mem_id);
}
/* HWA CODE END */
}
}
virtual public int getPriority(SchedBuf buf)
{
return(0);
}
public bool RequestCanIssue(SchedBuf buf)
{
return(ranks[buf.mreq.rank_index].RequestCanIssue(buf));
}
public SchedInvFRFCFS(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
{
}
public SchedBLP(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
{
}
override public void MarkCompleted(SchedBuf buf)
{
buf.marked = false;
markedRequestsRemaining--;
Debug.Assert(markedRequestsRemaining >= 0);
}
virtual public void MarkCompleted(SchedBuf buf)
{
}
// Override this for other algorithms
override protected SchedBuf Pick(SchedBuf winner, SchedBuf candidate)
{
if(winner == null)
{
winner = candidate;
return winner;
}
if( (!Simulator.QoSCtrl.is_HWA(winner.mreq.request.requesterID) ) &&
(!Simulator.QoSCtrl.is_HWA(candidate.mreq.request.requesterID) ))
// if( (!Simulator.network.nodes[winner.mreq.request.requesterID].cpu.is_HWA()) &&
// (!Simulator.network.nodes[candidate.mreq.request.requesterID].cpu.is_HWA()))
{
MemoryRequest req1 = winner.mreq;
MemoryRequest req2 = candidate.mreq;
int rank1 = rank[req1.request.requesterID];
int rank2 = rank[req2.request.requesterID];
if (rank1 != rank2) {
if (rank1 > rank2) return winner;
else return candidate;
}
}
else if( !Simulator.QoSCtrl.is_HWA(winner.mreq.request.requesterID) )
// else if( !Simulator.network.nodes[winner.mreq.request.requesterID].cpu.is_HWA() )
{
return candidate;
}
else if( !Simulator.QoSCtrl.is_HWA(candidate.mreq.request.requesterID) )
// else if( !Simulator.network.nodes[candidate.mreq.request.requesterID].cpu.is_HWA() )
{
return winner;
}
else
{
if( winner.mreq.request.requesterID == candidate.mreq.request.requesterID )
{
if(candidate.IsOlderThan(winner))
{
return candidate;
}
else
{
return winner;
}
}
else if( getPriority(winner.mreq.request.requesterID) < getPriority(candidate.mreq.request.requesterID))
return candidate;
else
return winner;
}
bool hit1 = winner.IsRowBufferHit;
bool hit2 = candidate.IsRowBufferHit;
if (hit1 ^ hit2) {
if (hit1) return winner;
else return candidate;
}
if (candidate.IsOlderThan(winner)) return candidate;
else return winner;
}
public bool IsOlderThan(SchedBuf other)
{
return(whenArrived < other.whenArrived);
}
public void IssueCommand(SchedBuf buf)
{
ranks[buf.mreq.rank_index].IssueCommand(buf);
}
public bool RequestCanIssue(SchedBuf buf)
{
int bank_index = buf.mreq.bank_index;
return(banks[bank_index].RequestCanIssue(buf));
}
// Override this for other algorithms
override protected SchedBuf Pick(SchedBuf winner, SchedBuf candidate)
{
if (winner == null)
{
winner = candidate;
return(winner);
}
if ((!Simulator.QoSCtrl.is_HWA(winner.mreq.request.requesterID)) &&
(!Simulator.QoSCtrl.is_HWA(candidate.mreq.request.requesterID)))
// if( (!Simulator.network.nodes[winner.mreq.request.requesterID].cpu.is_HWA()) &&
// (!Simulator.network.nodes[candidate.mreq.request.requesterID].cpu.is_HWA()))
{
MemoryRequest req1 = winner.mreq;
MemoryRequest req2 = candidate.mreq;
int rank1 = rank[req1.request.requesterID];
int rank2 = rank[req2.request.requesterID];
if (rank1 != rank2)
{
if (rank1 > rank2)
{
return(winner);
}
else
{
return(candidate);
}
}
}
else if (!Simulator.QoSCtrl.is_HWA(winner.mreq.request.requesterID))
// else if( !Simulator.network.nodes[winner.mreq.request.requesterID].cpu.is_HWA() )
{
return(candidate);
}
else if (!Simulator.QoSCtrl.is_HWA(candidate.mreq.request.requesterID))
// else if( !Simulator.network.nodes[candidate.mreq.request.requesterID].cpu.is_HWA() )
{
return(winner);
}
else
{
if (winner.mreq.request.requesterID == candidate.mreq.request.requesterID)
{
if (candidate.IsOlderThan(winner))
{
return(candidate);
}
else
{
return(winner);
}
}
else if (getPriority(winner.mreq.request.requesterID) < getPriority(candidate.mreq.request.requesterID))
{
return(candidate);
}
else
{
return(winner);
}
}
bool hit1 = winner.IsRowBufferHit;
bool hit2 = candidate.IsRowBufferHit;
if (hit1 ^ hit2)
{
if (hit1)
{
return(winner);
}
else
{
return(candidate);
}
}
if (candidate.IsOlderThan(winner))
{
return(candidate);
}
else
{
return(winner);
}
}
public void IssueCommand(SchedBuf buf)
{
MemoryRequest mreq = buf.mreq;
ulong pageIndex = mreq.shift_row;
if (Simulator.network.nodes[mreq.request.requesterID].m_cpu.m_stats_active)
{
Simulator.stats.dramreqs_persrc[mreq.request.requesterID].Add();
}
if (IsOpen(pageIndex)) // issue read/write
{
buf.whenCompleted = Now + cCAS + buf.burstLength;
buf.whenIdle = Now + cCAS;
if (buf.mreq.isWrite)
{
// if( mem.chan.unIssueRequestsPerCore[17] > 0 )
// if( mreq.request.requesterID == 18 )
// if(( Simulator.CurrentRound > 5041500 ) && ( Simulator.CurrentRound < 5294000 ))
// Console.WriteLine("LOG-WRITE, ch:{2}, id:{0}, bank:{1}", mreq.request.requesterID, mreq.bank_index, chan.mem_id );
nextWrite = Now + buf.burstLength;
nextRead = Max(nextRead, Now + cWTR);
nextPrecharge = Max(nextPrecharge, Now + cWR);
mem.UseBus(cDQS, buf.burstLength);
mem.chan.writeRequests++;
modified = true;
if (Simulator.network.nodes[mreq.request.requesterID].m_cpu.m_stats_active)
{
Simulator.stats.DRAMWriteRowBufferHitsPerSrc[mreq.request.requesterID].Add();
}
}
else
{
// if( mem.chan.unIssueRequestsPerCore[17] > 0 )
// if( mreq.request.requesterID == 18 )
// Console.WriteLine("LOG-READ, cycle:{4}, ch:{2}, id:{0}, bank:{1}, addr:{3:X}", mreq.request.requesterID, mreq.bank_index, chan.mem_id, mreq.request.address, Simulator.CurrentRound );
nextRead = Max(nextRead, Now + buf.burstLength);
nextPrecharge = Max(nextPrecharge, Now + cRTP);
mem.UseBus(cCAS, buf.burstLength);
mem.chan.readRequests++;
Simulator.stats.DRAMReadRowBufferHitsPerSrc[mreq.request.requesterID].Add();
}
buf.moreCommands = false; // no more commands to issue after this
}
else if (IsClosed) // issue activation
{
// ulong whenDone = Now;
// ulong prechargeStart = Now;
// ulong activateStart = Now;
// if( mem.chan.unIssueRequestsPerCore[17] > 0 )
// if( mreq.request.requesterID == 18 )
// if(( Simulator.CurrentRound > 5041500 ) && ( Simulator.CurrentRound < 5294000 ))
// Console.WriteLine("LOG-ACT, ch:{4}, id:{0}, bank:{1}, page:{2:x}, arrived:{3}", mreq.request.requesterID, mreq.bank_index, pageIndex, buf.whenArrived, chan.mem_id );
nextRead = Now + cRCD;
nextWrite = Now + cRCD;
nextPrecharge = Max(nextPrecharge, Now + cRAS);
nextActivation = Max(nextActivation, Now + cRC);
rank.nextActivation = Now + cRRD;
currentPage = pageIndex;
requesterID = mreq.request.requesterID;
buf.whenIdle = Now + cRCD;
if (Simulator.network.nodes[mreq.request.requesterID].m_cpu.m_stats_active)
{
Simulator.stats.DRAMActivationsPerSrc[buf.mreq.request.requesterID].Add();
}
buf.issuedActivation = true;
needsPrecharge = true;
}
else // conflict, issue precharge
{
// if( mem.chan.unIssueRequestsPerCore[17] > 0 )
// if( mreq.request.requesterID == 18 )
// if(( Simulator.CurrentRound > 5041500 ) && ( Simulator.CurrentRound < 5294000 ))
// Console.WriteLine("LOG-PRE, ch:{4}, id:{0}, bank:{1}, page:{2:x}, Arrived:{3}, nextWrite:{5}, nextRead:{6}, nextActivation:{7}, nextPrecharge:{8}", mreq.request.requesterID, mreq.bank_index, pageIndex, buf.whenArrived, chan.mem_id, nextWrite, nextRead, nextActivation, nextPrecharge );
nextActivation = Now + cRP;
nextPrecharge = Now + cRP;
buf.whenIdle = Now + cRP;
needsPrecharge = false;
Simulator.stats.DRAMPrechargesPerSrc[buf.mreq.request.requesterID].Add();
Simulator.stats.DRAMConflictsPerSrc[buf.mreq.request.requesterID].Add();
}
}
private double deadlinePriority( SchedBuf tgt )
{
if( !Simulator.QoSCtrl.is_HWA(tgt.mreq.request.requesterID) )
// if( !Simulator.network.nodes[tgt.mreq.request.requesterID].cpu.is_HWA() )
{
return 1;
}
if(( Simulator.network.nodes[tgt.mreq.request.requesterID].cpu.deadLineReq == 0 ) ||
( Simulator.network.nodes[tgt.mreq.request.requesterID].cpu.deadLine == 0 )){
return 1;
}
double progress = (double)Simulator.network.nodes[tgt.mreq.request.requesterID].cpu.deadLineReqCnt /
(double)Simulator.network.nodes[tgt.mreq.request.requesterID].cpu.deadLineReq;
double target_progress = (double)( Simulator.CurrentRound - Simulator.network.nodes[tgt.mreq.request.requesterID].cpu.deadLineCnt ) /
(double)Simulator.network.nodes[tgt.mreq.request.requesterID].cpu.deadLine;
/* Console.WriteLine("ID:{0},{1:x}",tgt.mreq.request.requesterID, tgt.mreq.request.address );
Console.WriteLine("{0},{1},{2},{3}",
Simulator.network.nodes[tgt.mreq.request.requesterID].cpu.deadLineReqCnt,
Simulator.network.nodes[tgt.mreq.request.requesterID].cpu.deadLineReq,
( Simulator.CurrentRound - Simulator.network.nodes[tgt.mreq.request.requesterID].cpu.deadLineCnt ),
Simulator.network.nodes[tgt.mreq.request.requesterID].cpu.deadLine ); */
if( progress > target_progress )
{
// Console.WriteLine("HWA:0 progress {0}, target_progress {1}", progress, target_progress );
return 0;
}
else if( target_progress > 0.9 )
{
// Console.WriteLine("HWA:2 progress {0}, target_progress {1}", progress, target_progress );
return 2;
}
else
{
// Console.WriteLine("HWA:1 progress {0:f}, target_progress {1:f}", progress, target_progress );
return 1;
}
}
public SchedFRFCFS_PrioCPUWhenNonBursty(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
{
ch = chan;
}
override public int getPriority( SchedBuf tgt )
{
return(getPriority(tgt.mreq.request.requesterID));
}
public SchedInvMPKI(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
{
mpki = new double[Config.Ng];
}
public void IssueCommand(SchedBuf buf)
{
int bank_index = buf.mreq.bank_index;
banks[bank_index].IssueCommand(buf);
}
private int deadlinePriority(SchedBuf tgt)
{
return(deadlinePriority(tgt.mreq.request.requesterID));
}
public void IssueCommand(SchedBuf buf)
{
MemoryRequest mreq = buf.mreq;
ulong pageIndex = mreq.shift_row;
if(Simulator.network.nodes[mreq.request.requesterID].m_cpu.m_stats_active)
Simulator.stats.dramreqs_persrc[mreq.request.requesterID].Add();
if(IsOpen(pageIndex)) // issue read/write
{
buf.whenCompleted = Now + cCAS + buf.burstLength;
buf.whenIdle = Now + cCAS;
if(buf.mreq.isWrite)
{
// if( mem.chan.unIssueRequestsPerCore[17] > 0 )
// if( mreq.request.requesterID == 18 )
// if(( Simulator.CurrentRound > 5041500 ) && ( Simulator.CurrentRound < 5294000 ))
// Console.WriteLine("LOG-WRITE, ch:{2}, id:{0}, bank:{1}", mreq.request.requesterID, mreq.bank_index, chan.mem_id );
nextWrite = Now + buf.burstLength;
nextRead = Max(nextRead,Now + cWTR);
nextPrecharge = Max(nextPrecharge,Now + cWR);
mem.UseBus(cDQS,buf.burstLength);
mem.chan.writeRequests++;
modified = true;
if(Simulator.network.nodes[mreq.request.requesterID].m_cpu.m_stats_active)
Simulator.stats.DRAMWriteRowBufferHitsPerSrc[mreq.request.requesterID].Add();
}
else
{
// if( mem.chan.unIssueRequestsPerCore[17] > 0 )
// if( mreq.request.requesterID == 18 )
// Console.WriteLine("LOG-READ, cycle:{4}, ch:{2}, id:{0}, bank:{1}, addr:{3:X}", mreq.request.requesterID, mreq.bank_index, chan.mem_id, mreq.request.address, Simulator.CurrentRound );
nextRead = Max(nextRead,Now + buf.burstLength);
nextPrecharge = Max(nextPrecharge,Now + cRTP);
mem.UseBus(cCAS,buf.burstLength);
mem.chan.readRequests++;
Simulator.stats.DRAMReadRowBufferHitsPerSrc[mreq.request.requesterID].Add();
}
buf.moreCommands = false; // no more commands to issue after this
}
else if(IsClosed) // issue activation
{
// ulong whenDone = Now;
// ulong prechargeStart = Now;
// ulong activateStart = Now;
// if( mem.chan.unIssueRequestsPerCore[17] > 0 )
// if( mreq.request.requesterID == 18 )
// if(( Simulator.CurrentRound > 5041500 ) && ( Simulator.CurrentRound < 5294000 ))
// Console.WriteLine("LOG-ACT, ch:{4}, id:{0}, bank:{1}, page:{2:x}, arrived:{3}", mreq.request.requesterID, mreq.bank_index, pageIndex, buf.whenArrived, chan.mem_id );
nextRead = Now + cRCD;
nextWrite = Now + cRCD;
nextPrecharge = Max(nextPrecharge,Now + cRAS);
nextActivation = Max(nextActivation,Now + cRC);
rank.nextActivation = Now + cRRD;
currentPage = pageIndex;
requesterID = mreq.request.requesterID;
buf.whenIdle = Now + cRCD;
if(Simulator.network.nodes[mreq.request.requesterID].m_cpu.m_stats_active)
Simulator.stats.DRAMActivationsPerSrc[buf.mreq.request.requesterID].Add();
buf.issuedActivation = true;
needsPrecharge = true;
}
else // conflict, issue precharge
{
// if( mem.chan.unIssueRequestsPerCore[17] > 0 )
// if( mreq.request.requesterID == 18 )
// if(( Simulator.CurrentRound > 5041500 ) && ( Simulator.CurrentRound < 5294000 ))
// Console.WriteLine("LOG-PRE, ch:{4}, id:{0}, bank:{1}, page:{2:x}, Arrived:{3}, nextWrite:{5}, nextRead:{6}, nextActivation:{7}, nextPrecharge:{8}", mreq.request.requesterID, mreq.bank_index, pageIndex, buf.whenArrived, chan.mem_id, nextWrite, nextRead, nextActivation, nextPrecharge );
nextActivation = Now + cRP;
nextPrecharge = Now + cRP;
buf.whenIdle = Now + cRP;
needsPrecharge = false;
Simulator.stats.DRAMPrechargesPerSrc[buf.mreq.request.requesterID].Add();
Simulator.stats.DRAMConflictsPerSrc[buf.mreq.request.requesterID].Add();
}
}
/* HWA Code End */
public Channel(int mem_id, int id)
{
this.mem_id = mem_id;
this.id = id;
this.numRanks = Config.memory.numRanks;
this.numBanks = Config.memory.numBanks;
mem = new DRAM(this);
this.IATCounter = new ulong[Config.Ng];
this.RBHCount = new int[Config.Ng];
this.insnsCount = new ulong[Config.Ng];
this.memServiceCount = new int[Config.Ng];
this.BLP = new double[Config.Ng];
this.BufferUsed = new double[Config.Ng];
this.loadPerProc = new int[Config.Ng];
this.ComboHitsCounts = 0;
for (int i = 0; i < Config.Ng; i++)
{
IATCounter[i] = 0;
}
// Scheduler
buf = new SchedBuf[Config.memory.schedBufSize];
for (int i = 0; i < buf.Length; i++)
{
buf[i] = new SchedBuf(i, mem);
}
switch (Config.memory.DCTARBPolicy)
{
case "INVFCFS":
sched = new SchedInvFCFS(buf, mem, this); break;
case "INVFRFCFS":
sched = new SchedInvFRFCFS(buf, mem, this); break;
case "FCFS":
sched = new SchedFCFS(buf, mem, this); break;
case "FRFCFS":
sched = new SchedFRFCFS(buf, mem, this); break;
case "CoreID":
sched = new SchedCoreID(buf, mem, this); break;
case "GFRFCFS":
sched = new SchedGFRFCFS(buf, mem, this); break;
case "INVMPKI":
sched = new SchedInvMPKI(buf, mem, this); break;
case "MPKI":
sched = new SchedMPKI(buf, mem, this); break;
case "PARBS":
sched = new SchedPARBS(buf, mem, this); break;
case "GPARBS":
sched = new SchedGPARBS(buf, mem, this); break;
case "FRFCFS_PrioCPU":
sched = new SchedFRFCFS_PrioCPU(buf, mem, this); break;
case "FRFCFS_CPUBURST":
sched = new SchedFRFCFS_PrioCPUWhenNonBursty(buf, mem, this); break;
case "BLP":
sched = new SchedBLP(buf, mem, this); break;
case "CTCM":
sched = new SchedCTCM(buf, mem, this); break;
case "INVTCM":
sched = new SchedInvTCM(buf, mem, this); break;
case "TCM":
sched = new SchedTCM(buf, mem, this); break;
case "ATLAS":
sched = new ATLAS(buf, mem, this); break;
/* HWA CODE */
case "FRFCFS_DEADLINE":
sched = new SchedFRFCFSDeadLine(buf, mem, this);
Console.WriteLine("FRFCFS_DeadLine selected");
break;
case "FRFCFS_PRIORHWA":
sched = new SchedFRFCFSwithPriorHWA(buf, mem, this);
Console.WriteLine("FRFCFS_withPriorHWA selected");
break;
case "TCM_PRIORHWA":
sched = new SchedTCMwithPriorHWA(buf, mem, this);
Console.WriteLine("TCM_PriorHWA selected");
break;
case "TCM_CLUSTEROPT":
sched = new SchedTCMClusterOpt(buf, mem, this);
Console.WriteLine("TCM_clusterOpt selected");
break;
case "TCM_CLUSTEROPTPROB4":
sched = new SchedTCMClusterOptProb4(buf, mem, this);
Console.WriteLine("TCM_clusterOptProb4 selected");
break;
case "TCM_DEADLINE":
sched = new SchedTCMDeadLine(buf, mem, this);
Console.WriteLine("TCM_deadline selected");
break;
/* HWA CODE END */
default:
Console.Error.WriteLine("Unknown DCT ARB Policy \"{0}\"", Config.memory.DCTARBPolicy);
Environment.Exit(-1);
break;
}
coreRequests = 0;
GPURequests = 0;
readRequests = 0;
writeRequests = 0;
/* HWA CODE */
HWARequests = 0;
HWAUnIssueRequests = 0;
unIssueRequestsPerCore = new int[Config.Ng];
unIssueReadRequestsPerCore = new int[Config.Ng];
RequestsPerBank = new int[numBanks];
for (int i = 0; i < Config.Ng; i++)
{
unIssueRequestsPerCore[i] = 0;
unIssueReadRequestsPerCore[i] = 0;
}
for (int i = 0; i < numBanks; i++)
{
RequestsPerBank[i] = 0;
}
/* HWA CODE End */
lastBankActivity = new ulong[numRanks, numBanks];
for (int r = 0; r < numRanks; r++)
{
for (int b = 0; b < numBanks; b++)
{
lastBankActivity[r, b] = 0;
}
}
/* HWA Code Comment Out */
/*
* maxCoreRequests = buf.Length - Config.memory.reservedGPUEntries;
* if(maxCoreRequests < 8) maxCoreRequests = 8;
* maxGPURequests = buf.Length - Config.memory.reservedCoreEntries;
* if(maxGPURequests < 8) maxGPURequests = 8;
*/
/* HWA Code Comment Out End */
maxReads = Config.memory.RDBSize;
maxWrites = Config.memory.WDBSize;
/* HWA Code */
maxCoreRequests = buf.Length - Config.memory.reservedGPUEntries - Config.memory.reservedHWAEntries;
if (maxCoreRequests < 8)
{
maxCoreRequests = 8;
}
maxGPURequests = buf.Length - Config.memory.reservedCoreEntries - Config.memory.reservedHWAEntries;
if (maxGPURequests < 8)
{
maxGPURequests = 8;
}
maxHWARequests = buf.Length - Config.memory.reservedCoreEntries - Config.memory.reservedGPUEntries;
if (maxHWARequests < 8)
{
maxHWARequests = 8;
}
Console.WriteLine("maxRequests {0},{1},{2}", maxCoreRequests, maxGPURequests, maxHWARequests);
/* HWA Code End */
}
private int deadlinePriority( SchedBuf tgt )
{
return(deadlinePriority(tgt.mreq.request.requesterID));
}
// Override this for other algorithms
override protected SchedBuf Pick(SchedBuf winner, SchedBuf candidate)
{
if(winner == null)
{
winner = candidate;
return winner;
}
double winner_priority = getPriority( winner );
double candidate_priority = getPriority( candidate );
if( winner_priority < candidate_priority )
{
winner = candidate;
return winner;
}
else if( winner_priority > candidate_priority )
{
return winner;
}
if( (!Simulator.QoSCtrl.is_HWA(winner.mreq.request.requesterID) ) &&
(!Simulator.QoSCtrl.is_HWA(candidate.mreq.request.requesterID) ))
// if( (!Simulator.network.nodes[winner.mreq.request.requesterID].cpu.is_HWA()) &&
// (!Simulator.network.nodes[candidate.mreq.request.requesterID].cpu.is_HWA()))
{
MemoryRequest req1 = winner.mreq;
MemoryRequest req2 = candidate.mreq;
int rank1 = rank[req1.request.requesterID];
int rank2 = rank[req2.request.requesterID];
if (rank1 != rank2) {
if (rank1 > rank2) return winner;
else return candidate;
}
}
else if( !Simulator.QoSCtrl.is_HWA(winner.mreq.request.requesterID) )
// else if( !Simulator.network.nodes[winner.mreq.request.requesterID].cpu.is_HWA() ) // winner is CPU, candidate is HWA
{
MemoryRequest req1 = winner.mreq;
MemoryRequest req2 = candidate.mreq;
int rank1 = rank[req1.request.requesterID];
if( !Simulator.QoSCtrl.schedule_cluster_check(1, req2.request.requesterID, chan.mem_id, chan.id ) )
return winner;
// else if( icluster_size == 0 )
else if( quantum_cnt == 0 )
return winner;
if( rank1 >= icluster_size + Config.HWANum ) // CPU is low memory intensity
{
// if(( Simulator.CurrentRound > 5041500 ) && ( Simulator.CurrentRound < 5294000 ))
// Console.WriteLine("1-2,Id:{0} win against {1}, icluster_size:{2}, rank:{3}", req1.request.requesterID, req2.request.requesterID, icluster_size, rank1 );
return winner;
}
else if( rnd_value < 100 * Config.sched.ratio_allocated_sdl_cluster ) // CPU is high memory intensity, HWA is selected
{
// if(( Simulator.CurrentRound > 5041500 ) && ( Simulator.CurrentRound < 5294000 ))
// Console.WriteLine("1-3,Id:{0} win against {1}, rnd_value:{2}, ratio:{3}", req2.request.requesterID, req1.request.requesterID, rnd_value, Config.sched.ratio_allocated_sdl_cluster );
return candidate;
}
else
{
// if(( Simulator.CurrentRound > 5041500 ) && ( Simulator.CurrentRound < 5294000 ))
// Console.WriteLine("1-2,Id:{0} win against {1}, icluster_size:{2}, rank:{3}", req1.request.requesterID, req2.request.requesterID, icluster_size, rank1 );
return winner;
}
}
else if( !Simulator.QoSCtrl.is_HWA(candidate.mreq.request.requesterID) )
// else if( !Simulator.network.nodes[candidate.mreq.request.requesterID].cpu.is_HWA() ) // winner is HWA, candidate is CPU
{
MemoryRequest req1 = candidate.mreq;
MemoryRequest req2 = winner.mreq;
int rank1 = rank[req1.request.requesterID];
if( !Simulator.QoSCtrl.schedule_cluster_check(1, req2.request.requesterID, chan.mem_id, chan.id ) )
return candidate;
else if( quantum_cnt == 0 )
return candidate;
else if( rank1 >= icluster_size + Config.HWANum ) // CPU is low memory intensity
{
// if(( Simulator.CurrentRound > 5041500 ) && ( Simulator.CurrentRound < 5294000 ))
// Console.WriteLine("1-2,Id:{0} win against {1}, icluster_size:{2}, rank:{3}", req1.request.requesterID, req2.request.requesterID, icluster_size, rank1 );
return candidate;
}
else if( rnd_value < 100 * Config.sched.ratio_allocated_sdl_cluster ) // CPU is high memory intensity, HWA is selected
{
// if(( Simulator.CurrentRound > 5041500 ) && ( Simulator.CurrentRound < 5294000 ))
// Console.WriteLine("1-3,Id:{0} win against {1}, rnd_value:{2}, ratio:{3}", req2.request.requesterID, req1.request.requesterID, rnd_value, Config.sched.ratio_allocated_sdl_cluster );
return winner;
}
else
{
// if(( Simulator.CurrentRound > 5041500 ) && ( Simulator.CurrentRound < 5294000 ))
// Console.WriteLine("1-2,Id:{0} win against {1}, icluster_size:{2}, rank:{3}", req1.request.requesterID, req2.request.requesterID, icluster_size, rank1 );
return candidate;
}
}
else // both are HWA
{
if( winner.mreq.request.requesterID == candidate.mreq.request.requesterID )
{
if(candidate.IsOlderThan(winner))
return candidate;
else
return winner;
}
if( remainingTime(winner.mreq.request.requesterID) > remainingTime(candidate.mreq.request.requesterID) )
{
return candidate;
}
else
{
return winner;
}
}
bool hit1 = winner.IsRowBufferHit;
bool hit2 = candidate.IsRowBufferHit;
if (hit1 ^ hit2) {
if (hit1) return winner;
else return candidate;
}
if (candidate.IsOlderThan(winner)) return candidate;
else return winner;
}
override public int getPriority(SchedBuf tgt)
{
return(getPriority(tgt.mreq.request.requesterID));
}
public SchedTCMClusterOptProb4(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
{
rank = new int[Config.Ng];
service = new double[Config.Ng];
curr_service = new double[Config.Ng];
service_bank_cnt = new uint[Config.Ng];
mpki = new double[Config.Ng];
prev_cache_miss = new ulong[Config.Ng];
prev_inst_cnt = new ulong[Config.Ng];
rbl = new double[Config.Ng];
shadow_row_hits = new ulong[Config.Ng];
blp = new double[Config.Ng];
blp_sample_sum = new uint[Config.Ng];
quantum_cycles_left = Config.sched.quantum_cycles;
nice = new int[Config.Ng];
shuffle_cycles_left = Config.sched.shuffle_cycles;
this.chan = chan;
Console.WriteLine("TCM Parameter Quantum:{0}, shuffle:{1}", quantum_cycles_left, shuffle_cycles_left );
Console.WriteLine("Exception Check!!");
catchflag = 0;
hwa_prior = new int[Config.HWANum];
deadline_prior = new int[Config.Ng];
cRandom = new System.Random();
mem_intensity_req_cnt = new int[Config.Ng];
mem_nonintensity_req_cnt = new int[Config.Ng];
next_cnt_disable = new bool[Config.Ng];
memreq_cnt = new int[Config.Ng];
for( int i = 0; i < Config.Ng; i++ )
memreq_cnt[i] = 0;
for( int i = 0; i < Config.Ng; i++ )
{
mem_intensity_req_cnt[i] = 0;
mem_nonintensity_req_cnt[i] = 0;
next_cnt_disable[i] = false;
}
cluster_factor = Config.sched.AS_cluster_factor;
pre_req_num = new ulong[Config.Ng];
for( int i = 0; i < Config.Ng; i++ )
{
pre_req_num[i] = 0;
}
accelerate_probability_nonint = new int[Config.Ng];
accelerate_probability_int = new int[Config.Ng];
for( int i = 0; i < Config.Ng; i++ )
{
accelerate_probability_nonint[i] = Config.sched.accelerate_probability_nonint;
accelerate_probability_int[i] = Config.sched.accelerate_probability_int;
}
quantum_cycles_for_probability = Config.sched.quantum_cycles_for_probability;
quantum_cycles_left_for_probability = Config.sched.quantum_cycles_for_probability;
quantum_cycles_for_suspend = Config.sched.quantum_cycles_for_suspend;
quantum_cycles_left_for_suspend = 0;
bw_shortage_cnt = 0;
}
// Override this for other algorithms
override protected SchedBuf Pick(SchedBuf winner, SchedBuf candidate)
{
if (winner == null)
{
winner = candidate;
return(winner);
}
double winner_priority = getPriority(winner);
double candidate_priority = getPriority(candidate);
if (winner_priority < candidate_priority)
{
winner = candidate;
return(winner);
}
else if (winner_priority > candidate_priority)
{
return(winner);
}
if ((!Simulator.network.nodes[winner.mreq.request.requesterID].cpu.is_HWA()) &&
(!Simulator.network.nodes[candidate.mreq.request.requesterID].cpu.is_HWA()))
{
MemoryRequest req1 = winner.mreq;
MemoryRequest req2 = candidate.mreq;
int rank1 = rank[req1.request.requesterID];
int rank2 = rank[req2.request.requesterID];
if (rank1 != rank2)
{
if (rank1 > rank2)
{
return(winner);
}
else
{
return(candidate);
}
}
}
else if (!Simulator.network.nodes[winner.mreq.request.requesterID].cpu.is_HWA()) // winner is CPU, candidate is HWA
{
MemoryRequest req1 = winner.mreq;
int rank1 = rank[req1.request.requesterID];
if (rank1 >= icluster_size + Config.HWANum)
{
return(winner);
}
else
{
return(candidate);
}
}
else if (!Simulator.network.nodes[candidate.mreq.request.requesterID].cpu.is_HWA()) // winner is HWA, candidate is CPU
{
MemoryRequest req1 = candidate.mreq;
int rank1 = rank[req1.request.requesterID];
if (rank1 >= icluster_size + Config.HWANum)
{
return(candidate);
}
else
{
return(winner);
}
}
else // both are HWA
{
if (winner.mreq.request.requesterID == candidate.mreq.request.requesterID)
{
if (candidate.IsOlderThan(winner))
{
return(candidate);
}
else
{
return(winner);
}
}
if (remainingTime(winner.mreq.request.requesterID) > remainingTime(candidate.mreq.request.requesterID))
{
return(candidate);
}
else
{
return(winner);
}
}
bool hit1 = winner.IsRowBufferHit;
bool hit2 = candidate.IsRowBufferHit;
if (hit1 ^ hit2)
{
if (hit1)
{
return(winner);
}
else
{
return(candidate);
}
}
if (candidate.IsOlderThan(winner))
{
return(candidate);
}
else
{
return(winner);
}
}
public void IssueCommand(SchedBuf buf)
{
ranks[buf.mreq.rank_index].IssueCommand(buf);
}
