override public void fetch(Request r, ulong address, bool isWrite, bool isReady) {
//Console.WriteLine("proc {0}: fetch addr {1:X}, write {2}, isReady {3}",
// m_cpu.ID, address, isWrite, isReady);
if (load < Config.proc.GPUWindowSize) {
load++;
addresses[next] = address;
writes[next] = isWrite;
ready[next] = isReady;
requests[next] = r;
issueT[next] = Simulator.CurrentRound;
headT[next] = Simulator.CurrentRound;
// index = next;
next++;
// if (!isWrite && !isLoad)
// Console.WriteLine("NonMem GPU addr = {0}", address);
// else
// Console.WriteLine("!!!!Mem GPU addr = {0}", address);
if (!isReady) outstandingReqs++;
if (next == Config.proc.GPUWindowSize) next = 0;
}
else throw new Exception("GPU Instruction Window is full!");
}
public GPUWindow(CPU cpu) : base(cpu) {
m_cpu = cpu;
next = oldest = 0;
addresses = new ulong[Config.proc.GPUWindowSize];
writes = new bool[Config.proc.GPUWindowSize];
requests = new Request[Config.proc.GPUWindowSize];
issueT = new ulong[Config.proc.GPUWindowSize];
headT = new ulong[Config.proc.GPUWindowSize];
ready = new bool[Config.proc.GPUWindowSize];
for (int i = 0; i < Config.proc.GPUWindowSize; i++) {
addresses[i] = NULL_ADDRESS;
writes[i] = false;
ready[i] = true;
requests[i] = null;
}
outstandingReqs = 0;
readLog = writeLog = false;
#if LOG
if (Simulator.sources.soloMode && Simulator.sources.solo.ID == procID)
{
sw = new StreamWriter ("insn.log");
sw.WriteLine("# cycle instrNr req_seq bank netlat injlat");
}
else
sw = null;
#endif
}
public Interference ()
{
_txn = null;
_request = null;
_requesterID = 0;
valid = false;
interference_cycle = 0;
}
public Interference (Packet pkt)
{
_txn = pkt.txn;
_mshr = pkt.txn.mshr;
_request = pkt.request;
_requesterID = pkt.requesterID;
valid = true;
interference_cycle = pkt.intfCycle;
}
public int getChannel(int input, ulong numChan, Request req)
{
int val;
if(mapping.TryGetValue(input,out val))
return val;
else
{
int chan = mappingFunction(input, numChan, req);
mapping.Add(input,chan);
return chan;
}
}
public MemoryRequest(Request req, Simulator.Ready cb)
{
this.cb = cb;
request = req;
req.beenToMemory = true;
mapAddr(req.blockAddress, out m_index, out b_index, out r_index, out glob_b_index);
//scheduling related
//sched = Config.memory.mem[m_index].sched;
sched = null;
isMarked = false;
}
virtual public int mappingFunction(int input, ulong numChan, Request req)
{
//random for now
return rand.Next((int)numChan);
}
public void setRequest(Request req)
{
_request = req;
req.setCarrier(this);
}
public void fetch(Request r, ulong address, bool isWrite, bool isReady) {
//Console.WriteLine("pr{0}: fetch addr {1:X}, write {2}, isReady {3}, next {4}",
// m_cpu.ID, address, isWrite, isReady, next);
if (load < Config.proc.instWindowSize) {
load++;
addresses[next] = address;
writes[next] = isWrite;
ready[next] = isReady;
requests[next] = r;
issueT[next] = Simulator.CurrentRound;
headT[next] = Simulator.CurrentRound;
if (isReady && r != null) r.service();
//Console.WriteLine("pr{0}: new req in slot {1}: addr {2}, write {3} ready {4}", m_cpu.ID, next, address, isWrite, isReady);
next++;
if (!isReady) outstandingReqs++;
//Console.WriteLine("pr{0}: outstanding reqs now at {1}", m_cpu.ID, outstandingReqs);
if (next == Config.proc.instWindowSize) next = 0;
}
else throw new Exception("Instruction Window is full!");
}
bool checkWAR (Request req)
{
for (int i = 0; i < m_mshrs.Length; i++)
if (m_mshrs[i].block == req.blockAddress && m_mshrs[i].valid == true)
{
if (req.write && !m_mshrs [i].write) //by Xiyue: Prevent Write After Read hazard???
return true;
}
return false;
}
/* HWA CODE */
// void issueReq(Request req)
void issueReq(Request req, int windowID)
/* HWA CODE END */
{
// Issue Req from a CPU node
if(!m_is_GPU)
{
//Console.WriteLine("core:{3} issueReq: block {0:X}, write {1} at cyc {2}", req.blockAddress, req.write, Simulator.CurrentRound, m_ID);
for (int i = 0; i < m_mshrs.Length; i++)
if ((m_mshrs[i].block == req.blockAddress) && m_mshrs[i].valid )
{
if (req.write && !m_mshrs[i].write)
m_mshrs[i].pending_write = true;
// if (m_ID == 0) Console.WriteLine("P0 issueReq: found req in MSHR {0}", i);
return;
}
// Console.WriteLine("In issueReq, before resolving MSHR");
int mshr = -1;
for (int i = 0; i < m_mshrs.Length; i++)
if (!m_mshrs[i].valid)
{
mshr = i;
break;
}
Debug.Assert(mshr != -1);
mshrs_free--;
m_mshrs[mshr].valid = true;
m_mshrs[mshr].block = req.blockAddress;
m_mshrs[mshr].write = req.write;
// Use these to determine if any mem req returns while there are other L2 misses out there
m_mshrs[mshr].reqTime = Simulator.CurrentRound;
m_mshrs[mshr].addr = req.address;
// if( m_is_HWA ) Console.WriteLine("ID:{2} Issue Req addr:{0:X}, write:{1}", req.address, req.write,ID);
// Console.WriteLine("In issueReq, after resolving MSHR");
_issueReq(mshr, req.address, req.write, Simulator.CurrentRound, windowID);
}
// Issue Req from a GPU node
else
{
int mem_slice = Simulator.controller.mapMC(req.requesterID, req.address >> Config.cache_block);
m_MemoryCoalescing.issueReq(mem_slice,req, delegate() { reqDone(req.address, -1, req.write);});
}
}
/*
public void receivePacket(MemoryPacket p)
{
Simulator.Ready cb;
//receive WB or request from memory
if(p.type == MemoryRequestType.RD)
{
cb = delegate()
{
MemoryPacket mp = new MemoryPacket(
p.request, p.block,
MemoryRequestType.DAT, p.dest, p.src);
node.queuePacket(mp);
};
}
else
{
// WB don't need a callback
cb = delegate(){};
}
access(p.request, cb);
}
*/
public void access(Request req, Simulator.Ready cb)
{
MemoryRequest mreq = new MemoryRequest(req, cb);
sched.issue_req(mreq);
bank[mreq.b_index].outstandingReqs_perapp[req.requesterID]++;
bank[mreq.b_index].outstandingReqs++;
}
// Called by CPU.cs to issue a request to the MemoryCoalescing
// This just places the request in the appropriate client queue
// This cannot be used when we model the network
public void issueReq(int targetID, Request req, Simulator.Ready cb)
{
// Console.WriteLine("In MemoryCoalescing, issueReq is called requester {0}, addr = {1} at cycle {2}", req.requesterID, req.address, Simulator.CurrentRound);
MemoryRequest mreq = new MemoryRequest(req, cb);
mreq.from_GPU = true;
//Console.WriteLine("Get a GPU Request {0}", req.from_GPU);
int c = (int)req.client;
int w = req.write?1:0;
if(Config.useMemoryCoalescing)
{
// Console.WriteLine("In MemoryCoalescing, enqueue to the client queue requester {0}, addr = {1} at cycle {2}", req.requesterID, req.address, Simulator.CurrentRound);
clientQueue[c,w].Enqueue(new Tuple3(targetID,Simulator.CurrentRound,mreq));
}
else
{
bool l1hit = false, l1upgr = false, l1ev = false, l1wb = false;
bool l2access = false, l2hit = false, l2ev = false, l2wb = false, c2c = false;
Simulator.network.cache.access(req.requesterID, req.address, req.write, cb, out l1hit, out l1upgr, out l1ev, out l1wb, out l2access, out l2hit, out l2ev, out l2wb, out c2c);
}
}
void issueReq(Request req)
{
// if (m_ID == 0) Console.WriteLine("P0 issueReq: block {0:X}, write {1} at cyc {2}", req.blockAddress, req.write, Simulator.CurrentRound);
for (int i = 0; i < m_mshrs.Length; i++)
if (m_mshrs[i].block == req.blockAddress)
{
if (req.write && !m_mshrs[i].write)
m_mshrs[i].pending_write = true;
// if (m_ID == 0) Console.WriteLine("P0 issueReq: found req in MSHR {0}", i);
return;
}
int mshr = -1;
for (int i = 0; i < m_mshrs.Length; i++)
if (!m_mshrs[i].valid)
{
mshr = i;
break;
}
Debug.Assert(mshr != -1);
mshrs_free--;
m_mshrs[mshr].valid = true;
m_mshrs[mshr].block = req.blockAddress;
m_mshrs[mshr].write = req.write;
_issueReq(mshr, req.address, req.write);
}
// construct a multicast packet
// TODO: it may be merged in network.
public Packet(Request request, ulong block, int nrOfFlits, Coord source, List <Coord> _destList)
{
_request = request;
if (_request != null)
_request.beenToNetwork = true;
_block = block; // may not come from request (see above)
_src = source;
destList = new List <Coord>(_destList);
nrMCPacket = _destList.Count;
nrArrivedMCPacket = 0;
nrOfArrivedFlitsMC = new int [Config.N]; // for safety, although mc_degree may not reach N
creationTimeMC = new ulong[Config.N]; // index the destination node ID
if (request != null)
request.setCarrier (this);
requesterID = -1;
hsFlowID = -1;
mc = true;
gather = false;
initialize (Simulator.CurrentRound, nrOfFlits);// Flitization of each packet;
}
public MemoryRequest(Request req, Simulator.Ready cb)
{
this.cb = cb;
request = req;
isWrite = req.write;
req.beenToMemory = true;
// mapAddr(req.blockAddress, out shift_row, out mem_index, out channel_index,
// out rank_index, out bank_index, out row_index);
mapAddr(req.requesterID, req.blockAddress, out shift_row, out mem_index, out channel_index,
out rank_index, out bank_index, out row_index);
// Console.WriteLine("Address:{0:x}, shift_row:{1:x}", req.address, shift_row );
//scheduling related
isMarked = false;
/* HWA CODE */ // Bug Fix??
this.from_GPU = req.from_GPU;
}
// regular packet
public Packet(Request request, ulong block, int nrOfFlits, Coord source, Coord dest)
{
_request = request;
if (_request != null)
_request.beenToNetwork = true;
_block = block; // may not come from request (see above)
_src = source;
_dest = dest;
if (request != null)
request.setCarrier(this);
requesterID = -1;
mc = false;
gather = false;
initialize(Simulator.CurrentRound, nrOfFlits);
}
int allocMSHR(Request req)
{
int mshr = -1;
for (int i = 0; i < m_mshrs.Length; i++)
if (!m_mshrs[i].valid)
{
mshr = i;
break;
}
Debug.Assert(mshr != -1);
mshrs_free--;
m_mshrs[mshr].valid = true;
m_mshrs[mshr].block = req.blockAddress;
m_mshrs[mshr].write = req.write;
return mshr;
}
//by Xiyue:
// TODO: this is the packet generated by the processor
public Packet(Request request, ulong block, int nrOfFlits, Coord source, Coord dest, CmpCache_Txn txn, bool critical)
{
_request = request;
if (_request != null)
_request.beenToNetwork = true;
_block = block; // may not come from request (see above)
_src = source;
_dest = dest;
_intfCycle = 0;
if (request != null)
request.setCarrier(this);
requesterID = -1;
initialize(Simulator.CurrentRound, nrOfFlits);
this.txn = txn;
this.critical = critical;
this.rank = Controller_QoSThrottle.app_rank[txn.node];
this.app_type = Controller_QoSThrottle.app_type[txn.node];
this.most_mem_inten = Controller_QoSThrottle.most_mem_inten[txn.node];
this.slowdown = Simulator.stats.estimated_slowdown [txn.node].LastPeriodValue; // TODO: by Xiyue: this is equivalent to have N ranking levels.
}
void access_mem(int requestor, ulong addr, bool write, Simulator.Ready cb)
{
Request req = new Request(requestor, addr, write);
int node = map_addr_mem(requestor, addr);
Simulator.network.nodes[node].mem.access(req, cb);
}
public void access(Request req, Simulator.Ready cb)
{
MemoryRequest mreq = new MemoryRequest(req, cb);
ReceivePacket(mreq);
}
