public static PStateMsr Decode(uint value, int pstate)
{
//uint maxDiv = (uint)K10Manager.MaxCOF();
uint maxDiv = (uint)K10Manager.CurrCOF();
uint clk = (uint)Form1.clock;
bool turbo = K10Manager.IsTurboSupported();
if (pstate < 8)
{
if (Form1.family == 12) //Llano
{
uint cpuDid = (value >> 0) & 0x0F;
uint cpuFid = (value >> 4) & 0x1F;
uint cpuVid = (value >> 9) & 0x7F;
uint enabled = (value >> 63) & 0x1;
double Did = 1;
switch (cpuDid)
{
case 0:
Did = 1;
break;
case 1:
Did = 1.5;
break;
case 2:
Did = 2;
break;
case 3:
Did = 3;
break;
case 4:
Did = 4;
break;
case 5:
Did = 6;
break;
case 6:
Did = 8;
break;
case 7:
Did = 12;
break;
case 8:
Did = 16;
break;
default:
throw new NotSupportedException("This Divider is not supported");
}
double Mult = (cpuFid + 16) / Did;
var msr = new PStateMsr()
{
CPUMultNBDivider = Mult,
Vid = 1.55 - 0.0125 * cpuVid,
Enabled = enabled,
PLL = Mult * clk
};
return(msr);
}
else if (Form1.family == 14) //Brazos
{
if (pstate <= K10Manager.GetHighestPState())
{
uint cpuDidLSD = (value >> 0) & 0x0F;
uint cpuDidMSD = (value >> 4) & 0x1F;
uint cpuVid = (value >> 9) & 0x7F;
uint enabled = (value >> 63) & 0x1;
double Div = cpuDidMSD + (cpuDidLSD * 0.25) + 1;
double DivPLL = cpuDidMSD + (cpuDidLSD * 0.25) + 1;
if (maxDiv == 16 && Div < 2) //E-350 seems to restrict PLL frequencies higher than 1.6GHz
{
DivPLL = 2;
}
else if (maxDiv == 24 && Div < 4 && !turbo) //C-50 seems to restrict PLL frequencies higher than 1.0GHz
{
DivPLL = 4;
}
else if (maxDiv == 24 && Div < 3 && turbo) //C-60 (with turbo seems to restrict PLL frequencies higher than 1.33GHz
{
DivPLL = 3;
}
var msr = new PStateMsr()
{
CPUMultNBDivider = Div,
Vid = 1.55 - 0.0125 * cpuVid,
Enabled = enabled,
PLL = (16 + maxDiv) / DivPLL * clk
};
return(msr);
}
else
{
var msr = new PStateMsr()
{
CPUMultNBDivider = 10,
Vid = 0.4,
Enabled = 0,
PLL = 0
};
return(msr);
}
}
else //family 16 Kabini
{
if (pstate <= K10Manager.GetHighestPState())
{
uint cpuDid = (value >> 6) & 0x7;
uint cpuFid = value & 0x3F;
uint cpuVid = (value >> 10) & 0x7F; //this works for SVI only - 7bits (CPUVid7:1 are used, CPUVid0 gets ignored)
uint enabled = (value >> 63) & 0x1;
if (cpuDid > 4)
{
throw new NotSupportedException("This Divider is not supported");
}
double CoreCOF = (cpuFid + 16) / (Math.Pow(2, cpuDid));
var msr = new PStateMsr()
{
CPUMultNBDivider = CoreCOF,
Vid = 1.55 - 0.0125 * cpuVid,
Enabled = enabled,
PLL = CoreCOF * clk
};
return(msr);
}
else
{
var msr = new PStateMsr()
{
CPUMultNBDivider = 10,
Vid = 0.4,
Enabled = 0,
PLL = 0
};
return(msr);
}
}
}
else if (pstate == 8)
{
if (Form1.family == 16) //Kabini
{
uint nbvidh = ((value >> 21) & 0x1);
//uint nbvidl = ((value >> 10) & 0x7F); //SVI2 - 8bits
uint nbvidl = ((value >> 11) & 0x3F);
uint nbvid = (nbvidh * 64 + nbvidl);
uint nbdid = ((value >> 7) & 0x1);
uint nbfid = ((value >> 1) & 0x3F);
double nclkdiv = (nbfid + 4) / (Math.Pow(2, nbdid));
var msr = new PStateMsr()
{
CPUMultNBDivider = nclkdiv,
Vid = 1.55 - 0.0125 * nbvid,
Enabled = 1,
PLL = nclkdiv * clk
};
return(msr);
}
else
{
uint nclk = ((value >> 20) & 0x7F);
uint nbVid = ((value >> 12) & 0x7F);
double nclkdiv = 1;
//NCLK Div 2-16 ind 0.25 steps / Div 16-32 in 0.5 steps / Div 32-63 in 1.0 steps
if (nclk >= 8 && nclk <= 63)
{
nclkdiv = nclk * 0.25;
}
else if (nclk >= 64 && nclk <= 95)
{
nclkdiv = (nclk - 64) * 0.5 - 16;
}
else if (nclk >= 96 && nclk <= 127)
{
nclkdiv = nclk - 64;
}
else
{
nclkdiv = 1;
}
var msr = new PStateMsr()
{
CPUMultNBDivider = nclkdiv,
Vid = 1.55 - 0.0125 * nbVid,
Enabled = 1,
PLL = (16 + maxDiv) / nclkdiv * clk
};
return(msr);
}
}
else if (pstate == 9)
{
if (Form1.family == 16) //Kabini
{
uint nbvidh = ((value >> 21) & 0x1);
//uint nbvidl = ((value >> 10) & 0x7F); //SVI2 - 8bits
uint nbvidl = ((value >> 11) & 0x3F);
uint nbvid = (nbvidh * 64 + nbvidl);
uint nbdid = ((value >> 7) & 0x1);
uint nbfid = ((value >> 1) & 0x3F);
double nclkdiv = (nbfid + 4) / (Math.Pow(2, nbdid));
var msr = new PStateMsr()
{
CPUMultNBDivider = nclkdiv,
Vid = 1.55 - 0.0125 * nbvid,
Enabled = 1,
PLL = nclkdiv * clk
};
return(msr);
}
else
{
uint nclk = ((value >> 0) & 0x7F);
uint nbVid = ((value >> 8) & 0x7F);
double nclkdiv = 1;
//NCLK Div 2-16 ind 0.25 steps / Div 16-32 in 0.5 steps / Div 32-63 in 1.0 steps
if (nclk >= 8 && nclk <= 63)
{
nclkdiv = nclk * 0.25;
}
else if (nclk >= 64 && nclk <= 95)
{
nclkdiv = (nclk - 64) * 0.5 - 16;
}
else if (nclk >= 96 && nclk <= 127)
{
nclkdiv = nclk - 64;
}
else
{
nclkdiv = 1;
}
var msr = new PStateMsr()
{
CPUMultNBDivider = nclkdiv,
Vid = 1.55 - 0.0125 * nbVid,
Enabled = 1,
PLL = (16 + maxDiv) / nclkdiv * clk
};
return(msr);
}
}
else
{
var msr = new PStateMsr()
{
CPUMultNBDivider = 0,
Vid = 1,
Enabled = 1,
PLL = 1600
};
return(msr);
}
}
/// <summary>
/// Loads the P-state settings from each core's MSR.
/// </summary>
public void LoadFromHardware()
{
if (_index < 0)
{
throw new InvalidOperationException("The PStateIndex property needs to be initialized first.");
}
if (_index < 8) //hardware loads for CPU
{
//FT if (_index <= K10Manager.GetHighestPState() + K10Manager.GetNumBoostedStates()) //skip, in case index is bigger than initialized CPU PStates
if (_index <= 7)//_maxPstate) //skip, in case just 2 CPU PStates are initialized
{
_pState = PState.Load(_index);
double maxCpuVid = 0;
for (int i = 0; i < _pState.Msrs.Length; i++)//iterating through cores
{
var msr = _pState.Msrs[i];
var control = (NumericUpDown)flowLayoutPanel1.Controls[i];
control.Value = (decimal)msr.CPUMultNBDivider;
maxCpuVid = Math.Max(maxCpuVid, msr.Vid);
}
VidNumericUpDown.Value = Math.Min(VidNumericUpDown.Maximum, (decimal)maxCpuVid);
//int check = K10Manager.SetBIOSBusSpeed(80);
pllfreq.Text = "P" + _index + " Freq (CPU): ";
clockvalue.Text = K10Manager.GetBIOSBusSpeed() + "MHz";
freqvalue.Text = (int)_pState.Msrs[0].PLL + "MHz";
if ((Form1.family == 12) || (Form1.family == 16)) //Llano + Kabini
{
Cofstate.Text = "Mult = ";
}
else //Brazos
{
Cofstate.Text = "Mult = " + (K10Manager.CurrCOF() + 16) + " divided by ->";
}
Form1.freq[_index] = (int)_pState.Msrs[0].PLL;
if (PStateIndex <= _maxPstate)
{
checkBox_Penable.Checked = true;
checkBox_Penable.Enabled = false;
}
else
{
checkBox_Penable.Checked = false;
checkBox_Penable.Enabled = false;
}
}
else
{
VidNumericUpDown.Value = (decimal)0.4;
}
}
else if (_index == 8)
{
//hardware loads for NB P0
_pState = PState.Load(_index);
var control = (NumericUpDown)flowLayoutPanel1.Controls[0];
control.Value = (decimal)K10Manager.GetNbDivPState0();
VidNumericUpDown.Value = (decimal)(1.55 - 0.0125 * K10Manager.GetNbVidPState0());
pllfreq.Text = "NB P0 Freq (GPU): ";
Cofstate.Text = "Mult = " + (K10Manager.CurrCOF() + 16) + " divided by ->";
clockvalue.Text = K10Manager.GetBIOSBusSpeed() + "MHz";
freqvalue.Text = (int)_pState.Msrs[0].PLL + "MHz";
Form1.freq[_index] = (int)_pState.Msrs[0].PLL;
checkBox_Penable.Checked = true;
checkBox_Penable.Enabled = false;
}
else if (_index == 9)
{
//hardware loads for NB P1
_pState = PState.Load(_index);
var control = (NumericUpDown)flowLayoutPanel1.Controls[0];
control.Value = (decimal)K10Manager.GetNbDivPState1();
VidNumericUpDown.Value = (decimal)(1.55 - 0.0125 * K10Manager.GetNbVidPState1());
pllfreq.Text = "NB P1 Freq (GPU): ";
clockvalue.Text = K10Manager.GetBIOSBusSpeed() + "MHz";
freqvalue.Text = (int)_pState.Msrs[0].PLL + "MHz";
Cofstate.Text = "Mult = " + (K10Manager.CurrCOF() + 16) + " divided by ->";
Form1.freq[_index] = (int)_pState.Msrs[0].PLL;
checkBox_Penable.Checked = true;
checkBox_Penable.Enabled = false;
}
else if (_index == 10) //settings for displaying registers
{
VidNumericUpDown.Value = 1;
}
_modified = false;
}