/// <summary>
/// Public class used to enter the workpath
/// </summary>
/// <param name="sktch">Sketch.Sketch object</param>
/// <param name="tv">List of Pin objects containing the inputs and outputs
/// recognized by the truth table recognizer</param>
/// <param name="superWire">List of Superwire objects of the recognized
/// circuit</param>
public bool Go(Sketch.Sketch sktch, List <List <Pin> > tv, CircuitRec.CircuitRec circ)
{
String pn = this.projectPath;
String fn = this.filePath;
//If the project path is null, get the project
if (pn == null)
{
pn = getProj(fn);
if (pn == null)
{
return(false);
}
}
//If the xml filename is null, get the desired filename
if (fn == null)
{
fn = saveFile(xmlFilt, Path.GetDirectoryName(pn));
if (fn == null)
{
return(false);
}
}
//otherwise execute workpath
return(path(pn, fn, sktch, tv, circ));
}
/// <summary>
/// Method returns number inputs/outputs found by the circuit recognizer
/// </summary>
/// <param name="circ">List of superwires from the circuitrec object</param>
/// <returns>Int containing the total number of circuit inputs and outputs</returns>
public int numCol(CircuitRec.CircuitRec circ)
{
//Convert the superwires to a list of input/output pins
PinList pins = new PinList(MeshToPins(circ.Meshes));
//removes the clock variable from the list of inputs/outputs
pins.clk_rm();
//returns the number of remaining inputs/outputs
return(pins.Count);
}
public bool Go(String filename, Sketch.Sketch sktch, List <List <Pin> > tv, CircuitRec.CircuitRec circuit)
{
String projName;
if (projectPath == null)
{
projectPath = getProj(filename);
if (projectPath == null)
{
return(false);
}
}
return(Go(projectPath, filename, sktch, tv, circuit));
}
/// <summary>
/// Runs CircuitRec on a sketch (optionally a the test sketch located at TestSketchFilePath).
/// Retrieves a CircuitRec instance that contains the following data:
/// * Map of substroke Ids to circuit elements (e.g. symbols, wires, and labels)
/// * Endpoints
/// * List of Parse error (if any)
/// * Text recognition results of recognizing labels
///
/// Precondition: args contains a labeled sketch; exceptions will occur (and be caught)
/// in CircuitRec if the labels are illogical or missing. This is never called?
/// </summary>
public override RecognitionResult Recognize(RecognitionArgs args)
{
// Get sketch to recognize
Sketch.Sketch resultSketch;
// DEBUG
if (ReadFromFile)
{
resultSketch = ((new ReadXML(TestSketchFilePath)).Sketch);
}
else
{
resultSketch = args.Sketch;
}
// Init CircuitRec
CircuitRecResult result = new CircuitRecResult();
Domain domain = new Domain(FilenameConstants.DefaultCircuitRecDomainFilepath);
Microsoft.Ink.WordList wordList = TextRecognition.TextRecognition.createLabelWordList();
CircuitRec.CircuitRec crec = new CircuitRec.CircuitRec(domain, wordList);
// Run CircuitRec
try
{
crec.Run(resultSketch);
}
catch (ParseError e)
{
// TEMP deprecated?
result.ParseError = e;
}
catch (ApplicationException e)
{
System.Windows.MessageBox.Show("Error (ApplicationException): CircuitRec could not recognize circuit properties: \n" + e.Message);
}
catch (Exception e)
{
System.Windows.MessageBox.Show("Error (General Exception): \n" + e.Message);
}
// Fill in result
result.UserTriggered = args.UserTriggered;
result.Sketch = resultSketch;
result.CircuitRecInstance = crec;
return(result);
}
static void Main(string[] args)
{
// Keep running the program until finished testing
while (true)
{
#region Input Select
ReadXML xml = null;
String input = " ";
bool fileloaderror = true;
// Choose which file to load (has to be a valid file)
while (fileloaderror)
{
Console.Write("Enter file number or name: ");
input = Console.ReadLine();
Console.WriteLine();
try
{
// use Absolute path because otherwise current directory changes
xml = new ReadXML(@"C:\\Documents and Settings\\Guest\\My Documents\\Sketch\\Code\\Util\\TestCircuitRec\\TestCircuitRec\\TestingData\\" + input + ".xml");
fileloaderror = false;
}
catch (System.IO.FileNotFoundException)
{
fileloaderror = true;
}
}
#endregion
#region Call CircuitRec
// Load domain file
Domain domain = new Domain("digital_domain.txt");
// Load WordList
List <string> stringList = TextRecognition.TextRecognition.loadLabelStringList("../../../../TextRecognition/WordList.txt");
WordList wordList = TextRecognition.TextRecognition.loadLabelWordList(stringList);
// Run CircuitRec
CircuitRec.CircuitRec CR = new CircuitRec.CircuitRec(domain, wordList);
CR.Run(xml.Sketch);
Dictionary <Guid?, object> map = CR.Substroke2CircuitMap;
// Look at errors
Console.WriteLine("Number of errors: " + CR.Errors.Count);
foreach (ParseError e in CR.Errors)
{
Console.WriteLine(e.Message);
}
#endregion
#region Graphical Output
// Gets the data ready for ZedGraph (do not worry about making this cleaner or faster since it is just to test CircuitRec)
// Temporary data variables to output to Graph
double tempx;
double tempy;
// Using ArrayLists to seperate invidual wires and symbols.
ArrayList Wire_Graph = new ArrayList();
ArrayList Wire_Bound = new ArrayList();
ArrayList Wire_Bound2 = new ArrayList();
ArrayList Symbol_Graph = new ArrayList();
ArrayList Symbol_Bound = new ArrayList();
ArrayList Symbol_Bound2 = new ArrayList();
// Temporarily stores the values in a PointPairList
PointPairList temp;
foreach (Wire output in CR.Wires)
{
temp = new PointPairList();
foreach (Point point in output.Points)
{
tempx = Convert.ToDouble(point.X);
tempy = Convert.ToDouble(point.Y);
String tag = output.ID + ": (" + point.X.ToString() + "," + point.Y.ToString() + ")";
temp.Add(tempx, -tempy, tag);
}
// Adds the wire data into the arraylist and then clears the wire PointPairList
Wire_Graph.Add(temp);
}
foreach (BaseSymbol output in CR.Symbols)
{
// Used to keep track of the index for symbol PointPairList
temp = new PointPairList();
// Used to output to form
foreach (Point point in output.Points)
{
tempx = Convert.ToDouble(point.X);
tempy = Convert.ToDouble(point.Y);
temp.Add(tempx, -tempy);
}
Symbol_Graph.Add(temp);
temp = new PointPairList();
}
ArrayList EndPoints = new ArrayList();
ArrayList EndPoints_1 = new ArrayList();
ArrayList EndPoints_2 = new ArrayList();
ArrayList EndPoints_3 = new ArrayList();
temp = new PointPairList();
foreach (Wire new_wire in CR.Wires)
{
for (int index = 0; index < new_wire.EndPt.Length; index++)
{
temp.Add((double)new_wire.EndPt[index].X, -(double)new_wire.EndPt[index].Y);
EndPoints.Add(temp);
temp = new PointPairList();
}
}
// Get Label Points
ArrayList labelpointsAL = new ArrayList();
for (int count = 0; count < CR.LabelShapes.Count; count++)
{
Shape templabels = (Shape)CR.LabelShapes[count];
PointPairList labelpoints = new PointPairList();
foreach (Sketch.Point point in templabels.Points)
{
labelpoints.Add((double)point.X, -(double)point.Y);
}
labelpointsAL.Add(labelpoints);
}
// Get endpoint lines (only adds endpoints)
ArrayList eplinesAL = new ArrayList();
foreach (Wire wire in CR.Wires)
{
foreach (Point ep in wire.EndPt)
{
PointPairList eplines = new PointPairList();
//double x1 = (double)ep.X + 100;
//double x2 = (double)ep.X - 100;
//double y1 = (x1 + 100) * ep.getSlope() + ep.getOffset();
//double y2 = (x2 + 100) * ep.getSlope() + ep.getOffset();
eplines.Add((double)ep.X, -(double)ep.Y);
//eplines.Add(x1, -y1);
//eplines.Add(x2, -y2);
//eplines.Add((double)ep.X + 100, -(((double)ep.X + 100) * ep.getSlope() + ep.getOffset()));
//eplines.Add((double)ep.X - 100, -(((double)ep.X - 100) * ep.getSlope() + ep.getOffset()));
eplinesAL.Add(eplines);
//Console.WriteLine("m={0}, b={1}", ep.getSlope(), ep.getOffset());
}
}
Form1 instance5 = new Form1(Wire_Graph, Symbol_Graph, labelpointsAL, EndPoints, eplinesAL, EndPoints_2, EndPoints_3, CR.Wires, eplinesAL);
Application.Run(instance5);
#endregion
Console.Write("Continue (y or n): ");
if (Console.ReadLine().Equals("n"))
{
break;
}
}
}
/// <summary>
/// Writes VerilogWrite object to a verilog file
/// </summary>
/// <param name="circuit">CircuitRec object to be written to
/// Verilog</param>
/// <param name="filename">String containing the desired verilog filename</param>
public Boolean write(CircuitRec.CircuitRec circuit, String filename)
{
String dir = Path.GetDirectoryName(filename);
String modName = Path.GetFileNameWithoutExtension(filename);
// Calls VerilogWriter to write the .v file
// Module Name
Module M = new Module(modName);
// Inputs to Module
List <Pin> inputs = new List <Pin>();
List <Pin> outputs = new List <Pin>();
List <Pin> wires = new List <Pin>();
Pin temp;
//Loops through each superwire and pulls out the inputs
//and outputs
foreach (Mesh new_wire in circuit.Meshes)
{
if (new_wire.IOType.Equals(WirePolarity.Input))
{
temp = new Pin(PinPolarity.Input, new_wire.Name, new_wire.Bussize);
inputs.Add(temp);
}
else if (new_wire.IOType.Equals(WirePolarity.Output))
{
temp = new Pin(PinPolarity.Ouput, new_wire.Name, new_wire.Bussize);
outputs.Add(temp);
}
else
{
temp = new Pin(PinPolarity.Wire, new_wire.Name, new_wire.Bussize);
wires.Add(temp);
}
}
M.addInputs(inputs);
M.addOutputs(outputs);
M.addWires(wires);
// Outputs of Symbols
String output_name = "";
int symbolSize = 1;
//Loops through each symbol, determines the superwire name
//of the inputs and outputs and add them to the module
foreach (BaseSymbol new_symb in circuit.Symbols)
{
List <Pin> symbInputs = new List <Pin>();
List <Pin> symbOutputs = new List <Pin>();
Pin temporary;
//Look at the wires connected to the symbol
foreach (Wire symb_wire in new_symb.InputWires)
{
//Loop through each superwire attached to the gate to determine
//which the inputwire belongs to. Add it to the gate's input
foreach (Mesh sup in new_symb.ConMeshes)
{
if (sup.AllConnectedWires.Contains(symb_wire))
{
temporary = new Pin(PinPolarity.Input, sup.Name, sup.Bussize);
symbInputs.Add(temporary);
break;
}
}
}
//Look at the output wires of the sympol
foreach (Wire symb_wire in new_symb.OutputWires)
{
//Figure out which superwire each output is attacked to and add it
//to the list of outputs
foreach (Mesh sup in new_symb.ConMeshes)
{
if (sup.AllConnectedWires.Contains(symb_wire))
{
temporary = new Pin(PinPolarity.Ouput, sup.Name, sup.Bussize);
symbOutputs.Add(temporary);
break;
}
}
}
M.addGate(new_symb.Name, new_symb.SymbType, symbOutputs, symbInputs);
}
//Writes the verilog module
return(M.printModule(dir, modName));
}
/// <summary>
/// Writes VerilogWrite object to a verilog file
/// </summary>
/// <param name="circuit">CircuitRec object to be written to
/// Verilog</param>
public Boolean write(CircuitRec.CircuitRec circuit)
{
return(write(circuit, this.filename));
}
/// <summary>
/// Constructor for VerilogWrite class
/// </summary>
public VerilogWrite()
{
this.circuit = null;
this.filename = null;
}
/// <summary>
/// Constructor for VerilogWrite class
/// </summary>
/// <param name="filename">String containing the desired verilog filename</param>
public VerilogWrite(String filename)
{
this.circuit = null;
this.filename = filename;
}
/// <summary>
/// Constructor for VerilogWrite class
/// </summary>
/// <param name="circuit">CircuitRec object to be written to
/// Verilog</param>
/// <param name="filename">String containing the desired verilog filename</param>
public VerilogWrite(CircuitRec.CircuitRec circuit, String filename)
{
this.circuit = circuit;
this.filename = filename;
}
/// <summary>
/// Workpath method
/// </summary>
/// <param name="projFile">String containing full filepath of Xilinx .ise
/// project file</param>
/// <param name="filename">String containing sketch xml filename</param>
/// <param name="sktch">Sketch.Sketch object</param>
/// <param name="superWire">List of Superwire objects of the recognized
/// circuit</param>
/// <param name="tv">List of Pin objects containing the inputs and outputs
/// recognized by the truth table recognizer</param>
private bool path(String projFile, String filename, Sketch.Sketch sktch, List <List <Pin> > tv, CircuitRec.CircuitRec circuit)
{
//In the off chance that either the passed in filename or project file
//is null, simulation can not proceed (possibly unnecessary)
if (projFile == null || filename == null)
{
return(false);
}
//save the sketch as an xml file
//XMLWrite(filename, sktch);
//if rectify returns null, the truth table and circuitrec results could
//not be rectified, so simulation can't proceed
List <Mesh> superWire = new List <Mesh>();
superWire.AddRange(circuit.Meshes);
if (inOutRectify(tv[0], superWire, filename) == null)
{
return(false);
}
tv.RemoveAt(0);
VerilogWrite vw = new VerilogWrite(circuit, filename);
pins2testVectors(tv, filename);
//Execute Xilinx and Modelsim components of workflow
XilinxRun(filename, projFile);
simulate(filename, projFile);
//if it gets to the end of the method, then simulation made it completely
//through the workpath code
return(true);
}
/// <summary>
/// Public class used to enter the workpath
/// </summary>
/// <param name="projname">String containing full filename of Xilinx .ise
/// project file</param>
/// <param name="filename">String containing sketch xml filename</param>
/// <param name="sktch">Sketch.Sketch object</param>
/// <param name="superWire">List of Superwire objects of the recognized
/// circuit</param>
/// <param name="tv">List of Pin objects containing the inputs and outputs
/// recognized by the truth table recognizer</param>
public bool Go(String projname, String filename, Sketch.Sketch sktch, List <List <Pin> > tv, CircuitRec.CircuitRec circuit)
{
return(path(projname, filename, sktch, tv, circuit));
}
/// <summary>
/// Public class used to enter the workpath
/// </summary>
/// <param name="tv">List of Pin objects containing the inputs and outputs
/// recognized by the truth table recognizer</param>
/// <param name="superWire">List of Superwire objects of the recognized
/// circuit</param>
public bool Go(List <List <Pin> > tv, CircuitRec.CircuitRec circuit)
{
return(Go(this.sketch, tv, circuit));
}
