private void ProcessPips(string line)
{
string[] pairs = line.Split(',');
if (pairs.Length != 2)
{
throw new ArgumentException("Error in line " + line);
}
int startIndex = pairs[0].IndexOf('=');
string tileName = pairs[0].Remove(0, startIndex + 1);
Tile t = FPGA.FPGA.Instance.GetTile(tileName);
SwitchMatrix sm = new SwitchMatrix();
string[] switching = pairs[1].Split(' ');
foreach (string entry in switching.Where(s => !string.IsNullOrEmpty(s)))
{
// "LIOI3_SING.IOI_BYP6_0->IOI_IDELAY0_CINVCTRL"
int fromEnd = entry.IndexOf('-');
int toStart = entry.LastIndexOf('>'); // last due to ->>
string from = entry.Substring(0, fromEnd);
bool biDirectional = from.EndsWith("<<");
// handle LH0<<->>LH12
while (from.EndsWith(">") || from.EndsWith("<"))
{
from = from.Remove(from.Length - 1);
}
string to = entry.Substring(toStart + 1);
Port p1 = new Port(from);
Port p2 = new Port(to);
sm.Add(p1, p2);
if (biDirectional && WireHelper.GetIncludeFlag(WireHelper.IncludeFlag.BiDirectionalPips))
{
sm.Add(p2, p1);
}
}
XDLTileParser.StoreAndShareSwitchMatrix(t, sm);
}
protected override void DoCommandAction()
{
if (!HandleUnresolvedWires)
{
FPGA.FPGA.Instance.ClearWireList();
}
m_loopWires = 0;
// create reader & open file
XDLStreamReaderWithUndo sr = new XDLStreamReaderWithUndo(FileName);
XDLTileParser tp = new XDLTileParser();
UnresolvedWires unresWires = null;
if (HandleUnresolvedWires)
{
unresWires = new UnresolvedWires();
}
try
{
Regex tileFilter = new Regex(@"\t+\(tile", RegexOptions.Compiled);
string line = "";
int tileCount = 0;
while ((line = sr.ReadLine()) != null)
{
// only consider tiles
if (tileFilter.IsMatch(line))
{
ProgressInfo.Progress = ProgressStart + ((int)((double)tileCount++ / (double)FPGA.FPGA.Instance.TileCount * ProgressShare));
int yPos;
int xPos;
string location;
XDLTileParser.GetTileHeaderData(line, out yPos, out xPos, out location);
Tile tile = FPGA.FPGA.Instance.GetTile(location);
Watch.Start("ParseWire");
tp.ParseWire(tile, sr, unresWires);
Watch.Stop("ParseWire");
if (HandleUnresolvedWires && tileCount % 10000 == 0)
{
ResolveWires(unresWires);
unresWires.ClearCache();
}
}
}
}
catch (Exception error)
{
throw error;
}
finally
{
sr.Close();
}
if (!HandleUnresolvedWires)
{
// clean up data structures that were used for fast comparing wire list and are now no longer needed
foreach (WireList wl in FPGA.FPGA.Instance.GetAllWireLists())
{
wl.ClearWireKeys();
}
}
else
{
ResolveWires(unresWires);
OutputManager.WriteOutput("Added " + m_loopWires + " loop wires");
}
}
private void ProcessWires(string line, StreamReader sr, ref long currentcharCount, long totalCharCount)
{
string currentTileName = "";
Tile currentTile = null;
WireList wl = new WireList();
string wireLine = line;
WireHelper wireHelper = new WireHelper();
do
{
currentcharCount += wireLine.Length;
if (PrintProgress)
{
ProgressInfo.Progress = (int)(((double)currentcharCount / (double)totalCharCount) * (ExcludePipsToBidirectionalWiresFromBlocking ? 50 : 100));
}
if (m_commentRegexp.IsMatch(wireLine))
{
Console.WriteLine(wireLine);
continue;
}
int equalIndex = wireLine.IndexOf('=');
int sepIndex = wireLine.IndexOf('>', equalIndex);
string left = wireLine.Substring(equalIndex + 1, sepIndex - equalIndex - 2);
int slashIndexLeft = left.IndexOf("/");
string fromTile = left.Substring(0, slashIndexLeft);
string fromPip = left.Substring(slashIndexLeft + 1);//, left.Length - slashIndexLeft-1);
if (string.IsNullOrEmpty(currentTileName))
{
currentTileName = fromTile;
currentTile = FPGA.FPGA.Instance.GetTile(currentTileName);
}
else if (!fromTile.Equals(currentTileName))
{
if (currentTile.WireList != null)
{
throw new ArgumentException("Wirelist should be null");
}
XDLTileParser.StoreAndShareWireList(currentTile, wl);
currentTileName = fromTile;
currentTile = FPGA.FPGA.Instance.GetTile(currentTileName);
wl = new WireList();
}
string right = wireLine.Substring(sepIndex + 1);//, wireLine.Length - sepIndex - 1);
int slashIndexRight = right.IndexOf("/");
string toTile = right.Substring(0, slashIndexRight);
string toPip = right.Substring(slashIndexRight + 1);//, right.Length - slashIndexRight - 1);
Tile tile = FPGA.FPGA.Instance.GetTile(fromTile);
Tile target = FPGA.FPGA.Instance.GetTile(toTile);
uint localPipKey = FPGA.FPGA.Instance.IdentifierListLookup.GetKey(fromPip);
if (WireHelper.GetIncludeFlag(WireHelper.IncludeFlag.WiresTrajectoriesData))
{
tile.AddWireTrajectoryData(localPipKey, FPGA.FPGA.Instance.IdentifierListLookup.GetKey(toTile));
}
if (!currentTile.SwitchMatrix.Contains(fromPip))
{
if (!WireHelper.GetIncludeFlag(WireHelper.IncludeFlag.BELOutWires) ||
!wireHelper.IsBELOutPip(currentTile, fromPip))
{
ReadVivadoFPGADebugger.DebugWire(fromTile, fromPip, toTile, toPip);
continue;
}
}
short xIncr = (short)(target.TileKey.X - currentTile.TileKey.X);
short yIncr = (short)(target.TileKey.Y - currentTile.TileKey.Y);
// Check if we should consider U-turn wires
bool condition = WireHelper.GetIncludeFlag(WireHelper.IncludeFlag.UTurnWires);
condition = condition ? fromTile != toTile || fromPip != toPip : xIncr != 0 || yIncr != 0;
if (!condition)
{
ReadVivadoFPGADebugger.DebugWire(fromTile, fromPip, toTile, toPip);
continue;
}
if (!target.SwitchMatrix.Contains(toPip))
{
if (!WireHelper.GetIncludeFlag(WireHelper.IncludeFlag.BELInWires) ||
!wireHelper.IsBELInPip(target, toPip))
{
ReadVivadoFPGADebugger.DebugWire(fromTile, fromPip, toTile, toPip);
continue;
}
}
uint pipOnOtherTileKey = FPGA.FPGA.Instance.IdentifierListLookup.GetKey(toPip);
Port from = new Port(fromPip);
//Port to = new Port(toPip);
bool fromIsBegin = currentTile.SwitchMatrix.ContainsRight(from);
Wire w = new Wire(localPipKey, pipOnOtherTileKey, fromIsBegin, xIncr, yIncr);
wl.Add(w);
if (WireHelper.GetIncludeFlag(WireHelper.IncludeFlag.IncomingWires))
{
target.AddIncomingWire(w);
}
}while ((wireLine = sr.ReadLine()) != null);
wireHelper.ProcessStopoverArcs();
}
protected override void DoCommandAction()
{
// reset PRIOR to reading to reset high lighter
CommandExecuter.Instance.Execute(new Reset());
FPGA.FPGA.Instance.Reset();
FPGA.FPGA.Instance.BackendType = FPGATypes.BackendType.Vivado;
// create reader & open file
StreamReader sr = new StreamReader(FileName);
FileInfo fi = new FileInfo(FileName);
long charCount = 0;
long lineCount = 0;
string line = "";
while ((line = sr.ReadLine()) != null)
{
lineCount++;
charCount += line.Length;
if (PrintProgress)
{
ProgressInfo.Progress = (int)(((double)charCount / (double)fi.Length) * (ExcludePipsToBidirectionalWiresFromBlocking ? 50 : 100));
}
if (m_commentRegexp.IsMatch(line))
{
continue;
}
int length = line.IndexOf('=');
string prefix = line.Substring(0, length);
switch (prefix)
{
case "Device":
Watch.Start("ProcessDevice");
ProcessDevice(line);
Watch.Stop("ProcessDevice");
break;
case "R":
Watch.Start("ProcessTile");
ProcessTile(line);
Watch.Stop("ProcessTile");
break;
case "Site":
Watch.Start("ProcessSite");
ProcessSite(line);
Watch.Stop("ProcessSite");
break;
case "Pips":
Watch.Start("ProcessPips");
ProcessPips(line);
Watch.Stop("ProcessPips");
break;
case "Wire":
Watch.Start("ProcessWire");
ProcessWires(line, sr, ref charCount, fi.Length);
Watch.Stop("ProcessWire");
break;
default:
{
throw new ArgumentException("Unknown line type: " + line + " (line" + lineCount + ")");
}
}
}
sr.Close();
ReadVivadoFPGADebugger.CloseStream();
WireList emptyWl = new WireList();
foreach (Tile tile in FPGA.FPGA.Instance.GetAllTiles().Where(t => t.WireList == null))
{
XDLTileParser.StoreAndShareWireList(tile, emptyWl);
}
if (ExcludePipsToBidirectionalWiresFromBlocking)
{
ExcludePipsToBidirectionalWiresFromBlocking exclCmd = new ExcludePipsToBidirectionalWiresFromBlocking();
exclCmd.Profile = Profile;
exclCmd.PrintProgress = PrintProgress;
exclCmd.ProgressStart = 50;
exclCmd.ProgressShare = 50;
exclCmd.FileName = "";
CommandExecuter.Instance.Execute(exclCmd);
}
CommandExecuter.Instance.Execute(new Reset());
// no LoadFPGAFamilyScript here! LoadFPGAFamilyScript is called through Reset
// remember for other stuff how we read in this FPGA
Blackboard.Instance.LastLoadCommandForFPGA = ToString();
}
protected override void DoCommandAction()
{
// reset PRIOR to reading to reset high lighter
CommandExecuter.Instance.Execute(new Reset());
// create reader & open file
XDLStreamReaderWithUndo sr = new XDLStreamReaderWithUndo(FileName);
FPGA.FPGA.Instance.Reset();
// XDL is only available with ISE
FPGA.FPGA.Instance.BackendType = FPGA.FPGATypes.BackendType.ISE;
XDLTileParser tp = new XDLTileParser();
try
{
string line = "";
while ((line = sr.ReadLine()) != null)
{
// add space not to match tile_summary or tiles
if (line.Contains("(tile "))
{
tp.ParseTile(line, sr);
if (PrintProgress)
{
ProgressInfo.Progress = (int)((double)FPGA.FPGA.Instance.TileCount / (double)FPGA.FPGA.Instance.NumberOfExpectedTiles * (ReadWireStatements ? 20 : 100));
}
}
//skip commens
else if (line.StartsWith("#"))
{
continue;
}
else if (line.StartsWith("(xdl_resource_report"))
{
XDLResourceReportParser.Parse(line);
}
else if (line.StartsWith("(tiles"))
{
XDLDeviceShapeParser.Parse(line);
}
}
}
finally
{
sr.Close();
}
// read wires in second run
if (ReadWireStatements)
{
ReadWireStatements rw = new ReadWireStatements();
rw.ProgressStart = 20;
rw.ProgressShare = 30;
rw.FileName = FileName;
rw.HandleUnresolvedWires = false;
rw.PrintProgress = PrintProgress;
rw.Profile = Profile;
CommandExecuter.Instance.Execute(rw);
// in third run
rw = new ReadWireStatements();
rw.ProgressStart = 50;
rw.ProgressShare = 30;
rw.FileName = FileName;
rw.HandleUnresolvedWires = true;
rw.PrintProgress = PrintProgress;
rw.Profile = Profile;
CommandExecuter.Instance.Execute(rw);
}
if (ExcludePipsToBidirectionalWiresFromBlocking)
{
ExcludePipsToBidirectionalWiresFromBlocking exclCmd = new ExcludePipsToBidirectionalWiresFromBlocking();
exclCmd.Profile = Profile;
exclCmd.PrintProgress = PrintProgress;
exclCmd.ProgressStart = 80;
exclCmd.ProgressShare = 20;
exclCmd.FileName = "";
CommandExecuter.Instance.Execute(exclCmd);
}
CommandExecuter.Instance.Execute(new Reset());
// no LoadFPGAFamilyScript here! LoadFPGAFamilyScript is called through Reset
// remember for other stuff how we read in this FPGA
Objects.Blackboard.Instance.LastLoadCommandForFPGA = ToString();
}