/// <summary>
/// The FPGA is already read in, this time only read wire statements
/// </summary>
/// <param name="line"></param>
/// <param name="sr"></param>
public void ParseWire(Tile tile, XDLStreamReaderWithUndo sr, UnresolvedWires unresWires)
{
WireList wireList = new WireList();
string line = "";
while ((line = sr.ReadLine()) != null)
{
if (line.Contains("(wire"))
{
wireList = XDLWireParser.Parse(tile, sr, unresWires);
}
else if (line.Contains("tile_summary") && unresWires == null)
{
StoreAndShareWireList(tile, wireList);
//consume closing bracket and exit
line = sr.ReadLine();
return;
}
else if (line.Contains("tile_summary") && unresWires != null)
{
//consume closing bracket and exit
line = sr.ReadLine();
return;
}
}
}
public void ParseTile(string line, XDLStreamReaderWithUndo sr)
{
int yPos;
int xPos;
string location;
GetTileHeaderData(line, out yPos, out xPos, out location);
TileKey key = new TileKey(xPos, yPos);
Tile tile = new Tile(key, location);
SwitchMatrix switchMatrix = new SwitchMatrix();
//add tile to FPGA
FPGA.FPGA.Instance.Add(tile);
//read until end of tile
while ((line = sr.ReadLine()) != null)
{
if (line.Contains("pip"))
{
// \t\t(pip TIOB_X1Y63 TIOB_DIFFO_OUT0 -> TIOB_DIFFO_IN1)
// scan for the first bracket in case \t is replaced by spaces!
int firstBracket = line.IndexOf('(', 0);
int firstBlank = line.IndexOf(' ', firstBracket);
int secondBlank = line.IndexOf(' ', firstBlank + 1);
int thirdBlank = line.IndexOf(' ', secondBlank + 1);
int fourthBlank = line.IndexOf(' ', thirdBlank + 1);
//String tileStr = line.Substring(firstBlank + 1, secondBlank - firstBlank);
string fromStr = line.Substring(secondBlank + 1, thirdBlank - secondBlank - 1);
string pipOperator = line.Substring(thirdBlank + 1, fourthBlank - thirdBlank - 1);
string toStr = line.Substring(fourthBlank + 1, line.Length - fourthBlank - 2);
if (toStr.Contains("(_ROUTE"))
{
toStr = toStr.Replace("(_ROUTE", "# (_ROUTE");
}
Port fromPort = new Port(fromStr);
Port toPort = new Port(toStr);
// there are unidirectional and bidirectional wires
// save string comparison:
// if (pipAtoms[4].Equals("->"))
// else if (pipAtoms[4].Equals("=-"))
switchMatrix.Add(fromPort, toPort);
if (pipOperator.Equals("=-"))
{
switchMatrix.Add(toPort, fromPort);
}
}
else if (line.Contains("conn"))
{
}
else if (line.Contains("wire"))
{
}
else if (line.Contains("primitive_site"))
{
InPortOutPortMapping nextPortMapping = new InPortOutPortMapping();
Slice nextSlice = XDLSliceParser.Parse(tile, nextPortMapping, line, sr);
// share in out port mappings
if (!FPGA.FPGA.Instance.Contains(nextPortMapping))
{
FPGA.FPGA.Instance.Add(nextPortMapping);
}
int hashCode = nextPortMapping.GetHashCode();
nextSlice.InPortOutPortMappingHashCode = hashCode;
}
else if (line.Contains("tile_summary"))
{
StoreAndShareSwitchMatrix(tile, switchMatrix);
//consume closing bracket and exit
line = sr.ReadLine();
return;
}
}
}
//private static Regex m_closingBrackes = new Regex(@"^\s+\)", RegexOptions.Compiled);
//private static Regex m_summary = new Regex("(pip)|(tile_summary)", RegexOptions.Compiled);
public static WireList Parse(Tile containingTile, XDLStreamReaderWithUndo sr, UnresolvedWires unresWires)
{
WireList wires = new WireList();
sr.UndoLastRead();
while (true)
{
// (wire WS5BEG1 3
// (conn INT_BUFS_R_X18Y78 INT_BUFS_WS5B1)
// (conn INT_X18Y78 WS5A1)
// (conn CLBLM_X18Y78 CLB_WS5A1)
// )
string line = sr.ReadLine();
bool conn = line.Contains("(conn");
if (!conn)
{
if (line.Contains("pip") || line.Contains("tile_summary"))
{
sr.UndoLastRead();
break;
}
}
// skip closing brackets
//if (WireParser.m_closingBrackes.IsMatch(nextLine))
if (line.EndsWith(")"))
{
continue;
}
int firstBracketWire = line.IndexOf('(', 0);
int firstBlankWire = line.IndexOf(' ', firstBracketWire);
int secondBlankWire = line.IndexOf(' ', firstBlankWire + 1);
// e.g. (wire WS5BEG1 3
// wireName becomes WS5BEG1
string wireName = line.Substring(firstBlankWire + 1, secondBlankWire - firstBlankWire - 1);
// wireCount becomes 3
string wireCountStr = line.Substring(secondBlankWire + 1, line.Length - secondBlankWire - 1);
int wireCount = int.Parse(wireCountStr);
// wire classification
bool beginPip = false;
bool endPip = false;
beginPip = containingTile.SwitchMatrix.ContainsRight(new Port(wireName));
// HasArcs is expensive, only search if the the pip is a not begin pip
if (!beginPip)
{
endPip = containingTile.SwitchMatrix.ContainsLeft(new Port(wireName));
}
for (int i = 0; i < wireCount; i++)
{
line = sr.ReadLine();
if (beginPip || endPip)
{
Tile targetTile;
Wire w = GetWire(line, containingTile, wireName, beginPip, false, unresWires, out targetTile);
if (w == null)
{
continue;
}
bool destinationExists = Navigator.DestinationAndWireExists(containingTile, w);
if (destinationExists && unresWires == null)
{
// regular wire (bipartite case: wire, pip, wire, pip)
wires.Add(w);
}
else if (!destinationExists && unresWires != null)
{
// store wire for later
unresWires.Add(containingTile, w);
}
}
else if (unresWires != null)
{
Tile targetTile;
Wire w = GetWire(line, containingTile, wireName, beginPip, true, unresWires, out targetTile);
if (w == null)
{
continue;
}
// store wire for later
unresWires.Add(containingTile, w);
}
}
}
return(wires);
}
protected override void DoCommandAction()
{
if (!HandleUnresolvedWires)
{
FPGA.FPGA.Instance.ClearWireList();
}
m_loopWires = 0;
// create reader & open file
XDLStreamReaderWithUndo sr = new XDLStreamReaderWithUndo(FileName);
XDLTileParser tp = new XDLTileParser();
UnresolvedWires unresWires = null;
if (HandleUnresolvedWires)
{
unresWires = new UnresolvedWires();
}
try
{
Regex tileFilter = new Regex(@"\t+\(tile", RegexOptions.Compiled);
string line = "";
int tileCount = 0;
while ((line = sr.ReadLine()) != null)
{
// only consider tiles
if (tileFilter.IsMatch(line))
{
ProgressInfo.Progress = ProgressStart + ((int)((double)tileCount++ / (double)FPGA.FPGA.Instance.TileCount * ProgressShare));
int yPos;
int xPos;
string location;
XDLTileParser.GetTileHeaderData(line, out yPos, out xPos, out location);
Tile tile = FPGA.FPGA.Instance.GetTile(location);
Watch.Start("ParseWire");
tp.ParseWire(tile, sr, unresWires);
Watch.Stop("ParseWire");
if (HandleUnresolvedWires && tileCount % 10000 == 0)
{
ResolveWires(unresWires);
unresWires.ClearCache();
}
}
}
}
catch (Exception error)
{
throw error;
}
finally
{
sr.Close();
}
if (!HandleUnresolvedWires)
{
// clean up data structures that were used for fast comparing wire list and are now no longer needed
foreach (WireList wl in FPGA.FPGA.Instance.GetAllWireLists())
{
wl.ClearWireKeys();
}
}
else
{
ResolveWires(unresWires);
OutputManager.WriteOutput("Added " + m_loopWires + " loop wires");
}
}
protected override void DoCommandAction()
{
// reset PRIOR to reading to reset high lighter
CommandExecuter.Instance.Execute(new Reset());
// create reader & open file
XDLStreamReaderWithUndo sr = new XDLStreamReaderWithUndo(FileName);
FPGA.FPGA.Instance.Reset();
// XDL is only available with ISE
FPGA.FPGA.Instance.BackendType = FPGA.FPGATypes.BackendType.ISE;
XDLTileParser tp = new XDLTileParser();
try
{
string line = "";
while ((line = sr.ReadLine()) != null)
{
// add space not to match tile_summary or tiles
if (line.Contains("(tile "))
{
tp.ParseTile(line, sr);
if (PrintProgress)
{
ProgressInfo.Progress = (int)((double)FPGA.FPGA.Instance.TileCount / (double)FPGA.FPGA.Instance.NumberOfExpectedTiles * (ReadWireStatements ? 20 : 100));
}
}
//skip commens
else if (line.StartsWith("#"))
{
continue;
}
else if (line.StartsWith("(xdl_resource_report"))
{
XDLResourceReportParser.Parse(line);
}
else if (line.StartsWith("(tiles"))
{
XDLDeviceShapeParser.Parse(line);
}
}
}
finally
{
sr.Close();
}
// read wires in second run
if (ReadWireStatements)
{
ReadWireStatements rw = new ReadWireStatements();
rw.ProgressStart = 20;
rw.ProgressShare = 30;
rw.FileName = FileName;
rw.HandleUnresolvedWires = false;
rw.PrintProgress = PrintProgress;
rw.Profile = Profile;
CommandExecuter.Instance.Execute(rw);
// in third run
rw = new ReadWireStatements();
rw.ProgressStart = 50;
rw.ProgressShare = 30;
rw.FileName = FileName;
rw.HandleUnresolvedWires = true;
rw.PrintProgress = PrintProgress;
rw.Profile = Profile;
CommandExecuter.Instance.Execute(rw);
}
if (ExcludePipsToBidirectionalWiresFromBlocking)
{
ExcludePipsToBidirectionalWiresFromBlocking exclCmd = new ExcludePipsToBidirectionalWiresFromBlocking();
exclCmd.Profile = Profile;
exclCmd.PrintProgress = PrintProgress;
exclCmd.ProgressStart = 80;
exclCmd.ProgressShare = 20;
exclCmd.FileName = "";
CommandExecuter.Instance.Execute(exclCmd);
}
CommandExecuter.Instance.Execute(new Reset());
// no LoadFPGAFamilyScript here! LoadFPGAFamilyScript is called through Reset
// remember for other stuff how we read in this FPGA
Objects.Blackboard.Instance.LastLoadCommandForFPGA = ToString();
}
/// <summary>
/// Parse the next slice, add it to containingTile and return the added slice
/// </summary>
/// <param name="containingTile"></param>
/// <param name="mapping"></param>
/// <param name="line"></param>
/// <param name="sr"></param>
/// <returns></returns>
public static Slice Parse(Tile containingTile, InPortOutPortMapping mapping, string line, XDLStreamReaderWithUndo sr)
{
// (primitive_site SLICE_X0Y79 SLICEM public 50
char[] pipSeparator = { ' ', '(', ')' };
string[] primitiveSiteAtoms = line.Split(pipSeparator);
//five elements expected, see above
if (primitiveSiteAtoms.Length != 6)
{
throw new ArgumentException("Unexpected primitive_site found: " + line);
}
// get S6, V5, ... slice
Slice slice = Slice.GetSlice(containingTile, primitiveSiteAtoms[2], primitiveSiteAtoms[3]);
containingTile.Slices.Add(slice);
if (FPGA.FPGA.Instance.Family.Equals(FPGATypes.FPGAFamily.Virtex4))
{
// Slice in Virtex4 come in order 0 2 1 3 -> reorder to 0 1 2 3
if (containingTile.Slices.Count == 4 && IdentifierManager.Instance.IsMatch(containingTile.Location, IdentifierManager.RegexTypes.CLB))
{
Slice temp = containingTile.Slices[2];
containingTile.Slices[2] = containingTile.Slices[1];
containingTile.Slices[1] = temp;
}
}
//read until end of tile
while ((line = sr.ReadLine()) != null)
{
if (line.Contains("pinwire"))
{
string[] atoms = line.Split(' ', ')');
if (atoms.Length != 5)
{
throw new ArgumentException("Unexpected pinwire line: " + line);
}
Port p = new Port(atoms[3]);
if (mapping.Contains(p))
{
Console.WriteLine("Warning: Port " + p.Name + " already exists in " + containingTile.Location + ". This port will be skipped." + p.GetHashCode());
}
if (atoms[2].Equals("input"))
{
mapping.AddSlicePort(p, FPGATypes.PortDirection.In);
}
else if (atoms[2].Equals("output"))
{
mapping.AddSlicePort(p, FPGATypes.PortDirection.Out);
}
else if (atoms[2].Equals("bidir"))
{
mapping.AddSlicePort(p, FPGATypes.PortDirection.In);
mapping.AddSlicePort(p, FPGATypes.PortDirection.Out);
}
else
{
throw new ArgumentException("Unexpected slice port " + line);
}
}
//reached end of tile
else if (m_endOfFile.IsMatch(line))
{
return(slice);
}
else
{
continue;
}
}
// should never be reached
throw new ArgumentException("Could not parse slice starting with " + line);
}