static ETMPcktFiveByteRunBase()
{
// In subsequent packets, 7 bits are used and the top
// bit indicates whether or not another byte follows.
iExtractionMaskSubsequentOriginalScheme = new SymMask("01111111");
iExtractionMaskSubsequentAlternativeScheme = new SymMask("00111111");
}
protected override void DecodePartial()
{
int count = base.Count;
System.Diagnostics.Debug.Assert(count > 0 && count < 5);
// According to Table 7-13, "Missing components of exception Branch address packets"
// then after a partial branch, we're always in "no exception" state
base.ExceptionType = TArmExceptionType.ENone;
if (count == 1)
{
// The single-byte packet is exactly the same as in the original encoding
base.DecodePartial();
}
else
{
// We have full 5 bytes of address info.
SymMask maskFirst = new SymMask(0x7E, SymMask.TShiftDirection.ERight, 1);
SymMask maskMiddle = new SymMask(0x7F);
SymMask maskLast = new SymMask(0x3F);
SymByte b;
SymAddressWithKnownBits address = new SymAddressWithKnownBits();
uint masked = 0;
// First byte
b = base[0];
address.KnownBits += 6;
address.Address |= maskFirst.Apply(b);
// Middle bytes, but not the last
for (int i = 1; i < count - 1; i++)
{
b = base[i];
b = (byte)maskMiddle.Apply(b);
masked = (uint)(b << address.KnownBits);
address.KnownBits += 7;
address.Address |= masked;
}
// Last byte
b = base.LastByte;
address.KnownBits += 6;
address.Address |= maskLast.Apply(b);
// Shift entire address by shift count based upon current instruction set.
int isShift = ETMBranchDecoder.CompressionLeftShiftCount(base.InstructionSet);
address.KnownBits += isShift;
address.Address <<= isShift;
// Save address
base.BranchAddress = address;
}
}
static ETMDecodeStatePHeader()
{
// ARM branch instructions
iBranchMask_ARM_BOrBL = new SymMask("#### 101 # ######## ######## ########");
iBranchMask_ARM_BLX_BranchToThumb = new SymMask("1111 101 # ######## ######## ########");
// THUMB branch instructions
iBranchMask_THUMB_B1 = new SymMask("1101 #### ########");
iBranchMask_THUMB_B2 = new SymMask("11100 ###########");
iBranchMask_THUMB_BLX_Part1 = new SymMask("11110 ###########"); // Multi-instruction branch
iBranchMask_THUMB_BLX_Part2 = new SymMask("111#1 ###########"); // Multi-instruction branch
}
public override bool Matches(SymByte aOpCode)
{
bool ret = base.Matches(aOpCode);
if (ret)
{
// Tag has to be > 0
SymMask mask = new SymMask("1100000", SymMask.TShiftDirection.ERight, 5);
uint tag = mask.Apply(aOpCode);
ret = (tag > 0 && tag < 4);
}
//
return(ret);
}
protected override void DecodePartial()
{
// According to Table 7-13, "Missing components of exception Branch address packets"
// then after a partial branch, we're always in "no exception" state
base.ExceptionType = TArmExceptionType.ENone;
// We have full 5 bytes of address info.
SymMask maskFirst = new SymMask(0x7E, SymMask.TShiftDirection.ERight, 1);
SymMask maskMiddle = new SymMask(0x7F);
SymByte b;
SymAddressWithKnownBits address = new SymAddressWithKnownBits();
uint masked = 0;
int count = base.Count;
// First byte
b = base[0];
address.KnownBits += 6;
address.Address |= maskFirst.Apply(b);
// Bytes 1, 2, 3
for (int i = 1; i < count; i++)
{
b = base[i];
b = (byte)maskMiddle.Apply(b);
masked = (uint)(b << address.KnownBits);
address.KnownBits += 7;
address.Address |= masked;
}
// Shift entire address by shift count based upon current instruction set.
int isShift = ETMBranchDecoder.CompressionLeftShiftCount(base.InstructionSet);
address.KnownBits += isShift;
address.Address <<= isShift;
// Save address
base.BranchAddress = address;
}
protected override void DecodeFull()
{
// We have full 5 bytes of address info.
SymMask maskFirst = new SymMask(0x7E, SymMask.TShiftDirection.ERight, 1);
SymMask maskMiddle = new SymMask(0x7F);
SymByte b;
SymAddressWithKnownBits address = new SymAddressWithKnownBits();
uint masked = 0;
// First byte
b = base[0];
address.KnownBits += 6;
address.Address |= maskFirst.Apply(b);
// Bytes 1, 2, 3
for (int i = 1; i <= 3; i++)
{
b = base[i];
b = (byte)maskMiddle.Apply(b);
masked = (uint)(b << address.KnownBits);
address.KnownBits += 7;
address.Address |= masked;
}
// Last byte - mask depends on instruction set.
b = base[4];
int lastByteAddressBits = 0;
if (this.ContainsInlineException || iMaskByte5_ARM.IsMatch(b))
{
// Inline exception indicates ARM.
base.InstructionSet = TArmInstructionSet.EARM;
lastByteAddressBits = 3;
}
else if (iMaskByte5_THUMB.IsMatch(b))
{
base.InstructionSet = TArmInstructionSet.ETHUMB;
lastByteAddressBits = 4;
}
else if (iMaskByte5_JAZELLE.IsMatch(b))
{
base.InstructionSet = TArmInstructionSet.EJAZELLE;
lastByteAddressBits = 5;
}
else
{
throw new ETMException("ERROR: branch type unknown");
}
// Now we can process the last byte
masked = b.LowestBits(lastByteAddressBits);
masked <<= address.KnownBits;
address.KnownBits += lastByteAddressBits;
address.Address |= masked;
// Shift entire address by shift count based upon current instruction set.
int isShift = ETMBranchDecoder.CompressionLeftShiftCount(base.InstructionSet);
System.Diagnostics.Debug.Assert(address.KnownBits + isShift == 32);
address.KnownBits = 32;
address.Address <<= isShift;
// Save address
base.BranchAddress = address;
// We may also need to decode the inline exception
if (ContainsInlineException)
{
// Yup, line exception...
DecodeInlineException(base.LastByte);
}
}
static ETMBranchDecoderOriginal()
{
iMaskByte5_ARM = new SymMask(KMaskByte5_ARM);
iMaskByte5_THUMB = new SymMask(KMaskByte5_THUMB);
iMaskByte5_JAZELLE = new SymMask(KMaskByte5_JAZELLE);
}
private void DecodeInlineException(SymByte aByte)
{
// b1CEEExxx Exception executed in ARM state.
//
// The C bit is set to 1 if the exception cancels the last traced instruction.
// The EEE bits, bits [5:3], indicate the type of exception as shown in Table 7-9.
// Use of this format is deprecated in favor of using an Exception information byte.
// Inline exception packets always indicate ARM mode
base.InstructionSet = TArmInstructionSet.EARM;
// Was it a cancelling branch?
base.IsLastInstructionCancelled = aByte[6];
// Set back to no exception unless changed explicitly below.
base.ExceptionType = TArmExceptionType.ENone;
// Get exception type
SymMask mask = new SymMask("## 111 ###", SymMask.TShiftDirection.ERight, 3);
SymByte exceptionInfo = (byte)mask.Apply(aByte);
if (exceptionInfo == 0)
{
// Have to work this out from the branch address
TArmExceptionVector vector = base.Config.MapToExceptionVector(base.BranchAddress.Address);
switch (vector)
{
case TArmExceptionVector.EReset:
base.ExceptionType = TArmExceptionType.EProcessorReset;
break;
case TArmExceptionVector.EUndefinedInstruction:
base.ExceptionType = TArmExceptionType.EUndefinedInstruction;
break;
case TArmExceptionVector.ESVC:
base.ExceptionType = TArmExceptionType.ESVC;
break;
case TArmExceptionVector.EPrefetchAbort:
base.ExceptionType = TArmExceptionType.EPrefetchAbortOrSWBreakpoint;
break;
case TArmExceptionVector.EDataAbort:
base.ExceptionType = TArmExceptionType.ESyncDataAbortOrSWWatchpoint;
break;
default:
throw new ETMException("ERROR - unable to extract exception type from branch address: 0x" + base.BranchAddress);
}
}
else
{
switch (exceptionInfo)
{
case 1:
base.ExceptionType = TArmExceptionType.EIRQ;
break;
default:
case 2:
case 3:
throw new NotSupportedException("Reserved exception type");
case 4:
base.ExceptionType = TArmExceptionType.EJazelle;
break;
case 5:
base.ExceptionType = TArmExceptionType.EFIQ;
break;
case 6:
base.ExceptionType = TArmExceptionType.EAsyncDataAbort;
break;
case 7:
base.ExceptionType = TArmExceptionType.EHaltingDebug;
break;
}
}
}
static ETMPcktPHeaderFormat2()
{
iAtomMask1 = new SymMask("1###", SymMask.TShiftDirection.ERight, 3);
iAtomMask2 = new SymMask("#1##", SymMask.TShiftDirection.ERight, 2);
}