private void ImplementFlow(Flow flow, IAlgorithmBuilder pbuilder, SLVSignal cwSignal, HashSet <ISignalOrPortDescriptor> sensitivity)
{
if (FlowMatrix.IsDontCareFlow(flow))
{
int valOffset = _vfc.GetValueWordOffset(flow.Target);
int valWidth = _vfc.GetValueWordWidth(flow.Target);
LiteralReference lrCWValSlice;
if (flow.Target.Desc.ElementType.CILType.Equals(typeof(StdLogic)))
{
lrCWValSlice = new LiteralReference(
((ISignal)cwSignal[valOffset])
.ToSignalRef(SignalRef.EReferencedProperty.Cur));
}
else
{
lrCWValSlice = new LiteralReference(
((ISignal)cwSignal[valOffset + valWidth - 1, valOffset])
.ToSignalRef(SignalRef.EReferencedProperty.Cur));
}
pbuilder.Store(flow.Target, lrCWValSlice);
}
else if (flow is SignalFlow)
{
var sflow = flow as SignalFlow;
pbuilder.Store(flow.Target, sflow.Source);
sensitivity.Add(sflow.Source.Desc);
}
else
{
var vflow = flow as ValueFlow;
pbuilder.Store(vflow.Target,
LiteralReference.CreateConstant(vflow.Value));
}
}
public override void AssembleStagedDecoderComb(ValueFlowCoder vfc, LiteralReference lrCWSelSlice,
IAlgorithmBuilder pbuilder, SLVSignal cwSignal, HashSet <ISignalOrPortDescriptor> sensitivity,
bool registered)
{
_encFlow0.AssembleStagedDecoderComb(vfc, lrCWSelSlice, pbuilder, cwSignal, sensitivity, registered);
_encFlow1.AssembleStagedDecoderComb(vfc, lrCWSelSlice, pbuilder, cwSignal, sensitivity, registered);
}
public FPUWrapper(EISEVersion iseVer)
{
var a = new SLVSignal(32);
var b = new SLVSignal(32);
var r = new SLVSignal(32);
var clk = new SLSignal();
_fpu = new FloatingPointCore()
{
A = a,
B = b,
Clk = clk,
Result = r,
DSP48EUsage = FloatingPointCore.EDSP48EUsage.FullUsage,
Function = FloatingPointCore.EFunction.AddSubtract,
TargetDeviceFamily = SystemSharp.Interop.Xilinx.EDeviceFamily.Virtex6,
UseMaximumLatency = true,
Precision = FloatingPointCore.EPrecision.Single,
ResultPrecision = FloatingPointCore.EPrecision.Single,
AddSubSel = FloatingPointCore.EAddSub.Add,
TargetISEVersion = iseVer
};
Clk = clk;
A = a;
B = b;
R = r;
}
/// <summary>
/// Constructs a new instance
/// </summary>
/// <param name="xIntWidth">integer width of operand</param>
/// <param name="xFracWidth">fractional width of operand</param>
/// <param name="yIntWidth">integer width of result</param>
/// <param name="yFracWidth">fractional width of result</param>
/// <param name="pipeStages">desired computation-only latency</param>
public LERPUnit(int xIntWidth, int xFracWidth, int yIntWidth, int yFracWidth, int pipeStages)
{
Contract.Requires <ArgumentOutOfRangeException>(xIntWidth > 0, "xIntWidth must be positive.");
Contract.Requires <ArgumentOutOfRangeException>(xFracWidth >= 0, "xFracWidth must be non-negative.");
Contract.Requires <ArgumentOutOfRangeException>(yIntWidth + yFracWidth > 0, "total bit-width of result must be positive");
Contract.Requires <ArgumentOutOfRangeException>(pipeStages >= 0, "pipeStages must be non-negative.");
Contract.Requires <ArgumentOutOfRangeException>(xFracWidth > 0 || pipeStages == 0, "xFracWidth == 0 is a degenerate case (lookup-only). No additional pipeline stages allowed.");
PipeStages = pipeStages;
XIntWidth = xIntWidth;
XFracWidth = xFracWidth;
YIntWidth = yIntWidth;
YFracWidth = yFracWidth;
AddrWidth = xIntWidth;
_yIn = new SLVSignal(yIntWidth + yFracWidth);
_yOut = new SLVSignal(yIntWidth + yFracWidth);
_yPipe = new RegPipe(pipeStages, yIntWidth + yFracWidth);
Bind(() =>
{
_yPipe.Clk = Clk;
_yPipe.Din = _yIn;
_yPipe.Dout = _yOut;
});
}
/// <summary>
/// Constructs a testbench instance. All other instances are created
/// and bound here.
/// </summary>
public SimpleCounterTestbench()
{
// Create a clock generator and bind its output to the clock signal.
_m_clk = new Clock(ClockPeriod)
{
Clk = _clk
};
for (int i = 0; i < NumCounters; i++)
{
//The internal signal for storing the counter value
var _ctr = new SLVSignal(CounterSize);
// Create a counter and bind it the the clock and the counter value signal.
var _m_ctr = new Counter(CounterSize)
{
Clk = _clk,
Ctr = _ctr
};
// Create a logger which will display the counter value at the console output.
var _m_logger = new ConsoleLogger <StdLogicVector>()
{
DataIn = _ctr
};
}
}
public override void Establish(IAutoBinder binder)
{
if (_realized)
{
return;
}
_addrBits = MathExt.CeilLog2(_array.ArrayObj.Length);
_dataBits = Marshal.SerializeForHW(_array.ElementType.GetSampleInstance()).Size;
_clkI = (SLSignal)binder.GetSignal(EPortUsage.Clock, "Clk", null, null);
_dataOutI = (SLVSignal)binder.GetSignal(EPortUsage.Default, "memIf_dataOut", null, StdLogicVector._0s(_dataBits));
_addrI = (SLVSignal)binder.GetSignal(EPortUsage.Default, "memIf_addr", null, StdLogicVector._0s(_addrBits));
_clk = _clkI.Descriptor;
_addr = _addrI.Descriptor;
_dataOut = _dataOutI.Descriptor;
if (NeedWriteAccess)
{
_wrEnI = (SLSignal)binder.GetSignal(EPortUsage.Default, "memIf_wrEn", null, StdLogic._0);
_dataInI = (SLVSignal)binder.GetSignal(EPortUsage.Default, "memIf_dataIn", null, StdLogicVector._0s(_dataBits));
_wrEn = _wrEnI.Descriptor;
_dataIn = _dataInI.Descriptor;
}
var memIfBuilder = new MemIfBuilder(this);
var memIfAlg = memIfBuilder.GetAlgorithm();
memIfAlg.Name = "MemIf";
binder.CreateProcess(Process.EProcessKind.Triggered, memIfAlg, _clk);
_realized = true;
}
/// <summary>
/// Constructs a new testbechn.
/// </summary>
/// <param name="userLogic">component under test</param>
public AXILiteSlaveUserLogicTestbench(AXILiteSlaveUserLogic userLogic)
{
user_logic = userLogic;
_sig_Bus2IP_Clk = new SLSignal();
_sig_Bus2IP_Resetn = new SLSignal() { InitialValue = '0' };
_sig_Bus2IP_Data = new SLVSignal(userLogic.SLVDWidth) { InitialValue = StdLogicVector.Xs(userLogic.SLVDWidth) };
_sig_Bus2IP_BE = new SLVSignal(userLogic.SLVDWidth / 8) { InitialValue = StdLogicVector._0s(userLogic.SLVDWidth / 8) };
_sig_Bus2IP_RdCE = new SLVSignal(userLogic.NumRegs) { InitialValue = StdLogicVector._0s(userLogic.NumRegs) };
_sig_Bus2IP_WrCE = new SLVSignal(userLogic.NumRegs) { InitialValue = StdLogicVector._0s(userLogic.NumRegs) };
_sig_IP2Bus_Data = new SLVSignal(userLogic.SLVDWidth) { InitialValue = StdLogicVector._0s(userLogic.SLVDWidth) };
_sig_IP2Bus_RdAck = new SLSignal() { InitialValue = '0' };
_sig_IP2Bus_WrAck = new SLSignal() { InitialValue = '0' };
_sig_IP2Bus_Error = new SLSignal() { InitialValue = '0' };
userLogic.Bus2IP_Clk = _sig_Bus2IP_Clk;
userLogic.Bus2IP_BE = _sig_Bus2IP_BE;
userLogic.Bus2IP_Clk = _sig_Bus2IP_Clk;
userLogic.Bus2IP_Data = _sig_Bus2IP_Data;
userLogic.Bus2IP_RdCE = _sig_Bus2IP_RdCE;
userLogic.Bus2IP_Resetn = _sig_Bus2IP_Resetn;
userLogic.Bus2IP_WrCE = _sig_Bus2IP_WrCE;
userLogic.IP2Bus_Data = _sig_IP2Bus_Data;
userLogic.IP2Bus_Error = _sig_IP2Bus_Error;
userLogic.IP2Bus_RdAck = _sig_IP2Bus_RdAck;
userLogic.IP2Bus_WrAck = _sig_IP2Bus_WrAck;
_clockGen = new Clock(new Time(10.0, ETimeUnit.ns))
{
Clk = _sig_Bus2IP_Clk
};
}
public TestDesign1(int width1, int width2)
{
_width1 = width1;
_width2 = width2;
_ctr1 = new SLVSignal(MaxWidth);
_ctr2 = new SLVSignal(MaxWidth);
_dummy = new SLVSignal(4 * MaxWidth);
_clkgen = new Clock(ClockPeriod)
{
Clk = _clk
};
_ctr1Logger = new ConsoleLogger <StdLogicVector>()
{
DataIn = _ctr1
};
_ctr2Logger = new ConsoleLogger <StdLogicVector>()
{
DataIn = _ctr2
};
_dummyLogger = new ConsoleLogger <StdLogicVector>()
{
DataIn = _dummy
};
}
public TestDesign1(int width1, int width2)
{
_width1 = width1;
_width2 = width2;
_ctr1 = new SLVSignal(MaxWidth);
_ctr2 = new SLVSignal(MaxWidth);
_dummy = new SLVSignal(4 * MaxWidth);
_clkgen = new Clock(ClockPeriod)
{
Clk = _clk
};
_ctr1Logger = new ConsoleLogger<StdLogicVector>()
{
DataIn = _ctr1
};
_ctr2Logger = new ConsoleLogger<StdLogicVector>()
{
DataIn = _ctr2
};
_dummyLogger = new ConsoleLogger<StdLogicVector>()
{
DataIn = _dummy
};
}
public override void Establish(IAutoBinder binder)
{
if (_allocated)
{
return;
}
_brAltFlagP = (SLVSignal)binder.GetSignal(EPortUsage.Default, "BCU_BrP", null, StdLogicVector._0s(1));
_brAltFlagN = (SLVSignal)binder.GetSignal(EPortUsage.Default, "BCU_BrN", null, StdLogicVector._1s(1));
_curState = binder.GetSignal(EPortUsage.State, "BCU_CurState", null, null).Descriptor;
_tState = _curState.ElementType.CILType;
Array enumValues = _tState.GetEnumValues();
int numStates = enumValues.Length;
object defaultState = Activator.CreateInstance(_tState);
_incState = binder.GetSignal(EPortUsage.Default, "BCU_IncState", null, defaultState).Descriptor;
_altState = binder.GetSignal(EPortUsage.Default, "BCU_AltState", null, defaultState).Descriptor;
_nextState = binder.GetSignal(EPortUsage.Default, "BCU_NextState", null, defaultState).Descriptor;
IncStateProcessBuilder ispb = new IncStateProcessBuilder(this);
Function incStateFn = ispb.GetAlgorithm();
incStateFn.Name = "BCU_IncState";
binder.CreateProcess(Process.EProcessKind.Triggered, incStateFn, _curState);
SyncProcessBuilder spb = new SyncProcessBuilder(this, binder);
Function syncStateFn = spb.GetAlgorithm();
syncStateFn.Name = "BCU_FSM";
ISignalOrPortDescriptor sdClock = binder.GetSignal <StdLogic>(EPortUsage.Clock, "Clk", null, '0').Descriptor;
binder.CreateProcess(Process.EProcessKind.Triggered, syncStateFn, sdClock);
_allocated = true;
}
public FPUWrapper(EISEVersion iseVer)
{
var a = new SLVSignal(32);
var b = new SLVSignal(32);
var r = new SLVSignal(32);
var clk = new SLSignal();
_fpu = new FloatingPointCore()
{
A = a,
B = b,
Clk = clk,
Result = r,
DSP48EUsage = FloatingPointCore.EDSP48EUsage.FullUsage,
Function = FloatingPointCore.EFunction.AddSubtract,
TargetDeviceFamily = SystemSharp.Interop.Xilinx.EDeviceFamily.Virtex6,
UseMaximumLatency = true,
Precision = FloatingPointCore.EPrecision.Single,
ResultPrecision = FloatingPointCore.EPrecision.Single,
AddSubSel = FloatingPointCore.EAddSub.Add,
TargetISEVersion = iseVer
};
Clk = clk;
A = a;
B = b;
R = r;
}
public void CreateControlpath(FlowMatrix flowSpec, string procName)
{
int ncsteps = flowSpec.NumCSteps;
string report = _mcd.ComputeEncoding(flowSpec, _maxSelWidth);
_curCW = (SLVSignal)_binder.GetSignal <StdLogicVector>(EPortUsage.Default, "CurCW", null,
StdLogicVector._0s(_mcd.CWWidth));
var clkInst = _binder.GetSignal <StdLogic>(EPortUsage.Clock, "Clk", null, '0');
if (_staged)
{
_mcd.CreateStagedDecoder(_binder, _curCW, (SLSignal)clkInst, _registered);
}
else
{
_mcd.CreateDecoder(_binder, _curCW);
}
CreateROM(ncsteps);
for (int cstep = 0; cstep < ncsteps; cstep++)
{
var cw = _mcd.Encode(cstep, flowSpec.GetFlow(cstep));
_romIf.PreWrite(StdLogicVector.FromUInt((uint)cstep, _pc.Size), cw);
}
var syncTempl = new SyncTemplate(this);
var syncFunc = syncTempl.GetAlgorithm();
_binder.CreateProcess(SystemSharp.Components.Process.EProcessKind.Triggered, syncFunc, clkInst.Descriptor);
_host.Descriptor.GetDocumentation().Documents.Add(new Document(procName + "_HMA_report.txt", report));
}
/// <summary>
/// Constructs a new testbechn.
/// </summary>
/// <param name="userLogic">component under test</param>
public AXILiteSlaveUserLogicTestbench(AXILiteSlaveUserLogic userLogic)
{
user_logic = userLogic;
_sig_Bus2IP_Clk = new SLSignal();
_sig_Bus2IP_Resetn = new SLSignal()
{
InitialValue = '0'
};
_sig_Bus2IP_Data = new SLVSignal(userLogic.SLVDWidth)
{
InitialValue = StdLogicVector.Xs(userLogic.SLVDWidth)
};
_sig_Bus2IP_BE = new SLVSignal(userLogic.SLVDWidth / 8)
{
InitialValue = StdLogicVector._0s(userLogic.SLVDWidth / 8)
};
_sig_Bus2IP_RdCE = new SLVSignal(userLogic.NumRegs)
{
InitialValue = StdLogicVector._0s(userLogic.NumRegs)
};
_sig_Bus2IP_WrCE = new SLVSignal(userLogic.NumRegs)
{
InitialValue = StdLogicVector._0s(userLogic.NumRegs)
};
_sig_IP2Bus_Data = new SLVSignal(userLogic.SLVDWidth)
{
InitialValue = StdLogicVector._0s(userLogic.SLVDWidth)
};
_sig_IP2Bus_RdAck = new SLSignal()
{
InitialValue = '0'
};
_sig_IP2Bus_WrAck = new SLSignal()
{
InitialValue = '0'
};
_sig_IP2Bus_Error = new SLSignal()
{
InitialValue = '0'
};
userLogic.Bus2IP_Clk = _sig_Bus2IP_Clk;
userLogic.Bus2IP_BE = _sig_Bus2IP_BE;
userLogic.Bus2IP_Clk = _sig_Bus2IP_Clk;
userLogic.Bus2IP_Data = _sig_Bus2IP_Data;
userLogic.Bus2IP_RdCE = _sig_Bus2IP_RdCE;
userLogic.Bus2IP_Resetn = _sig_Bus2IP_Resetn;
userLogic.Bus2IP_WrCE = _sig_Bus2IP_WrCE;
userLogic.IP2Bus_Data = _sig_IP2Bus_Data;
userLogic.IP2Bus_Error = _sig_IP2Bus_Error;
userLogic.IP2Bus_RdAck = _sig_IP2Bus_RdAck;
userLogic.IP2Bus_WrAck = _sig_IP2Bus_WrAck;
_clockGen = new Clock(new Time(10.0, ETimeUnit.ns))
{
Clk = _sig_Bus2IP_Clk
};
}
/// <summary>
/// Performs resource allocation and binding.
/// </summary>
/// <param name="dpb">datapath builder to use</param>
/// <returns>resulting flow matrix</returns>
public FlowMatrix Allocate(IDatapathBuilder dpb)
{
// Step 1: create intermediate storage for each instruction output slot
var tempSignals = new SLVSignal[_func.SlotTypes.Length];
for (int i = 0; i < _func.SlotTypes.Length; i++)
{
int width = TypeLowering.Instance.GetWireWidth(_func.SlotTypes[i]);
var initial = StdLogicVector.Us(width);
tempSignals[i] = (SLVSignal)Signals.CreateInstance(initial);
tempSignals[i].Descriptor.TagTemporary(i);
}
// Step 2: Allocate and establish unit bindings
Action <IXILMapping> onAlloc = map => dpb.AddFU(map.TASite.Host);
_alloc.OnFUAllocation += onAlloc;
var mappings = new Dictionary <int, IXILMapping>();
foreach (var xil3i in _func.Instructions)
{
TypeDescriptor[] otypes = xil3i.OperandSlots.Select(i => _func.SlotTypes[i]).ToArray();
TypeDescriptor[] rtypes = xil3i.ResultSlots.Select(i => _func.SlotTypes[i]).ToArray();
long cstep = CStep[xil3i];
var mapping = _alloc.TryBind(xil3i, cstep, otypes, rtypes);
if (mapping == null)
{
throw new XILSchedulingFailedException("Realization failed: " + xil3i.Command);
}
mappings[xil3i.Index] = mapping;
mapping.TASite.Establish(dpb.FUBinder);
Allocator.Policy.TellMapping(xil3i, cstep, mapping);
}
_alloc.OnFUAllocation -= onAlloc;
// Step 3: Assemble flow matrix
var result = new FlowMatrix();
foreach (var xil3i in _func.Instructions)
{
long cstep = CStep[xil3i];
var mapping = mappings[xil3i.Index];
result.AddNeutral(mapping.TASite.DoNothing());
var impl = mapping.Realize(
xil3i.OperandSlots.Select(s => tempSignals[s].AsSignalSource <StdLogicVector>()).ToArray(),
xil3i.ResultSlots.Select(s => tempSignals[s].AsCombSink()).ToArray());
if (impl.Count() - Latency[xil3i] > 1)
{
throw new XILSchedulingFailedException("Mapping length exceeds scheduled latency");
}
result.Add((int)cstep, impl);
result.AppendComment((int)cstep, ToComment(xil3i));
_mappingCache[xil3i.Index] = mapping;
}
return(result);
}
private void CreateState(int ncsteps)
{
int pcWidth = MathExt.CeilLog2(ncsteps);
_pc = (SLVSignal)_binder.GetSignal(EPortUsage.State, "State", null, StdLogicVector._0s(pcWidth));
_altAddr = (SLVSignal)_binder.GetSignal(EPortUsage.Default, "BCU_AltAddr", null, StdLogicVector._0s(pcWidth));
_rdEn = (SLSignal)_binder.GetSignal(EPortUsage.Default, "ROM_RdEn", null, StdLogic._1);
_brP = (SLVSignal)_binder.GetSignal <StdLogicVector>(EPortUsage.Default, "BCU_BrP", null, "0");
_brN = (SLVSignal)_binder.GetSignal <StdLogicVector>(EPortUsage.Default, "BCU_BrN", null, "1");
_rst = (SLSignal)_binder.GetSignal(EPortUsage.Default, "BCU_Rst", null, StdLogic._1);
}
protected override void PreInitialize()
{
_result = new SLVSignal(OutWidth);
_rpipe = new RegPipe(Latency, OutWidth);
Bind(() =>
{
_rpipe.Clk = CLK;
_rpipe.Din = _result;
_rpipe.Dout = S;
});
}
public void CreateStagedDecoder(IAutoBinder binder, SLVSignal cwSignal, SLSignal clkSignal, bool registered)
{
var valWordInit = StdLogicVector._0s(_vcf.ValueWordWidth);
var rcwSignal = (SLVSignal)binder.GetSignal(EPortUsage.Default, "D1_CW", null, valWordInit);
var rcwSignalDesc = rcwSignal.Descriptor;
SLVSignal rrcwSignal = null;
if (registered)
{
rrcwSignal = (SLVSignal)binder.GetSignal(EPortUsage.Default, "D2_CW", null, valWordInit);
}
var syncBuilder = new DefaultAlgorithmBuilder();
syncBuilder.If(clkSignal.ToSignalRef(SignalRef.EReferencedProperty.RisingEdge));
syncBuilder.Store(rcwSignal.ToSignalRef(SignalRef.EReferencedProperty.Next),
((ISignal)cwSignal[_vcf.ValueWordWidth - 1, 0]).ToSignalRef(SignalRef.EReferencedProperty.Cur));
if (registered)
{
syncBuilder.Store(rrcwSignal.ToSignalRef(SignalRef.EReferencedProperty.Next),
rcwSignal.ToSignalRef(SignalRef.EReferencedProperty.Cur));
}
foreach (var ms in _strings)
{
ms.AssembleStagedDecoderSync(binder, syncBuilder, cwSignal, registered);
}
syncBuilder.EndIf();
var syncFunc = syncBuilder.Complete();
syncFunc.Name = "cwdecode_sync";
binder.CreateProcess(SystemSharp.Components.Process.EProcessKind.Triggered, syncFunc, clkSignal.Descriptor);
var combBuilder = new DefaultAlgorithmBuilder();
var sensitivity = new HashSet <ISignalOrPortDescriptor>();
sensitivity.Add(cwSignal.Descriptor);
sensitivity.Add(rcwSignalDesc);
if (registered)
{
sensitivity.Add(rrcwSignal.Descriptor);
}
foreach (var ms in _strings)
{
ms.AssembleStagedDecoderComb(combBuilder, registered ? rrcwSignal : rcwSignal, sensitivity, registered);
}
var combFunc = combBuilder.Complete();
combFunc.Name = "cwdecode_comb";
binder.CreateProcess(SystemSharp.Components.Process.EProcessKind.Triggered, combFunc, sensitivity.ToArray());
}
/// <summary>
/// Constructs a new instance.
/// </summary>
/// <param name="inWidth">bit-width of operand</param>
/// <param name="outWidth">bit-width of result</param>
/// <param name="latency">desired latency</param>
public FixedAbs(int inWidth, int outWidth, int latency)
{
InputWidth = inWidth;
OutputWidth = outWidth;
Latency = latency;
if (latency > 1)
{
_pipeIn = new SLVSignal(outWidth);
_pipeOut = new SLVSignal(outWidth);
_rpipe = new RegPipe(latency, inWidth);
}
TASite = new TASiteImpl(this);
}
internal void AssembleStagedDecoderComb(IAlgorithmBuilder pbuilder, SLVSignal cwSignal,
HashSet <ISignalOrPortDescriptor> sensitivity, bool registered)
{
LiteralReference lrCWSelSlice = null;
if (SelWidth != 0)
{
lrCWSelSlice = new LiteralReference(
((ISignal)cwSignal[SelOffset + SelWidth - 1, SelOffset])
.ToSignalRef(SignalRef.EReferencedProperty.Cur));
}
_encFlow.AssembleStagedDecoderComb(_vfc, lrCWSelSlice, pbuilder, cwSignal, sensitivity, registered);
}
public void CreateDecoder(IAutoBinder binder, SLVSignal cwSignal)
{
var pbuilder = new DefaultAlgorithmBuilder();
var sensitivity = new HashSet <ISignalOrPortDescriptor>();
sensitivity.Add(cwSignal.Descriptor);
foreach (var ms in _strings)
{
ms.AssembleDecoder(pbuilder, cwSignal, sensitivity);
}
var decFunc = pbuilder.Complete();
decFunc.Name = "cwdecode";
binder.CreateProcess(SystemSharp.Components.Process.EProcessKind.Triggered, decFunc, sensitivity.ToArray());
}
/// <summary>
/// Constructs a new instance
/// </summary>
/// <param name="totalWidth">bit-width of operand</param>
/// <param name="operation">selected operation</param>
/// <param name="pipelineDepth">desired pipeline depth (i.e. computation latency)</param>
public FloatNegAbs(int totalWidth, EOperation operation, int pipelineDepth)
{
TotalWidth = totalWidth;
Operation = operation;
PipelineDepth = pipelineDepth;
_pipeIn = new SLVSignal(totalWidth);
if (pipelineDepth > 0)
{
_pipeOut = new SLVSignal(totalWidth);
}
TASite = new TransactionSite(this);
}
public Mod2TestDesign(int inIntWidth, int fracWidth, int outIntWidth)
{
_clk = new SLSignal();
_x = new SLVSignal(inIntWidth + fracWidth) { InitialValue = StdLogicVector._0s(inIntWidth + fracWidth) };
_r = new SLVSignal(outIntWidth + fracWidth) { InitialValue = StdLogicVector._0s(outIntWidth + fracWidth) };
_clkGen = new Clock(new Time(10.0, ETimeUnit.ns));
Bind(() => _clkGen.Clk = _clk);
_mod2 = new FixFPMod1(inIntWidth, fracWidth, outIntWidth)
{
X = _x,
R = _r
};
}
protected override void PreInitialize()
{
if (StartupAddr.Size != AddrWidth)
{
throw new InvalidOperationException("BCU: Invalid startup address");
}
_lastAddr = new SLVSignal(StdLogicVector._0s(AddrWidth));
_outAddr = new SLVSignal(AddrWidth);
if (Latency > 1)
{
_rstPat = StdLogicVector._1s(Latency - 1);
_rstq = new SLVSignal(_rstPat);
}
}
/// <summary>
/// Constructs a new instance.
/// </summary>
/// <param name="dataWidth">bit-width of operand</param>
/// <param name="pipelineDepth">number of pipeline stages, i.e. computation latency</param>
public Shifter(int dataWidth, int pipelineDepth)
{
DataWidth = dataWidth;
ShiftWidth = MathExt.CeilLog2(dataWidth);
PipelineDepth = pipelineDepth;
_y = new SLVSignal(DataWidth);
_pad = StdLogicVector._0s(DataWidth);
_pipe = new RegPipe(PipelineDepth, DataWidth);
Bind(() => {
_pipe.Clk = Clk;
_pipe.Din = _y;
_pipe.Dout = Y;
});
TASite = new ShifterTransactor(this);
}
internal void AssembleDecoder(IAlgorithmBuilder pbuilder, SLVSignal cwSignal, HashSet <ISignalOrPortDescriptor> sensitivity)
{
if (_encFlow.NumSymbols == 0)
{
foreach (var target in _targets)
{
pbuilder.Store(target, LiteralReference.CreateConstant(target.Desc.InitialValue));
}
}
else if (_encFlow.NumSymbols == 1)
{
var pflow = _encFlow.BwdEnc[0];
foreach (var flow in pflow.Flows)
{
ImplementFlow(flow, pbuilder, cwSignal, sensitivity);
}
}
else
{
var lrCWSelSlice = new LiteralReference(
((ISignal)cwSignal[SelOffset + SelWidth - 1, SelOffset])
.ToSignalRef(SignalRef.EReferencedProperty.Cur));
pbuilder.Switch(lrCWSelSlice);
for (int i = 0; i < _encFlow.NumSymbols; i++)
{
var selValue = StdLogicVector.FromUInt((uint)i, SelWidth);
var pflow = _encFlow.BwdEnc[i];
if (i + 1 == _encFlow.NumSymbols)
{
pbuilder.DefaultCase();
}
else
{
pbuilder.Case(LiteralReference.CreateConstant(selValue));
}
foreach (var flow in pflow.Flows)
{
ImplementFlow(flow, pbuilder, cwSignal, sensitivity);
}
pbuilder.EndCase();
}
pbuilder.EndSwitch();
}
}
public override void Establish(IAutoBinder binder)
{
if (_createSignal)
{
_constSignal = Host.Descriptor
.GetSignals()
.Where(s => s.HasAttribute <ConstLoadingTransactionSite>() &&
s.InitialValue.Equals(_constValue))
.Select(s => s.Instance)
.Cast <SLVSignal>()
.SingleOrDefault();
if (_constSignal == null)
{
_constSignal = (SLVSignal)binder.GetSignal(EPortUsage.Default, "const_" + _constValue.ToString(), null, _constValue);
_constSignal.Descriptor.AddAttribute(this);
}
}
}
public override void Establish(IAutoBinder binder)
{
if (_createSignal)
{
_constSignal = Host.Descriptor
.GetSignals()
.Where(s => s.HasAttribute<ConstLoadingTransactionSite>() &&
s.InitialValue.Equals(_constValue))
.Select(s => s.Instance)
.Cast<SLVSignal>()
.SingleOrDefault();
if (_constSignal == null)
{
_constSignal = (SLVSignal)binder.GetSignal(EPortUsage.Default, "const_" + _constValue.ToString(), null, _constValue);
_constSignal.Descriptor.AddAttribute(this);
}
}
}
public override void Establish(IAutoBinder binder)
{
if (_established)
{
return;
}
_clk = binder.GetSignal(EPortUsage.Clock, null, null, null).Descriptor;
_enI = (SLSignal)binder.GetSignal(EPortUsage.Default, _port.Name + "_en", null, StdLogic._1);
_en = _enI.Descriptor;
_slvSignalI = (SLVSignal)binder.GetSignal(EPortUsage.Default, _port.Name + "_in", null, StdLogicVector._0s(_dataWidth));
_slvSignal = _slvSignalI.Descriptor;
var templ = new ConvProcessBuilder(this);
var alg = templ.GetAlgorithm();
binder.CreateProcess(Process.EProcessKind.Triggered, alg, _clk, _en);
_established = true;
}
/// <summary>
/// Maps a signal to a register.
/// </summary>
/// <param name="sig">signal to map</param>
/// <param name="mode">register access</param>
/// <param name="reg">register index</param>
/// <param name="startBit">start bit in register</param>
protected void MapSignal(SLVSignal sig, EAccessMode mode, int reg, int startBit)
{
if (mode != EAccessMode.Read)
{
for (int i = 0; i < sig.Size(); i++)
{
_writeBits[reg, i + startBit] = sig[i];
}
_writeSignals.Add(sig);
}
if (mode != EAccessMode.Write)
{
for (int i = 0; i < sig.Size(); i++)
{
_readBits[reg, i + startBit] = sig[i];
}
_readSignals.Add(sig);
}
}
protected override void PreInitialize()
{
_t = new SLVSignal(PhaseWidth)
{
InitialValue = StdLogicVector._0s(PhaseWidth)
};
PINC = new SLVSignal(PhaseWidth)
{
InitialValue = StdLogicVector._0s(PhaseWidth)
};
POFF = new SLVSignal(PhaseWidth)
{
InitialValue = StdLogicVector._0s(PhaseWidth)
};
PH = new SLVSignal(PhaseWidth)
{
InitialValue = StdLogicVector._0s(PhaseWidth)
};
PhaseIn = new SLVSignal(PhaseWidth)
{
InitialValue = StdLogicVector._0s(PhaseWidth)
};
phase3 = new SLVSignal(PhaseWidth)
{
InitialValue = StdLogicVector._0s(PhaseWidth)
};
Dat_in = new SLVSignal(PhaseWidth)
{
InitialValue = StdLogicVector._0s(PhaseWidth)
};
Dat_outOff = new SLVSignal(PhaseWidth)
{
InitialValue = StdLogicVector._0s(PhaseWidth)
};
_RegPipe = new RegPipe(Latency, PhaseWidth)
{
Clk = CLK,
Din = Dat_in,
Dout = Dat_outOff,
};
}
protected override void PreInitialize()
{
int width = OutputWidthHigh - OutputWidthLow + 1;
_pipeIn = new SLVSignal(width);
if (PipeStages > 0)
{
_outPipe = new RegPipe(PipeStages, width);
Bind(() =>
{
_outPipe.Clk = CLK;
_outPipe.Din = _pipeIn;
_outPipe.Dout = P;
});
}
else
{
AddProcess(DrivePIm, _pipeIn);
}
}
public override void Establish(IAutoBinder binder)
{
if (_realized)
{
return;
}
_inSignals = _argWidths.Select((w, i) =>
(SLVSignal)binder.GetSignal(EPortUsage.Default, "concat" + i, null,
StdLogicVector.Us(w))).ToArray();
int total = _argWidths.Sum();
_outSignal = (SLVSignal)binder.GetSignal(EPortUsage.Default, "concout", null, StdLogicVector.Us(total));
var pb = new ConcatProcessBuilder(this);
var alg = pb.GetAlgorithm();
alg.Name = "concatenize";
binder.CreateProcess(Process.EProcessKind.Triggered, alg, _inSignals.Select(s => s.Descriptor).ToArray());
_realized = true;
}
/// <summary>
/// Constructs a new instance.
/// </summary>
/// <param name="mappedVariable">variable to be hardware-mapped</param>
/// <param name="directFeed"><c>true</c>, if write-trough semantics hold, i.e. input is combinatorially routed to output during write access</param>
public LocalStorageUnit(Variable mappedVariable, bool directFeed)
{
MappedVariable = mappedVariable;
_directFeed = directFeed;
DataWidth = (int)TypeLowering.Instance.GetWireType(mappedVariable.Type).Constraints[0].Size;
StdLogicVector initial;
if (mappedVariable.InitialValue == null)
{
initial = StdLogicVector._0s(TypeLowering.Instance.GetWireWidth(mappedVariable.Type));
}
else
{
initial = Marshal.SerializeForHW(mappedVariable.InitialValue);
}
_stg = new SLVSignal(DataWidth)
{
InitialValue = initial
};
_taSite = new LocalStorageUnitTransactionSite(this);
}
public Mod2TestDesign(int inIntWidth, int fracWidth, int outIntWidth)
{
_clk = new SLSignal();
_x = new SLVSignal(inIntWidth + fracWidth)
{
InitialValue = StdLogicVector._0s(inIntWidth + fracWidth)
};
_r = new SLVSignal(outIntWidth + fracWidth)
{
InitialValue = StdLogicVector._0s(outIntWidth + fracWidth)
};
_clkGen = new Clock(new Time(10.0, ETimeUnit.ns));
Bind(() => _clkGen.Clk = _clk);
_mod2 = new FixFPMod1(inIntWidth, fracWidth, outIntWidth)
{
X = _x,
R = _r
};
}
protected override void PreInitialize()
{
_quotient = new SLVSignal(DividendAndQuotientWidth);
_remainder = new SLVSignal(FractionWidth);
_quotientOut = new SLVSignal(DividendAndQuotientWidth);
_remainderOut = new SLVSignal(FractionWidth);
_qpipe = new RegPipe(Latency, DividendAndQuotientWidth);
Bind(() =>
{
_qpipe.Clk = CLK;
_qpipe.Din = _quotient;
_qpipe.Dout = _quotientOut;
});
_rpipe = new RegPipe(Latency, FractionWidth);
Bind(() =>
{
_rpipe.Clk = CLK;
_rpipe.Din = _remainder;
_rpipe.Dout = _remainderOut;
});
}
public TestHLS_SinCosLUT_Testbench(int xFracWidth, int yFracWidth)
{
_xFracWidth = xFracWidth;
_yFracWidth = yFracWidth;
_x = new SLVSignal(2 + xFracWidth);
_sin = new SLVSignal(2 + yFracWidth);
_cos = new SLVSignal(2 + yFracWidth);
_dut = new TestHLS_SinCosLUT(xFracWidth, yFracWidth)
{
Clk = _clk,
X = _x,
Sin = _sin,
Cos = _cos,
Rdy = _rdy
};
_clkGen = new Clock(new Time(10.0, ETimeUnit.ns))
{
Clk = _clk
};
}
/// <summary>
/// Constructs a new instance.
/// </summary>
/// <param name="depth">depth of shift register (i.e. number of stages)</param>
/// <param name="width">bit-width of shift register</param>
/// <param name="useEn">whether to use shift enable input</param>
public RegPipe(int depth, int width, bool useEn = false)
{
Contract.Requires<ArgumentOutOfRangeException>(depth >= 0, "depth must be non-negative");
Contract.Requires<ArgumentOutOfRangeException>(width > 0, "width must be positive");
Contract.Requires<ArgumentOutOfRangeException>(depth > 0 || !useEn, "need at least 1 stage if using enable input.");
_width = width;
_depth = depth;
UseEn = useEn;
if (depth > 1)
{
int bits = width * depth;
_belowbit = bits - width - 1;
_stages = new SLVSignal(bits)
{
InitialValue = StdLogicVector._0s(bits)
};
}
else if (depth < 0)
{
throw new ArgumentException("Depth must be >= 0");
}
}
public override void Establish(IAutoBinder binder)
{
if (_allocated)
return;
_brAltFlagP = (SLVSignal)binder.GetSignal(EPortUsage.Default, "BCU_BrP", null, StdLogicVector._0s(1));
_brAltFlagN = (SLVSignal)binder.GetSignal(EPortUsage.Default, "BCU_BrN", null, StdLogicVector._1s(1));
_curState = binder.GetSignal(EPortUsage.State, "BCU_CurState", null, null).Descriptor;
_tState = _curState.ElementType.CILType;
Array enumValues = _tState.GetEnumValues();
int numStates = enumValues.Length;
object defaultState = Activator.CreateInstance(_tState);
_incState = binder.GetSignal(EPortUsage.Default, "BCU_IncState", null, defaultState).Descriptor;
_altState = binder.GetSignal(EPortUsage.Default, "BCU_AltState", null, defaultState).Descriptor;
_nextState = binder.GetSignal(EPortUsage.Default, "BCU_NextState", null, defaultState).Descriptor;
IncStateProcessBuilder ispb = new IncStateProcessBuilder(this);
Function incStateFn = ispb.GetAlgorithm();
incStateFn.Name = "BCU_IncState";
binder.CreateProcess(Process.EProcessKind.Triggered, incStateFn, _curState);
SyncProcessBuilder spb = new SyncProcessBuilder(this, binder);
Function syncStateFn = spb.GetAlgorithm();
syncStateFn.Name = "BCU_FSM";
ISignalOrPortDescriptor sdClock = binder.GetSignal<StdLogic>(EPortUsage.Clock, "Clk", null, '0').Descriptor;
binder.CreateProcess(Process.EProcessKind.Triggered, syncStateFn, sdClock);
_allocated = true;
}
/// <summary>
/// Maps a signal to a register.
/// </summary>
/// <param name="sig">signal to map</param>
/// <param name="mode">register access</param>
/// <param name="reg">register index</param>
/// <param name="startBit">start bit in register</param>
protected void MapSignal(SLVSignal sig, EAccessMode mode, int reg, int startBit)
{
if (mode != EAccessMode.Read)
{
for (int i = 0; i < sig.Size(); i++)
_writeBits[reg, i + startBit] = sig[i];
_writeSignals.Add(sig);
}
if (mode != EAccessMode.Write)
{
for (int i = 0; i < sig.Size(); i++)
_readBits[reg, i + startBit] = sig[i];
_readSignals.Add(sig);
}
}
/// <summary>
/// Constructs a new instance
/// </summary>
/// <param name="totalWidth">bit-width of operand</param>
/// <param name="operation">selected operation</param>
/// <param name="pipelineDepth">desired pipeline depth (i.e. computation latency)</param>
public FloatNegAbs(int totalWidth, EOperation operation, int pipelineDepth)
{
TotalWidth = totalWidth;
Operation = operation;
PipelineDepth = pipelineDepth;
_pipeIn = new SLVSignal(totalWidth);
if (pipelineDepth > 0)
{
_pipeOut = new SLVSignal(totalWidth);
}
TASite = new TransactionSite(this);
}
private void ImplementFlow(ValueFlowCoder vfc, Flow flow, IAlgorithmBuilder pbuilder, SLVSignal cwSignal, HashSet<ISignalOrPortDescriptor> sensitivity)
{
if (FlowMatrix.IsDontCareFlow(flow))
{
int valOffset = vfc.GetValueWordOffset(flow.Target);
int valWidth = vfc.GetValueWordWidth(flow.Target);
LiteralReference lrCWValSlice;
if (flow.Target.Desc.ElementType.CILType.Equals(typeof(StdLogic)))
{
lrCWValSlice = new LiteralReference(
((ISignal)cwSignal[valOffset])
.ToSignalRef(SignalRef.EReferencedProperty.Cur));
}
else
{
lrCWValSlice = new LiteralReference(
((ISignal)cwSignal[valOffset + valWidth - 1, valOffset])
.ToSignalRef(SignalRef.EReferencedProperty.Cur));
}
pbuilder.Store(flow.Target, lrCWValSlice);
}
else if (flow is SignalFlow)
{
var sflow = flow as SignalFlow;
pbuilder.Store(flow.Target, sflow.Source);
sensitivity.Add(sflow.Source.Desc);
}
else
{
var vflow = flow as ValueFlow;
pbuilder.Store(vflow.Target,
LiteralReference.CreateConstant(vflow.Value));
}
}
protected override void PreInitialize()
{
_t = new SLVSignal(PhaseWidth)
{
InitialValue = StdLogicVector._0s(PhaseWidth)
};
PINC = new SLVSignal(PhaseWidth)
{
InitialValue = StdLogicVector._0s(PhaseWidth)
};
POFF = new SLVSignal(PhaseWidth)
{
InitialValue = StdLogicVector._0s(PhaseWidth)
};
PH = new SLVSignal(PhaseWidth)
{
InitialValue = StdLogicVector._0s(PhaseWidth)
};
PhaseIn = new SLVSignal(PhaseWidth)
{
InitialValue = StdLogicVector._0s(PhaseWidth)
};
phase3 = new SLVSignal(PhaseWidth)
{
InitialValue = StdLogicVector._0s(PhaseWidth)
};
Dat_in = new SLVSignal(PhaseWidth)
{
InitialValue = StdLogicVector._0s(PhaseWidth)
};
Dat_outOff = new SLVSignal(PhaseWidth)
{
InitialValue = StdLogicVector._0s(PhaseWidth)
};
_RegPipe = new RegPipe(Latency, PhaseWidth)
{
Clk = CLK,
Din = Dat_in,
Dout = Dat_outOff,
};
}
/// <summary>
/// Constructs a new instance.
/// </summary>
/// <param name="funcSel">which operation the ALU is supposed to carry out</param>
/// <param name="arithMode">signedness of operands/result</param>
/// <param name="pipelineDepth">desired latency</param>
/// <param name="awidth">width of first (or sole) operand</param>
/// <param name="bwidth">width of second operand</param>
/// <param name="rwidth">width of result</param>
/// <exception cref="ArgumentOutOfRangeException">if parameter is invalid or inconsistency between parameters was detected</exception>
public ALU(EFunction funcSel, EArithMode arithMode,
int pipelineDepth, int awidth, int bwidth, int rwidth)
{
Contract.Requires<ArgumentOutOfRangeException>(pipelineDepth >= 0, "Pipeline depth must be non-negative.");
Contract.Requires<ArgumentOutOfRangeException>(awidth >= 1, "Operand width A must be positive.");
Contract.Requires<ArgumentOutOfRangeException>(funcSel.IsUnary() || bwidth >= 1, "Operand width B must be positive.");
Contract.Requires<ArgumentOutOfRangeException>(funcSel == EFunction.Compare || rwidth >= 1, "Result width must be positive");
Contract.Requires<ArgumentOutOfRangeException>(funcSel == EFunction.Add || funcSel == EFunction.Mul || funcSel == EFunction.Neg ||
funcSel == EFunction.Sub || awidth == bwidth, "Operand sizes must be equal for this kind of operation.");
Contract.Requires<ArgumentOutOfRangeException>(funcSel == EFunction.Add || funcSel == EFunction.Compare ||
funcSel == EFunction.Mul || funcSel == EFunction.Neg || funcSel == EFunction.Sub || rwidth == awidth,
"Result and operand sizes must be equal for this kind of instruction.");
FuncSel = funcSel;
ArithMode = arithMode;
PipelineDepth = pipelineDepth;
if (funcSel == EFunction.Compare)
rwidth = 6;
AWidth = awidth;
BWidth = bwidth;
RWidth = rwidth;
_opResult = new SLVSignal(rwidth)
{
InitialValue = StdLogicVector._0s(rwidth)
};
if (pipelineDepth >= 3)
{
// If pipeline depth > 0, the operand inputs will be registered.
// Thus, the post pipeline must be reduced by one stage.
_pipe = new RegPipe(Math.Max(0, pipelineDepth - 1), rwidth);
if (FuncSel == EFunction.Compare)
{
_pipeOut = new SLVSignal(rwidth)
{
InitialValue = StdLogicVector._0s(rwidth)
};
Bind(() =>
{
_pipe.Clk = Clk;
_pipe.Din = _opResult;
_pipe.Dout = _pipeOut;
});
}
else
{
Bind(() =>
{
_pipe.Clk = Clk;
_pipe.Din = _opResult;
_pipe.Dout = R;
});
}
}
_transactor = new ALUTransactor(this);
}
public ALUTestDesign(int awidth, int bwidth, int pipelineDepth)
{
_clk = new SLSignal();
_a = new SLVSignal(awidth) { InitialValue = StdLogicVector._0s(awidth) };
_b = new SLVSignal(bwidth) { InitialValue = StdLogicVector._0s(bwidth) };
_ba = new SLVSignal(awidth) { InitialValue = StdLogicVector._0s(awidth) };
_clkGen = new Clock(new Time(10.0, ETimeUnit.ns));
Bind(() => _clkGen.Clk = _clk);
_add = new ALU(ALU.EFunction.Add, ALU.EArithMode.Signed, pipelineDepth,
awidth, bwidth, Math.Max(awidth, bwidth) + 1);
Bind(() =>
{
_add.Clk = _clk;
_add.A = _a;
_add.B = _b;
_add.R = _rAdd;
});
_rAdd = new SLVSignal(_add.RWidth);
_sub = new ALU(ALU.EFunction.Sub, ALU.EArithMode.Signed, pipelineDepth,
awidth, bwidth, Math.Max(awidth, bwidth) + 1);
Bind(() =>
{
_sub.Clk = _clk;
_sub.A = _a;
_sub.B = _b;
_sub.R = _rSub;
});
_rSub = new SLVSignal(_sub.RWidth);
_mul = new ALU(ALU.EFunction.Mul, ALU.EArithMode.Signed, pipelineDepth,
awidth, bwidth, awidth + bwidth);
Bind(() =>
{
_mul.Clk = _clk;
_mul.A = _a;
_mul.B = _b;
_mul.R = _rMul;
});
_rMul = new SLVSignal(_mul.RWidth);
_neg = new ALU(ALU.EFunction.Neg, ALU.EArithMode.Signed, pipelineDepth,
awidth, 0, awidth + 1);
Bind(() =>
{
_neg.Clk = _clk;
_neg.A = _a;
_neg.R = _rNeg;
});
_rNeg = new SLVSignal(_neg.RWidth);
_not = new ALU(ALU.EFunction.Not, ALU.EArithMode.Signed, pipelineDepth,
awidth, 0, awidth);
Bind(() =>
{
_not.Clk = _clk;
_not.A = _a;
_not.R = _rNot;
});
_rNot = new SLVSignal(_not.RWidth);
_and = new ALU(ALU.EFunction.And, ALU.EArithMode.Signed, pipelineDepth,
awidth, awidth, awidth);
Bind(() =>
{
_and.Clk = _clk;
_and.A = _a;
_and.B = _ba;
_and.R = _rAnd;
});
_rAnd = new SLVSignal(_and.RWidth);
_or = new ALU(ALU.EFunction.Or, ALU.EArithMode.Signed, pipelineDepth,
awidth, awidth, awidth);
Bind(() =>
{
_or.Clk = _clk;
_or.A = _a;
_or.B = _ba;
_or.R = _rOr;
});
_rOr = new SLVSignal(_or.RWidth);
}
/// <summary>
/// Constructs a new instance
/// </summary>
/// <param name="xIntWidth">integer width of operand</param>
/// <param name="xFracWidth">fractional width of operand</param>
/// <param name="yIntWidth">integer width of result</param>
/// <param name="yFracWidth">fractional width of result</param>
/// <param name="pipeStages">desired computation-only latency</param>
public LERPUnit(int xIntWidth, int xFracWidth, int yIntWidth, int yFracWidth, int pipeStages)
{
Contract.Requires<ArgumentOutOfRangeException>(xIntWidth > 0, "xIntWidth must be positive.");
Contract.Requires<ArgumentOutOfRangeException>(xFracWidth >= 0, "xFracWidth must be non-negative.");
Contract.Requires<ArgumentOutOfRangeException>(yIntWidth + yFracWidth > 0, "total bit-width of result must be positive");
Contract.Requires<ArgumentOutOfRangeException>(pipeStages >= 0, "pipeStages must be non-negative.");
Contract.Requires<ArgumentOutOfRangeException>(xFracWidth > 0 || pipeStages == 0, "xFracWidth == 0 is a degenerate case (lookup-only). No additional pipeline stages allowed.");
PipeStages = pipeStages;
XIntWidth = xIntWidth;
XFracWidth = xFracWidth;
YIntWidth = yIntWidth;
YFracWidth = yFracWidth;
AddrWidth = xIntWidth;
_yIn = new SLVSignal(yIntWidth + yFracWidth);
_yOut = new SLVSignal(yIntWidth + yFracWidth);
_yPipe = new RegPipe(pipeStages, yIntWidth + yFracWidth);
Bind(() =>
{
_yPipe.Clk = Clk;
_yPipe.Din = _yIn;
_yPipe.Dout = _yOut;
});
}
internal void AssembleStagedDecoderComb(IAlgorithmBuilder pbuilder, SLVSignal cwSignal,
HashSet<ISignalOrPortDescriptor> sensitivity, bool registered)
{
LiteralReference lrCWSelSlice = null;
if (SelWidth != 0)
{
lrCWSelSlice = new LiteralReference(
((ISignal)cwSignal[SelOffset + SelWidth - 1, SelOffset])
.ToSignalRef(SignalRef.EReferencedProperty.Cur));
}
_encFlow.AssembleStagedDecoderComb(_vfc, lrCWSelSlice, pbuilder, cwSignal, sensitivity, registered);
}
/// <summary>
/// Creates an instance of a Counter component.
/// </summary>
/// <param name="width">the desired bit-width of the counter</param>
public Counter(int width)
{
_ctr = new SLVSignal(StdLogicVector._1s(width));
}
protected override void PreInitialize()
{
_result = new SLVSignal(OutWidth);
_rpipe = new RegPipe(Latency, OutWidth);
Bind(() =>
{
_rpipe.Clk = CLK;
_rpipe.Din = _result;
_rpipe.Dout = S;
});
}
protected override void PreInitialize()
{
_rin = new SLVSignal(ResultWidth);
_rout = new SLVSignal(ResultWidth);
_rpipe = new RegPipe(Latency, ResultWidth);
Bind(() =>
{
_rpipe.Clk = Clk;
_rpipe.Din = _rin;
_rpipe.Dout = _rout;
});
}
public override void Establish(IAutoBinder binder)
{
if (_realized)
return;
object constValue;
var literal = (Literal)_literal;
if (literal.IsConst(out constValue))
{
var slv = Marshal.SerializeForHW(constValue);
_dataOutI = (SLVSignal)binder.GetSignal(EPortUsage.Default, "constSignal_" + constValue.ToString(), null, slv);
_dataOut = _dataOutI.Descriptor;
}
else
{
bool needRead = true, needWrite = true;
var fref = _literal as FieldRef;
if (fref != null)
{
needRead = fref.FieldDesc.IsReadInCurrentContext(Host.Context);
needWrite = fref.FieldDesc.IsWrittenInCurrentContext(Host.Context);
}
var stlit = (IStorableLiteral)_literal;
string name = stlit.Name;
var valueSample = _literal.Type.GetSampleInstance();
_dataBits = Marshal.SerializeForHW(valueSample).Size;
_clkI = (SLSignal)binder.GetSignal(EPortUsage.Clock, null, null, null);
_clk = _clkI.Descriptor;
if (needWrite)
{
_wrEnI = (SLSignal)binder.GetSignal(EPortUsage.Default, name + "_wrEn", null, StdLogic._0);
_wrEn = _wrEnI.Descriptor;
_dataInI = (SLVSignal)binder.GetSignal(EPortUsage.Default, name + "_dataIn", null, StdLogicVector._0s(_dataBits));
_dataIn = _dataInI.Descriptor;
}
if (needRead)
{
_dataOutI = (SLVSignal)binder.GetSignal(EPortUsage.Default, name + "_dataOut", null, StdLogicVector._0s(_dataBits));
_dataOut = _dataOutI.Descriptor;
}
//var apb = new AccessProcessBuilder(this, needRead, needWrite);
//var alg = apb.GetAlgorithm();
//alg.Name = name + "_process";
//binder.CreateProcess(Process.EProcessKind.Triggered, alg, _clk);
CommonClockProcess ccp = null;
string algName = name + "_process";
if (Host.Descriptor.HasAttribute<CommonClockProcess>())
{
ccp = Host.Descriptor.QueryAttribute<CommonClockProcess>();
Host.Descriptor.RemoveChild(ccp.CCProc);
}
else
{
ccp = new CommonClockProcess(_clk);
Host.Descriptor.AddAttribute(ccp);
}
ccp.AddAccessor(this, needRead, needWrite);
var alg = ccp.FrameBuilder.Complete();
alg.Name = algName;
ccp.CCProc = binder.CreateProcess(Process.EProcessKind.Triggered, alg, _clk);
}
_realized = true;
}
/// <summary>
/// Creates an instance.
/// </summary>
/// <param name="userLogic">component under test</param>
public AXIMasterUserLogicTestbench(AXIMasterUserLogic userLogic)
{
user_logic = userLogic;
_sig_Bus2IP_Clk = new SLSignal();
_sig_Bus2IP_Resetn = new SLSignal() { InitialValue = '0' };
_sig_Bus2IP_Data = new SLVSignal(userLogic.SLVDWidth) { InitialValue = StdLogicVector.Xs(userLogic.SLVDWidth) };
_sig_Bus2IP_BE = new SLVSignal(userLogic.SLVDWidth / 8) { InitialValue = StdLogicVector._0s(userLogic.SLVDWidth / 8) };
_sig_Bus2IP_RdCE = new SLVSignal(userLogic.NumRegs) { InitialValue = StdLogicVector._0s(userLogic.NumRegs) };
_sig_Bus2IP_WrCE = new SLVSignal(userLogic.NumRegs) { InitialValue = StdLogicVector._0s(userLogic.NumRegs) };
_sig_IP2Bus_Data = new SLVSignal(userLogic.SLVDWidth) { InitialValue = StdLogicVector._0s(userLogic.SLVDWidth) };
_sig_IP2Bus_RdAck = new SLSignal() { InitialValue = '0' };
_sig_IP2Bus_WrAck = new SLSignal() { InitialValue = '0' };
_sig_IP2Bus_Error = new SLSignal() { InitialValue = '0' };
_sig_ip2bus_mstrd_req = new SLSignal() { InitialValue = '0' };
_sig_ip2bus_mstwr_req = new SLSignal() { InitialValue = '0' };
_sig_ip2bus_mst_addr = new SLVSignal(userLogic.MasterAXIAddrWidth) { InitialValue = StdLogicVector.Us(userLogic.MasterAXIAddrWidth) };
_sig_ip2bus_mst_be = new SLVSignal(userLogic.NativeDataWidth/8) { InitialValue = StdLogicVector._1s(userLogic.NativeDataWidth/8) };
_sig_ip2bus_mst_length = new SLVSignal(userLogic.LengthWidth) { InitialValue = StdLogicVector._0s(userLogic.LengthWidth) };
_sig_ip2bus_mst_type = new SLSignal() { InitialValue = '0' };
_sig_ip2bus_mst_lock = new SLSignal() { InitialValue = '0' };
_sig_ip2bus_mst_reset = new SLSignal() { InitialValue = '0' };
_sig_bus2ip_mst_cmdack = new SLSignal() { InitialValue = '0' };
_sig_bus2ip_mst_cmplt = new SLSignal() { InitialValue = '0' };
_sig_bus2ip_mst_error = new SLSignal() { InitialValue = '0' };
_sig_bus2ip_mst_rearbitrate = new SLSignal() { InitialValue = '0' };
_sig_bus2ip_mst_cmd_timeout = new SLSignal() { InitialValue = '0' };
_sig_bus2ip_mstrd_d = new SLVSignal(userLogic.NativeDataWidth);
_sig_bus2ip_mstrd_rem = new SLVSignal(userLogic.NativeDataWidth / 8) { InitialValue = StdLogicVector._0s(userLogic.NativeDataWidth / 8) };
_sig_bus2ip_mstrd_sof_n = new SLSignal() { InitialValue = '0' };
_sig_bus2ip_mstrd_eof_n = new SLSignal() { InitialValue = '0' };
_sig_bus2ip_mstrd_src_rdy_n = new SLSignal() { InitialValue = '1' };
_sig_bus2ip_mstrd_src_dsc_n = new SLSignal() { InitialValue = '1' };
_sig_ip2bus_mstrd_dst_rdy_n = new SLSignal() { InitialValue = '1' };
_sig_ip2bus_mstrd_dst_dsc_n = new SLSignal() { InitialValue = '1' };
_sig_ip2bus_mstwr_d = new SLVSignal(userLogic.NativeDataWidth);
_sig_ip2bus_mstwr_rem = new SLVSignal(userLogic.NativeDataWidth / 8) { InitialValue = StdLogicVector._0s(userLogic.NativeDataWidth / 8) };
_sig_ip2bus_mstwr_src_rdy_n = new SLSignal() { InitialValue = '1' };
_sig_ip2bus_mstwr_src_dsc_n = new SLSignal() { InitialValue = '1' };
_sig_ip2bus_mstwr_sof_n = new SLSignal() { InitialValue = '1' };
_sig_ip2bus_mstwr_eof_n = new SLSignal() { InitialValue = '1' };
_sig_bus2ip_mstwr_dst_rdy_n = new SLSignal() { InitialValue = '1' };
_sig_bus2ip_mstwr_dst_dsc_n = new SLSignal() { InitialValue = '1' };
userLogic.Bus2IP_Clk = _sig_Bus2IP_Clk;
userLogic.Bus2IP_BE = _sig_Bus2IP_BE;
userLogic.Bus2IP_Clk = _sig_Bus2IP_Clk;
userLogic.Bus2IP_Data = _sig_Bus2IP_Data;
userLogic.Bus2IP_RdCE = _sig_Bus2IP_RdCE;
userLogic.Bus2IP_Resetn = _sig_Bus2IP_Resetn;
userLogic.Bus2IP_WrCE = _sig_Bus2IP_WrCE;
userLogic.IP2Bus_Data = _sig_IP2Bus_Data;
userLogic.IP2Bus_Error = _sig_IP2Bus_Error;
userLogic.IP2Bus_RdAck = _sig_IP2Bus_RdAck;
userLogic.IP2Bus_WrAck = _sig_IP2Bus_WrAck;
userLogic.ip2bus_mstrd_req = _sig_ip2bus_mstrd_req;
userLogic.ip2bus_mstwr_req = _sig_ip2bus_mstwr_req;
userLogic.ip2bus_mst_addr = _sig_ip2bus_mst_addr;
userLogic.ip2bus_mst_be = _sig_ip2bus_mst_be;
userLogic.ip2bus_mst_length = _sig_ip2bus_mst_length;
userLogic.ip2bus_mst_type = _sig_ip2bus_mst_type;
userLogic.ip2bus_mst_lock = _sig_ip2bus_mst_lock;
userLogic.ip2bus_mst_reset = _sig_ip2bus_mst_reset;
userLogic.bus2ip_mst_cmdack = _sig_bus2ip_mst_cmdack;
userLogic.bus2ip_mst_cmplt = _sig_bus2ip_mst_cmplt;
userLogic.bus2ip_mst_error = _sig_bus2ip_mst_error;
userLogic.bus2ip_mst_rearbitrate = _sig_bus2ip_mst_rearbitrate;
userLogic.bus2ip_mst_cmd_timeout = _sig_bus2ip_mst_cmd_timeout;
userLogic.bus2ip_mstrd_d = _sig_bus2ip_mstrd_d;
userLogic.bus2ip_mstrd_rem = _sig_bus2ip_mstrd_rem;
userLogic.bus2ip_mstrd_sof_n = _sig_bus2ip_mstrd_sof_n;
userLogic.bus2ip_mstrd_eof_n = _sig_bus2ip_mstrd_eof_n;
userLogic.bus2ip_mstrd_src_rdy_n = _sig_bus2ip_mstrd_src_rdy_n;
userLogic.bus2ip_mstrd_src_dsc_n = _sig_bus2ip_mstrd_src_dsc_n;
userLogic.ip2bus_mstrd_dst_rdy_n = _sig_ip2bus_mstrd_dst_rdy_n;
userLogic.ip2bus_mstrd_dst_dsc_n = _sig_ip2bus_mstrd_dst_dsc_n;
userLogic.ip2bus_mstwr_d = _sig_ip2bus_mstwr_d;
userLogic.ip2bus_mstwr_rem = _sig_ip2bus_mstwr_rem;
userLogic.ip2bus_mstwr_src_rdy_n = _sig_ip2bus_mstwr_src_rdy_n;
userLogic.ip2bus_mstwr_src_dsc_n = _sig_ip2bus_mstwr_src_dsc_n;
userLogic.ip2bus_mstwr_sof_n = _sig_ip2bus_mstwr_sof_n;
userLogic.ip2bus_mstwr_eof_n = _sig_ip2bus_mstwr_eof_n;
userLogic.bus2ip_mstwr_dst_rdy_n = _sig_bus2ip_mstwr_dst_rdy_n;
userLogic.bus2ip_mstwr_dst_dsc_n = _sig_bus2ip_mstwr_dst_dsc_n;
_clockGen = new Clock(new Time(10.0, ETimeUnit.ns))
{
Clk = _sig_Bus2IP_Clk
};
}
public void CreateDecoder(IAutoBinder binder, SLVSignal cwSignal)
{
var pbuilder = new DefaultAlgorithmBuilder();
var sensitivity = new HashSet<ISignalOrPortDescriptor>();
sensitivity.Add(cwSignal.Descriptor);
foreach (var ms in _strings)
{
ms.AssembleDecoder(pbuilder, cwSignal, sensitivity);
}
var decFunc = pbuilder.Complete();
decFunc.Name = "cwdecode";
binder.CreateProcess(SystemSharp.Components.Process.EProcessKind.Triggered, decFunc, sensitivity.ToArray());
}
/// <summary>
/// Constructs a new instance
/// </summary>
/// <param name="lutWidth">resolution of data table</param>
/// <param name="xFracWidth">fractional width of operand</param>
/// <param name="yFracWidth">fractional width of result</param>
/// <param name="pipeStages">additional pipeline stages for interpolation computation</param>
public SinCosLUTCore(int lutWidth, int xFracWidth, int yFracWidth, int pipeStages)
{
PipeStages = pipeStages;
XIntWidth = 2;
XFracWidth = xFracWidth;
YIntWidth = 2;
YFracWidth = yFracWidth;
DIntWidth = 2;
DFracWidth = yFracWidth;
LUTWidth = lutWidth;
_x = new Signal<UFix>()
{
InitialValue = UFix.FromDouble(0.0, LUTWidth + 1, XFracWidth - LUTWidth - 1)
};
_xq = new Signal<UFix>()
{
InitialValue = UFix.FromDouble(0.0, LUTWidth + 1, XFracWidth - LUTWidth - 1)
};
_sinRaw = new Signal<SFix>()
{
InitialValue = SFix.FromDouble(0.0, YIntWidth, YFracWidth)
};
_cosRaw = new Signal<SFix>()
{
InitialValue = SFix.FromDouble(0.0, YIntWidth, YFracWidth)
};
_sinIn = new SLVSignal(YIntWidth + YFracWidth)
{
InitialValue = SFix.FromDouble(0.0, YIntWidth, YFracWidth).SLVValue
};
_cosIn = new SLVSignal(YIntWidth + YFracWidth)
{
InitialValue = SFix.FromDouble(0.0, YIntWidth, YFracWidth).SLVValue
};
_sinOut = new SLVSignal(YIntWidth + YFracWidth)
{
InitialValue = SFix.FromDouble(0.0, YIntWidth, YFracWidth).SLVValue
};
_cosOut = new SLVSignal(YIntWidth + YFracWidth)
{
InitialValue = SFix.FromDouble(0.0, YIntWidth, YFracWidth).SLVValue
};
AddrWidth = lutWidth + 1;
_sinAddr = new Signal<Unsigned>()
{
InitialValue = Unsigned.FromUInt(0, AddrWidth)
};
_cosAddr = new Signal<Unsigned>()
{
InitialValue = Unsigned.FromUInt(0, AddrWidth)
};
_sinData = new Signal<SFix>()
{
InitialValue = SFix.FromDouble(0.0, YIntWidth, YFracWidth)
};
_cosData = new Signal<SFix>()
{
InitialValue = SFix.FromDouble(0.0, YIntWidth, YFracWidth)
};
_sinLUT = new VSignal<SFix>((1 << lutWidth) + 2, _ => new Signal<SFix>()
{
InitialValue = SFix.FromDouble(Math.Sin(Math.PI * 0.5 * _ / (double)(1 << lutWidth)), 2, yFracWidth)
});
_sinFlipSignIn = new SLVSignal(1)
{
InitialValue = "0"
};
_cosFlipSignIn = new SLVSignal(1)
{
InitialValue = "0"
};
_sinFlipSignOut = new SLVSignal(1)
{
InitialValue = "0"
};
_cosFlipSignOut = new SLVSignal(1)
{
InitialValue = "0"
};
_mirror = UFix.FromUnsigned(Unsigned.One.Resize(XFracWidth + 2) << (xFracWidth + 1), xFracWidth - LUTWidth);
_mirror2 = UFix.FromUnsigned(Unsigned.One.Resize(XFracWidth + 2) << xFracWidth, xFracWidth - LUTWidth);
_sinPipe = new RegPipe(pipeStages, YIntWidth + YFracWidth);
Bind(() => {
_sinPipe.Clk = Clk;
_sinPipe.Din = _sinIn;
_sinPipe.Dout = _sinOut;
});
_cosPipe = new RegPipe(pipeStages, YIntWidth + YFracWidth);
Bind(() => {
_cosPipe.Clk = Clk;
_cosPipe.Din = _cosIn;
_cosPipe.Dout = _cosOut;
});
_sinFlipSignPipe = new RegPipe(2, 1);
Bind(() => {
_sinFlipSignPipe.Clk = Clk;
_sinFlipSignPipe.Din = _sinFlipSignIn;
_sinFlipSignPipe.Dout = _sinFlipSignOut;
});
_cosFlipSignPipe = new RegPipe(2, 1);
Bind(() => {
_cosFlipSignPipe.Clk = Clk;
_cosFlipSignPipe.Din = _cosFlipSignIn;
_cosFlipSignPipe.Dout = _cosFlipSignOut;
});
_sinUnit = new LERPUnit(lutWidth + 1, xFracWidth - 1 - lutWidth, YIntWidth, yFracWidth, 0);
Bind(() =>
{
_sinUnit.Clk = Clk;
_sinUnit.X = _x;
_sinUnit.Y = _sinRaw;
_sinUnit.Addr = _sinAddr;
_sinUnit.Data = _sinData;
});
_cosUnit = new LERPUnit(lutWidth + 1, xFracWidth - 1 - lutWidth, YIntWidth, yFracWidth, 0);
Bind(() =>
{
_cosUnit.Clk = Clk;
_cosUnit.X = _xq;
_cosUnit.Y = _cosRaw;
_cosUnit.Addr = _cosAddr;
_cosUnit.Data = _cosData;
});
TASite = new TransactionSite(this);
}
protected override void PreInitialize()
{
_quotient = new SLVSignal(DividendAndQuotientWidth);
_remainder = new SLVSignal(FractionWidth);
_quotientOut = new SLVSignal(DividendAndQuotientWidth);
_remainderOut = new SLVSignal(FractionWidth);
_qpipe = new RegPipe(Latency, DividendAndQuotientWidth);
Bind(() =>
{
_qpipe.Clk = CLK;
_qpipe.Din = _quotient;
_qpipe.Dout = _quotientOut;
});
_rpipe = new RegPipe(Latency, FractionWidth);
Bind(() =>
{
_rpipe.Clk = CLK;
_rpipe.Din = _remainder;
_rpipe.Dout = _remainderOut;
});
}
/// <summary>
/// Constructs a new instance.
/// </summary>
/// <param name="dataWidth">bit-width of operand</param>
/// <param name="pipelineDepth">number of pipeline stages, i.e. computation latency</param>
public Shifter(int dataWidth, int pipelineDepth)
{
DataWidth = dataWidth;
ShiftWidth = MathExt.CeilLog2(dataWidth);
PipelineDepth = pipelineDepth;
_y = new SLVSignal(DataWidth);
_pad = StdLogicVector._0s(DataWidth);
_pipe = new RegPipe(PipelineDepth, DataWidth);
Bind(() => {
_pipe.Clk = Clk;
_pipe.Din = _y;
_pipe.Dout = Y;
});
TASite = new ShifterTransactor(this);
}
public void CreateStagedDecoder(IAutoBinder binder, SLVSignal cwSignal, SLSignal clkSignal, bool registered)
{
var valWordInit = StdLogicVector._0s(_vcf.ValueWordWidth);
var rcwSignal = (SLVSignal)binder.GetSignal(EPortUsage.Default, "D1_CW", null, valWordInit);
var rcwSignalDesc = rcwSignal.Descriptor;
SLVSignal rrcwSignal = null;
if (registered)
{
rrcwSignal = (SLVSignal)binder.GetSignal(EPortUsage.Default, "D2_CW", null, valWordInit);
}
var syncBuilder = new DefaultAlgorithmBuilder();
syncBuilder.If(clkSignal.ToSignalRef(SignalRef.EReferencedProperty.RisingEdge));
syncBuilder.Store(rcwSignal.ToSignalRef(SignalRef.EReferencedProperty.Next),
((ISignal)cwSignal[_vcf.ValueWordWidth - 1, 0]).ToSignalRef(SignalRef.EReferencedProperty.Cur));
if (registered)
{
syncBuilder.Store(rrcwSignal.ToSignalRef(SignalRef.EReferencedProperty.Next),
rcwSignal.ToSignalRef(SignalRef.EReferencedProperty.Cur));
}
foreach (var ms in _strings)
{
ms.AssembleStagedDecoderSync(binder, syncBuilder, cwSignal, registered);
}
syncBuilder.EndIf();
var syncFunc = syncBuilder.Complete();
syncFunc.Name = "cwdecode_sync";
binder.CreateProcess(SystemSharp.Components.Process.EProcessKind.Triggered, syncFunc, clkSignal.Descriptor);
var combBuilder = new DefaultAlgorithmBuilder();
var sensitivity = new HashSet<ISignalOrPortDescriptor>();
sensitivity.Add(cwSignal.Descriptor);
sensitivity.Add(rcwSignalDesc);
if (registered)
sensitivity.Add(rrcwSignal.Descriptor);
foreach (var ms in _strings)
{
ms.AssembleStagedDecoderComb(combBuilder, registered ? rrcwSignal : rcwSignal, sensitivity, registered);
}
var combFunc = combBuilder.Complete();
combFunc.Name = "cwdecode_comb";
binder.CreateProcess(SystemSharp.Components.Process.EProcessKind.Triggered, combFunc, sensitivity.ToArray());
}
internal void AssembleStagedDecoderSync(IAutoBinder binder, IAlgorithmBuilder pbuilder, SLVSignal cwSignal, bool registered)
{
LiteralReference lrCWSelSlice = null;
if (SelWidth != 0)
{
lrCWSelSlice = new LiteralReference(
((ISignal)cwSignal[SelOffset + SelWidth - 1, SelOffset])
.ToSignalRef(SignalRef.EReferencedProperty.Cur));
}
_encFlow.AssembleStagedDecoderSync(Enumerable.Range(1, _encFlow.NumSymbols).ToArray(),
SelWidth, lrCWSelSlice, binder, pbuilder, registered);
}
public override void Establish(IAutoBinder binder)
{
if (_realized)
return;
_addrBits = MathExt.CeilLog2(_array.ArrayObj.Length);
_dataBits = Marshal.SerializeForHW(_array.ElementType.GetSampleInstance()).Size;
_clkI = (SLSignal)binder.GetSignal(EPortUsage.Clock, "Clk", null, null);
_dataOutI = (SLVSignal)binder.GetSignal(EPortUsage.Default, "memIf_dataOut", null, StdLogicVector._0s(_dataBits));
_addrI = (SLVSignal)binder.GetSignal(EPortUsage.Default, "memIf_addr", null, StdLogicVector._0s(_addrBits));
_clk = _clkI.Descriptor;
_addr = _addrI.Descriptor;
_dataOut = _dataOutI.Descriptor;
if (NeedWriteAccess)
{
_wrEnI = (SLSignal)binder.GetSignal(EPortUsage.Default, "memIf_wrEn", null, StdLogic._0);
_dataInI = (SLVSignal)binder.GetSignal(EPortUsage.Default, "memIf_dataIn", null, StdLogicVector._0s(_dataBits));
_wrEn = _wrEnI.Descriptor;
_dataIn = _dataInI.Descriptor;
}
var memIfBuilder = new MemIfBuilder(this);
var memIfAlg = memIfBuilder.GetAlgorithm();
memIfAlg.Name = "MemIf";
binder.CreateProcess(Process.EProcessKind.Triggered, memIfAlg, _clk);
_realized = true;
}
/// <summary>
/// Constructs a new instance.
/// </summary>
/// <param name="inWidth">bit-width of operand</param>
/// <param name="outWidth">bit-width of result</param>
/// <param name="latency">desired latency</param>
public FixedAbs(int inWidth, int outWidth, int latency)
{
InputWidth = inWidth;
OutputWidth = outWidth;
Latency = latency;
if (latency > 1)
{
_pipeIn = new SLVSignal(outWidth);
_pipeOut = new SLVSignal(outWidth);
_rpipe = new RegPipe(latency, inWidth);
}
TASite = new TASiteImpl(this);
}
/// <summary>
/// Constructs a testbench instance. All other instances are created
/// and bound here.
/// </summary>
public SimpleCounterTestbench()
{
// Create a clock generator and bind its output to the clock signal.
_m_clk = new Clock(ClockPeriod)
{
Clk = _clk
};
for (int i = 0; i < NumCounters; i++)
{
//The internal signal for storing the counter value
var _ctr = new SLVSignal(CounterSize);
// Create a counter and bind it the the clock and the counter value signal.
var _m_ctr = new Counter(CounterSize)
{
Clk = _clk,
Ctr = _ctr
};
// Create a logger which will display the counter value at the console output.
var _m_logger = new ConsoleLogger<StdLogicVector>()
{
DataIn = _ctr
};
}
}
