public static BitVecExpr Create_Key(Rn reg, string key, Context ctx)
{
Contract.Requires(ctx != null);
uint nBits = (uint)RegisterTools.NBits(reg);
if (RegisterTools.Is_SIMD_Register(reg))
{
(uint high, uint low) = SIMD_Extract_Range(reg);
return(ctx.MkExtract(high, low, ctx.MkBVConst(Reg_Name(reg, key), 32 * 512)));
}
else if (RegisterTools.IsGeneralPurposeRegister(reg))
{
if (nBits == 64)
{
return(ctx.MkBVConst(Reg_Name(reg, key), 64));
}
else
{
Rn reg64 = RegisterTools.Get64BitsRegister(reg);
return(RegisterTools.Is8BitHigh(reg)
? ctx.MkExtract(15, 8, ctx.MkBVConst(Reg_Name(reg64, key), 64))
: ctx.MkExtract(nBits - 1, 0, ctx.MkBVConst(Reg_Name(reg64, key), 64)));
}
}
else
{
return(ctx.MkBVConst(Reg_Name(reg, key), nBits));
}
}
public static BitVecExpr Create_Key(Rn reg, String key, Context ctx)
{
uint nBits = (uint)RegisterTools.NBits(reg);
if (RegisterTools.Is_SIMD_Register(reg))
{
var range = SIMD_Extract_Range(reg);
return(ctx.MkExtract(range.High, range.Low, ctx.MkBVConst(Tools.Reg_Name(reg, key), 32 * 512)));
}
else if (RegisterTools.IsGeneralPurposeRegister(reg))
{
if (nBits == 64)
{
return(ctx.MkBVConst(Reg_Name(reg, key), 64));
}
else
{
Rn reg64 = RegisterTools.Get64BitsRegister(reg);
return((RegisterTools.Is8BitHigh(reg))
? ctx.MkExtract(15, 8, ctx.MkBVConst(Reg_Name(reg64, key), 64))
: ctx.MkExtract(nBits - 1, 0, ctx.MkBVConst(Reg_Name(reg64, key), 64)));
}
}
else
{
return(ctx.MkBVConst(Reg_Name(reg, key), nBits));
}
}
private void AddInstruction_Nop(int lineNumber)
{
Context ctx = this._ctx;
string asm = "NOP";
int ln0 = lineNumber - 1;
int ln1 = lineNumber;
BoolExpr instruction_Switch = ctx.MkBoolConst("L" + lineNumber + "_" + asm);
this._switches[lineNumber].Add(instruction_Switch);
IList <BoolExpr> r = new List <BoolExpr>();
for (int i = 0; i < this._registers.Count; ++i)
{
Rn reg = this._registers[i];
r.Add(ctx.MkEq(GetReg(reg, lineNumber, ctx), GetReg(reg, lineNumber - 1, ctx)));
r.Add(ctx.MkEq(GetRegGoal(reg, ln1, ctx), GetRegGoal(reg, ln0, ctx))); // make the prerequisite a goal
r.Add(ctx.MkEq(GetRegProvided(reg, ln1, ctx), GetRegProvided(reg, ln0, ctx))); //rax0 is based on (variable) input but is not a constant
}
this._solver.Assert(ctx.MkImplies(
instruction_Switch,
ctx.MkAnd(r)
));
}
public ButtonInfo(TextBox text, Rn reg, bool before)
{
this.text = text;
this.reg = reg;
this.flag = Flags.NONE;
this.before = before;
}
public bool Is_Redundant(Rn regName, string key1, string key2)
{
lock (this._ctxLock)
{
this.UndefGrounding = true; // needed!
bool popNeeded = false;
if ((this.BranchInfoStore != null) && (this.BranchInfoStore.Count > 0))
{
this.Solver.Push();
this.Solver_U.Push();
this.AssertBranchInfoToSolver();
popNeeded = true;
}
using (Expr e1 = Tools.Create_Key(regName, key1, this._ctx))
using (Expr e2 = Tools.Create_Key(regName, key2, this._ctx))
using (BoolExpr e = this._ctx.MkEq(e1, e2))
{
Tv result = ToolsZ3.GetTv(e, e, this.Solver, this.Solver_U, this._ctx);
if (popNeeded)
{
this.Solver.Pop();
this.Solver_U.Pop();
}
return(result == Tv.ONE);
}
}
}
public BitVecExpr Create_Tail(Rn regName)
{
lock (this._ctxLock)
{
return(Tools.Create_Key(regName, this.TailKey, this._ctx));
}
}
public void SetDescription(Rn reg, AsmDudeTools asmDudeTools)
{
string regStr = reg.ToString();
this.Description.Inlines.Add(new Run("Register ")
{
FontWeight = FontWeights.Bold, Foreground = this._foreground
});
this.Description.Inlines.Add(new Run(regStr)
{
FontWeight = FontWeights.Bold, Foreground = new SolidColorBrush(AsmDudeToolsStatic.ConvertColor(Settings.Default.SyntaxHighlighting_Register))
});
Arch arch = RegisterTools.GetArch(reg);
string archStr = (arch == Arch.ARCH_NONE) ? "" : " [" + ArchTools.ToString(arch) + "] ";
string descr = asmDudeTools.Get_Description(regStr);
if (regStr.Length > (AsmDudePackage.maxNumberOfCharsInToolTips / 2))
{
descr = "\n" + descr;
}
string full_Descr = AsmSourceTools.Linewrap(":" + archStr + descr, AsmDudePackage.maxNumberOfCharsInToolTips);
this.Description.Inlines.Add(new Run(full_Descr)
{
Foreground = this._foreground
});
}
public ButtonInfo(TextBox text, Flags flag, bool before)
{
this.text = text;
this.reg = Rn.NOREG;
this.flag = flag;
this.before = before;
}
public string Create([Bind(Exclude = "Id")] Rn Model)
{
ApplicationDbContext db = new ApplicationDbContext();
string msg;
try
{
if (ModelState.IsValid)
{
db.Rns.Add(Model);
db.SaveChanges();
msg = "Сохранено успешно";
}
else
{
msg = "Данные не прошли проверку ввода";
}
}
catch (Exception ex)
{
msg = "Произошла ошибка:" + ex.Message;
}
return(msg);
}
public override int GetHashCode()
{
int hashCode = 13;
hashCode = (hashCode * 7) + Rn.GetHashCode();
return(hashCode);
}
public static void AreEqual(Rn name, Tv[] expectedTvArray, State state)
{
Contract.Requires(state != null);
Contract.Requires(expectedTvArray != null);
Assert.IsNotNull(state);
int nBits = RegisterTools.NBits(name);
Assert.AreEqual(nBits, expectedTvArray.Length);
Tv[] actualTvArray = state.GetTvArray(name);
Assert.AreEqual(nBits, actualTvArray.Length);
ulong?actualLong = ToolsZ3.ToUlong(actualTvArray);
ulong?expectedLong = ToolsZ3.ToUlong(expectedTvArray);
if (actualLong.HasValue && expectedLong.HasValue)
{
Assert.AreEqual(expectedLong.Value, actualLong.Value, "Reg " + name + ": Expected value " + expectedLong.Value + " while actual value is " + actualLong.Value);
}
else
{
AreEqual(expectedTvArray, actualTvArray);
}
}
private void AddInstruction_Sub(Rn reg1, Rn reg2, int lineNumber)
{
Context ctx = this._ctx;
string asm = "SUB_" + reg1 + "_" + reg2;
int ln0 = lineNumber - 1;
int ln1 = lineNumber;
BoolExpr instruction_Switch = ctx.MkBoolConst("L" + lineNumber + "_" + asm);
this._switches[lineNumber].Add(instruction_Switch);
{
BitVecExpr x = ctx.MkBVSub(GetReg(reg1, ln0, ctx), GetReg(reg2, ln0, ctx));
BoolExpr newRegState = MakeRuleRegResult(reg1, this._registers, x, lineNumber, ctx);
BoolExpr newFlagState = ctx.MkAnd(
ZeroFlag(reg1, lineNumber, ctx),
OverFlowFlag(reg1, lineNumber, ctx)
);
this._solver.Assert(ctx.MkImplies(instruction_Switch, newRegState));
this._solver.Assert(ctx.MkImplies(instruction_Switch, newFlagState));
}
{
BoolExpr newState = ctx.MkAnd(
ctx.MkEq(GetRegKnown(Rn.RAX, ln1, ctx), (reg1 == Rn.RAX) ? GetRegKnown(reg2, ln0, ctx) : GetRegKnown(Rn.RAX, ln0, ctx)),
ctx.MkEq(GetRegKnown(Rn.RBX, ln1, ctx), (reg1 == Rn.RBX) ? GetRegKnown(reg2, ln0, ctx) : GetRegKnown(Rn.RBX, ln0, ctx)),
ctx.MkEq(GetRegKnown(Rn.RCX, ln1, ctx), (reg1 == Rn.RCX) ? GetRegKnown(reg2, ln0, ctx) : GetRegKnown(Rn.RCX, ln0, ctx)),
ctx.MkEq(GetRegKnown(Rn.RDX, ln1, ctx), (reg1 == Rn.RDX) ? GetRegKnown(reg2, ln0, ctx) : GetRegKnown(Rn.RDX, ln0, ctx)),
ZeroFlag(reg1, lineNumber, ctx),
OverFlowFlag(reg1, lineNumber, ctx)
);
this._solver.Assert(ctx.MkImplies(instruction_Switch, newState));
//this._solver.Assert(ctx.MkImplies(instruction_Switch, IsKnownTest(reg1, ln0, ctx)));
//this._solver.Assert(ctx.MkImplies(instruction_Switch, IsKnownTest(reg2, ln0, ctx)));
}
}
public static string Reg_Name(Rn reg, string key)
{
if (RegisterTools.Is_SIMD_Register(reg))
{
return("SIMD" + key);
}
return(reg.ToString() + key);
}
private void AddInstruction_Inc(Rn reg, int lineNumber)
{
Context ctx = this._ctx;
string asm = "INC_" + reg;
uint nBits = (uint)RegisterTools.NBits(reg);
int ln0 = lineNumber - 1;
int ln1 = lineNumber;
BoolExpr instruction_Switch = ctx.MkBoolConst("L" + lineNumber + "_" + asm);
this._switches[lineNumber].Add(instruction_Switch);
if (true)
{
BitVecExpr x = ctx.MkBVAdd(GetReg(reg, ln0, ctx), ctx.MkBV(1, nBits));
this._solver.Assert(ctx.MkImplies(
instruction_Switch,
MakeRuleRegResult(reg, this._registers, x, lineNumber, ctx)
));
this._solver.Assert(ctx.MkImplies(
instruction_Switch,
ctx.MkAnd(
GetRegGoal(reg, ln0, ctx), // make the prerequisite a goal
GetRegGoal(reg, ln1, ctx), // make application of this rule goal directed
GetRegProvided(reg, ln0, ctx), //rax0 is based on (variable) input but is not a constant
GetRegProvided(reg, ln1, ctx) //rax1 is based on (variable) input but is not a constant
)
));
}
if (false)
{
BitVecExpr x = ctx.MkBVAdd(GetReg(reg, ln0, ctx), ctx.MkBV(1, nBits));
BoolExpr newRegState = MakeRuleRegResult(reg, this._registers, x, lineNumber, ctx);
BoolExpr newFlagState = ctx.MkAnd(
ZeroFlag(reg, lineNumber, ctx),
OverFlowFlag(reg, lineNumber, ctx)
);
this._solver.Assert(ctx.MkImplies(instruction_Switch, newRegState));
//this._solver.Assert(ctx.MkImplies(instruction_Switch, newFlagState));
}
if (false)
{
BoolExpr newState = ctx.MkAnd(
ctx.MkEq(GetRegKnown(Rn.RAX, ln1, ctx), GetRegKnown(Rn.RAX, ln0, ctx)),
ctx.MkEq(GetRegKnown(Rn.RBX, ln1, ctx), GetRegKnown(Rn.RBX, ln0, ctx)),
ctx.MkEq(GetRegKnown(Rn.RCX, ln1, ctx), GetRegKnown(Rn.RCX, ln0, ctx)),
ctx.MkEq(GetRegKnown(Rn.RDX, ln1, ctx), GetRegKnown(Rn.RDX, ln0, ctx)),
ZeroFlag(reg, lineNumber, ctx),
OverFlowFlag(reg, lineNumber, ctx)
);
this._solver.Assert(ctx.MkImplies(instruction_Switch, newState));
//this._solver.Assert(ctx.MkImplies(instruction_Switch, IsKnownTest(reg, ln1, ctx)));
}
}
private static BoolExpr ZeroFlag(Rn reg, int lineNumber, Context ctx)
{
int ln0 = lineNumber - 1;
int ln1 = lineNumber;
uint nBits = (uint)RegisterTools.NBits(reg);
BitVecExpr ZERO = ctx.MkBV(0, nBits);
return(ctx.MkEq(GetFlag(Flags.ZF, ln1, ctx), ctx.MkEq(GetReg(reg, ln1, ctx), ZERO)));
}
public string Delete(int Id)
{
ApplicationDbContext db = new ApplicationDbContext();
Rn rns = db.Rns.Find(Id);
db.Rns.Remove(rns);
db.SaveChanges();
return("Удалено успешно");
}
public string GetRegisterValue(Rn name, IState_R state)
{
if (state == null)
{
return("");
}
Tv5[] reg = state.GetTv5Array(name);
return(string.Format("{0} = {1}", ToolsZ3.ToStringBin(reg), ToolsZ3.ToStringHex(reg)));
}
private static BoolExpr MakeRuleRegResult(Rn selectedReg, IList <Rn> regs, BitVecExpr newState, int lineNumber, Context ctx)
{
BoolExpr[] r = new BoolExpr[regs.Count];
for (int i = 0; i < regs.Count; ++i)
{
Rn reg1 = regs[i];
r[i] = ctx.MkEq(GetReg(reg1, lineNumber, ctx), (selectedReg == reg1) ? newState : GetReg(reg1, lineNumber - 1, ctx));
}
return(ctx.MkAnd(r));
}
public Operand(string token)
{
//TODO: properly handle optional elements {K}{Z} {AES}{ER}
string token2 = token.
Replace("{K0}", "").
Replace("{K1}", "").
Replace("{K2}", "").
Replace("{K3}", "").
Replace("{K4}", "").
Replace("{K5}", "").
Replace("{K6}", "").
Replace("{K7}", "").
Replace("{Z}", "").
Replace("{ER}", "").
Replace("{SAE}", "").
Replace("{1TO4}", "").
Replace("{1TO8}", "").
Replace("{1TO16}", "");
this._str = token;
Tuple <bool, Rn, int> t0 = RegisterTools.toRn(token2);
if (t0.Item1)
{
this._type = Ot.reg;
this._rn = t0.Item2;
this._nBits = t0.Item3;
}
else
{
Tuple <bool, ulong, int> t1 = AsmSourceTools.toConstant(token2);
if (t1.Item1)
{
this._type = Ot.imm;
this._imm = t1.Item2;
this._nBits = t1.Item3;
}
else
{
Tuple <bool, Rn, Rn, int, long, int> t2 = AsmSourceTools.parseMemOperand(token2);
if (t2.Item1)
{
this._type = Ot.mem;
this._mem = new Tuple <Rn, Rn, int, long>(t2.Item2, t2.Item3, t2.Item4, t2.Item5);
this._nBits = t2.Item6;
}
else
{
this._type = Ot.UNKNOWN;
this._nBits = -1;
}
}
}
}
public Tv[] GetTvArray(Rn regName)
{
lock (this._ctxLock)
{
if (this.Frozen && this._cached_Reg_Values.TryGetValue(regName, out var value))
{
return(value);
}
try
{
this.UndefGrounding = true; // needed!
bool popNeeded = false;
if ((this.BranchInfoStore != null) && (this.BranchInfoStore.Count > 0))
{
this.Solver.Push();
this.Solver_U.Push();
this.AssertBranchInfoToSolver();
popNeeded = true;
}
using (BitVecExpr regExpr = this.Create(regName))
{
Tv[] result = ToolsZ3.GetTvArray(regExpr, RegisterTools.NBits(regName), this.Solver, this.Solver_U, this._ctx);
if (popNeeded)
{
this.Solver.Pop();
this.Solver_U.Pop();
}
if (this.Frozen)
{
if (ADD_COMPUTED_VALUES && (RegisterTools.NBits(regName) == 64))
{
ulong?value2 = ToolsZ3.ToUlong(result);
if (value2 != null)
{
this.Solver.Assert(this.Ctx.MkEq(regExpr, this.Ctx.MkBV(value2.Value, 64)));
this.Solver_Dirty = true;
}
}
this._cached_Reg_Values[regName] = result;
}
return(result);
}
}
catch (Exception e)
{
Console.WriteLine("WARNING: AsmSimulator: " + e.ToString());
return(new Tv[RegisterTools.NBits(regName)]);
}
}
}
public bool Is_Undefined(Rn regName)
{
Tv[] result = this.GetTvArray(regName);
foreach (Tv tv in result)
{
if (tv == Tv.UNDEFINED)
{
return(true);
}
}
return(false);
}
public static bool isBoundRegister(Rn rn)
{
switch (rn)
{
case Rn.BND0:
case Rn.BND1:
case Rn.BND2:
case Rn.BND3:
return(true);
default: return(false);
}
}
public static Tuple <bool, Rn, int> toRn(string str)
{
Rn rn = parseRn(str);
if (rn == Rn.NOREG)
{
return(new Tuple <bool, Rn, int>(false, Rn.NOREG, 0));
}
else
{
return(new Tuple <bool, Rn, int>(true, rn, nBits(rn)));
}
}
public string RandomProgram(int nInstructions)
{
StringBuilder sb = new StringBuilder();
for (int i = 0; i < nInstructions; ++i)
{
Mnemonic m = this._eligibleMnemonics[this._rand.Next(this._eligibleMnemonics.Count)];
Rn reg1 = RandomReg();
Rn reg2 = RandomReg();
sb.AppendLine(MakeCodeLine(m, reg1, reg2));
}
return(sb.ToString().TrimEnd());
}
private void AddInstruction_Mov(Rn reg, int lineNumber)
{
Context ctx = this._ctx;
#region Create Constant
string constantName_prev = "Const-Mov-" + reg + "-L" + (lineNumber - 1);
string constantName = "Const-Mov-" + reg + "-L" + lineNumber;
BitVecExpr constant = ctx.MkBVConst(constantName, 64);
this._constants.Add(constantName, constant);
#endregion
int ln0 = lineNumber - 1;
int ln1 = lineNumber;
BoolExpr instruction_Switch = ctx.MkBoolConst("L" + lineNumber + "_MOV_" + reg + "_" + constantName);
this._switches[lineNumber].Add(instruction_Switch);
{
BoolExpr newState = MakeRuleRegResult(reg, this._registers, constant, lineNumber, ctx);
this._solver.Assert(ctx.MkImplies(instruction_Switch, newState));
}
{
BitVecExpr knownConstant = MakeKnownConst(reg, ctx);
BoolExpr newState = ctx.MkAnd(
ctx.MkEq(GetRegKnown(Rn.RAX, ln1, ctx), (reg == Rn.RAX) ? knownConstant : GetRegKnown(Rn.RAX, ln0, ctx)),
ctx.MkEq(GetRegKnown(Rn.RBX, ln1, ctx), (reg == Rn.RBX) ? knownConstant : GetRegKnown(Rn.RBX, ln0, ctx)),
ctx.MkEq(GetRegKnown(Rn.RCX, ln1, ctx), (reg == Rn.RCX) ? knownConstant : GetRegKnown(Rn.RCX, ln0, ctx)),
ctx.MkEq(GetRegKnown(Rn.RDX, ln1, ctx), (reg == Rn.RDX) ? knownConstant : GetRegKnown(Rn.RDX, ln0, ctx))
);
this._solver.Assert(ctx.MkImplies(instruction_Switch, newState));
}
if (true)
{
if (lineNumber > 1)
{
// prevent destructive writes : try not to overwrite registers that have been written in the privious line.
BoolExpr switch_Mov_Previous = ctx.MkBoolConst("L" + (lineNumber - 1) + "_MOV_" + reg + "_" + constantName_prev);
this._solver.Assert(ctx.MkNot(ctx.MkAnd(switch_Mov_Previous, instruction_Switch)));
BoolExpr switch_Inc_Previous = ctx.MkBoolConst("L" + (lineNumber - 1) + "_INC_" + reg);
this._solver.Assert(ctx.MkNot(ctx.MkAnd(switch_Inc_Previous, instruction_Switch)));
BoolExpr switch_Dec_Previous = ctx.MkBoolConst("L" + (lineNumber - 1) + "_DEC_" + reg);
this._solver.Assert(ctx.MkNot(ctx.MkAnd(switch_Dec_Previous, instruction_Switch)));
}
}
}
private string ToString(Rn name, State state)
{
Tv[] array = state.GetTv5Array(name);
var tup = ToolsZ3.HasOneValue(array);
if (tup.hasOneValue)
{
return(ToolsZ3.ToStringBin(tup.value) + "");
}
else
{
return(ToolsZ3.ToStringBin(array));
}
}
public static bool isSegmentRegister(Rn rn)
{
switch (rn)
{
case Rn.CS:
case Rn.DS:
case Rn.ES:
case Rn.SS:
case Rn.FS:
case Rn.GS: return(true);
default:
return(false);
}
}
private static BitVecExpr MakeUnknownConst(Rn reg, Context ctx)
{
switch (RegisterTools.NBits(reg))
{
case 64: return(ctx.MkBV(0xFFFF_FFFF_FFFF_FFFF, 64));
case 32: return(ctx.MkBV(0xFFFF_FFFF, 32));
case 16: return(ctx.MkBV(0xFFFF, 16));
case 8: return(ctx.MkBV(0xFF, 8));
default: throw new Exception();
}
}
public void Test_MemZ3_Forward_Eq6()
{
StateConfig stateConfig = new StateConfig();
stateConfig.Set_All_Off();
stateConfig.RAX = true;
stateConfig.RBX = true;
stateConfig.RCX = true;
stateConfig.RDX = true;
stateConfig.Mem = true;
State state = this.CreateState(stateConfig);
Context ctx = state.Ctx;
Tools tools = state.Tools;
Rn reg1 = Rn.CL;
Rn reg2 = Rn.DL;
int nBytes = RegisterTools.NBits(reg1) >> 3;
Debug.Assert(RegisterTools.NBits(reg1) == RegisterTools.NBits(reg2));
BitVecExpr address1 = Tools.Calc_Effective_Address("qword ptr[rax]", state.HeadKey, tools, ctx);
BitVecExpr address2 = Tools.Calc_Effective_Address("qword ptr[rbx]", state.HeadKey, tools, ctx);
BitVecExpr value1 = state.Create_Mem(address1, nBytes);
BitVecExpr value2 = state.Create_Mem(address2, nBytes);
Assert.AreNotEqual(value1, value2); // value1 is not equal to value2 simply because rax and rbx are not related yet
state.Add(new BranchInfo(state.Ctx.MkEq(state.Create(Rn.RAX), state.Create(Rn.RBX)), true));
// value1 and value2 are now (intuitively) equal; however, the retrieved memory values have not been updated yet to reflect this.
using (StateUpdate updateState = new StateUpdate(state.HeadKey, Tools.CreateKey(tools.Rand), tools))
{
updateState.Set(reg1, value1);
updateState.Set(reg2, value2);
state.Update_Forward(updateState);
}
if (LogToDisplay)
{
Console.WriteLine("value1 = " + value1);
Console.WriteLine("value2 = " + value2);
Console.WriteLine(reg1 + " = " + state.Create(reg1));
Console.WriteLine(reg2 + " = " + state.Create(reg2));
Console.WriteLine(state);
}
AsmTestTools.AreEqual(Tv.ONE, state.EqualValues(reg1, reg2));
}
public static bool isMmxRegister(Rn rn)
{
switch (rn)
{
case Rn.MM0:
case Rn.MM1:
case Rn.MM2:
case Rn.MM3:
case Rn.MM4:
case Rn.MM5:
case Rn.MM6:
case Rn.MM7: return(true);
default: return(false);
}
}
