public static RegisterFile Lpm(RegisterFile registerFile, byte d, AvrSim.Flash programMemory, object[] arguments)
{
var postIncrement = (bool)arguments[0];
var word = (uint)(registerFile.GetWide(Core.R_Z) >> 1);
var MSB = (registerFile.GetWide(Core.R_Z) & 1) != 0;
var data = programMemory.GetInstruction(word);
byte value;
if (MSB)
{
value = (byte)(data >> 8);
}
else
{
value = (byte)(data & 0xff);
}
registerFile = registerFile.WithRegister(d, value);
if (postIncrement)
{
registerFile = registerFile.WithWide(Core.R_Z, z => (ushort)(z + 1));
}
return(registerFile);
}
public void TestMethod21()
{
// testing cmp_i
RegisterFile <Vector4> vRF = new RegisterFile <Vector4>(32);
RegisterFile <Scalar> sRF = new RegisterFile <Scalar>(33);
Memory m = new Memory(5000);
Memory m_ic = new Memory(5000);
IntersectionCore ic = new IntersectionCore(m_ic);
cmp_i c = new cmp_i(1, 2);
sRF[1] = 1;
sRF[2] = 1;
c.Process(vRF, sRF, m, ic);
Assert.AreEqual <int>(0, sRF[32].i);
sRF[1] = 1;
sRF[2] = 2;
c.Process(vRF, sRF, m, ic);
Assert.AreEqual <int>(1, sRF[32].i);
sRF[1] = 2;
sRF[2] = 1;
c.Process(vRF, sRF, m, ic);
Assert.AreEqual <int>(2, sRF[32].i);
}
public void TestMethod20()
{
// testing cmp_v
RegisterFile <Vector4> vRF = new RegisterFile <Vector4>(32);
RegisterFile <Scalar> sRF = new RegisterFile <Scalar>(33);
Memory m = new Memory(5000);
Memory m_ic = new Memory(5000);
IntersectionCore ic = new IntersectionCore(m_ic);
vRF[1] = new Vector4(1, 2, 3, 4);
vRF[2] = new Vector4(1, 2, 3, 5);
cmp_v c = new cmp_v(1, 2);
c.Process(vRF, sRF, m, ic);
Assert.AreEqual <int>(3, sRF[32].i);
vRF[2] = new Vector4(1, 2, 3, 4);
c.Process(vRF, sRF, m, ic);
Assert.AreEqual <int>(0, sRF[32].i);
}
internal override void Process(RegisterFile <int> RF, Memory mem)
{
if (RF[rd] != 0)
{
RF[15] = RF[15] + imm;
}
}
public void TestMethod28()
{
// testing bge_rt
RegisterFile <Vector4> vRF = new RegisterFile <Vector4>(32);
RegisterFile <Scalar> sRF = new RegisterFile <Scalar>(33);
Memory m = new Memory(5000);
Memory m_ic = new Memory(5000);
IntersectionCore ic = new IntersectionCore(m_ic);
cmp_f c = new cmp_f(1, 2);
bge_rt b = new bge_rt(5);
sRF[1] = (float)1.5;
sRF[2] = (float)1.5;
c.Process(vRF, sRF, m, ic);
b.Process(vRF, sRF, m, ic);
Assert.AreEqual <int>(5, sRF[31].i);
sRF[1] = (float)2;
sRF[2] = (float)1;
c.Process(vRF, sRF, m, ic);
b.Process(vRF, sRF, m, ic);
Assert.AreEqual <int>(10, sRF[31].i);
}
public void TestMethod30()
{
// testing jmp_link and ret
RegisterFile <Vector4> vRF = new RegisterFile <Vector4>(32);
RegisterFile <Scalar> sRF = new RegisterFile <Scalar>(33);
Memory m = new Memory(5000);
Memory m_ic = new Memory(5000);
IntersectionCore ic = new IntersectionCore(m_ic);
jmp_link j = new jmp_link(10);
sRF[31] = 1;
j.Process(vRF, sRF, m, ic);
Assert.AreEqual <int>(1, sRF[30].i);
Assert.AreEqual <int>(11, sRF[31].i);
ret r = new ret();
r.Process(vRF, sRF, m, ic);
Assert.AreEqual <int>(1, sRF[31]);
}
public static RegisterFile Out(RegisterFile registerFile, byte A, byte r, MemoryBus memoryBus)
{
// I/O Addresses are offset 0x20 on the memory bus.
memoryBus.Store((ushort)(A + 0x20), registerFile[r]);
return(registerFile);
}
/// <summary>
/// Constructor.
/// </summary>
/// <param name="reg">The register file to display.</param>
/// <param name="isSpecial">True if the register file is the special registers.</param>
public RegisterForm(RegisterFile reg, bool isSpecial)
{
InitializeComponent();
this.Text = reg.Name;
this.mReg = reg;
this.mIsSpecial = isSpecial;
this.mShadow = new uint[16];
//Add an entry for all WRAMP registers
for (uint i = 0; i <= 0xf; i++)
{
RegisterFile.GpRegister greg = (RegisterFile.GpRegister)i;
RegisterFile.SpRegister sreg = (RegisterFile.SpRegister)i;
uint v;
string name;
if (mIsSpecial)
{
v = mReg[(RegisterFile.SpRegister)i];
name = mSpRegNames[i];
}
else
{
v = mReg[(RegisterFile.GpRegister)i];
name = mGpRegNames[i];
}
listView1.Items.Add(new ListViewItem(new string[] { name, v.ToString(), v.ToString("X8"), Convert.ToString(v, 2).PadLeft(32, '0') }));
}
updateTimer.Start();
}
public static RegisterFile Std(RegisterFile registerFile, byte r, byte q, MemoryBus memoryBus, object[] arguments)
{
var register = (byte)arguments[0];
memoryBus.Store((ushort)(registerFile.GetWide(register) + q), registerFile[r]);
return(registerFile);
}
internal override void Process(RegisterFile <int> RF, Memory mem)
{
if (RF[rd] == 0)
{
RF[15] = imm; // 17th reg of a reg file representing the CP PC
// In the hardware, the PC will not actually
// be in the main reg file
}
}
public static RegisterFile Cpse(RegisterFile registerFile, byte r, byte d)
{
if (registerFile[r] == registerFile[d])
{
return(registerFile.WithProgramCounter(p => p + 1));
}
return(registerFile);
}
public static bool fCheckForRegistringFiles(bool _bForce = false)
{
try {
return(RegisterFile.fRegisterAllFileType(_bForce));
}catch (Exception Ex) {
Console.WriteLine("Error: " + Ex.Message + " : " + Ex.Source + " : " + Ex.StackTrace);
return(false);
}
}
public static RegisterFile Brne(RegisterFile registerFile, sbyte k)
{
if (!registerFile.StatusRegister.Z)
{
return(registerFile.WithProgramCounter(p => (uint)(p + k)));
}
return(registerFile);
}
public void TestMethod8()
{
// test bnz (don't take branch)
RegisterFile <int> iRF = new RegisterFile <int>(16);
Memory m = new Memory(5000);
bnz b = new bnz(2, 10);
b.Process(iRF, m);
Assert.AreEqual <int>(0, iRF[15]);
}
public void TestMethod2()
{
// test add
RegisterFile <int> iRF = new RegisterFile <int>(16);
Memory m = new Memory(5000);
addi a = new addi(0, 1, 15);
a.Process(iRF, m);
Assert.AreEqual <int>(15, iRF[0]);
}
public void TestMethod12()
{
// test ble (take branch with rd = 0)
RegisterFile <int> iRF = new RegisterFile <int>(16);
Memory m = new Memory(5000);
ble b = new ble(2, 10);
b.Process(iRF, m);
Assert.AreEqual <int>(10, iRF[15]);
}
public void TestMethod3()
{
// test sub
RegisterFile <int> iRF = new RegisterFile <int>(16);
Memory m = new Memory(5000);
subi a = new subi(0, 1, 15);
a.Process(iRF, m);
Assert.AreEqual <int>(-15, iRF[0]);
}
public void TestMethod4()
{
// test mul
RegisterFile <int> iRF = new RegisterFile <int>(16);
Memory m = new Memory(5000);
addi a = new addi(0, 1, 2);
muli mu = new muli(0, 0, 2);
a.Process(iRF, m);
mu.Process(iRF, m);
Assert.AreEqual <int>(4, iRF[0]);
}
public void TestMethod13()
{
// test ble (don't take branch with rd > 0)
RegisterFile <int> iRF = new RegisterFile <int>(16);
Memory m = new Memory(5000);
addi a = new addi(2, 0, 1);
ble b = new ble(2, 10);
a.Process(iRF, m);
b.Process(iRF, m);
Assert.AreEqual <int>(0, iRF[15]);
}
public void TestMethod7()
{
// test bnz (take branch)
RegisterFile <int> iRF = new RegisterFile <int>(16);
Memory m = new Memory(5000);
addi a = new addi(2, 0, 1);
bnz b = new bnz(2, 10);
a.Process(iRF, m);
b.Process(iRF, m);
Assert.AreEqual <int>(10, iRF[15]);
}
public static RegisterFile And(RegisterFile registerFile, byte r, byte d)
{
var R = (byte)(registerFile[d] & registerFile[r]);
var statusRegister = registerFile.StatusRegister
.WithTwosComplementOverflow(false)
.WithNegative(r.BitIsSet(7))
.WithZero(R == 0);
statusRegister = statusRegister.WithSigned(statusRegister.N & statusRegister.V);
return(registerFile.WithRegister(d, R).WithStatusRegister(statusRegister));
}
public void TestMethod15()
{
// test ld
RegisterFile <int> iRF = new RegisterFile <int>(16);
Memory m = new Memory(5000);
byte[] val = BitConverter.GetBytes(5);
m.Write(15, val);
ld l = new ld(0, 1, 15);
l.Process(iRF, m);
Assert.AreEqual(5, iRF[0]);
}
public Z48Spectrum()
{
_memory = new Z48Memory();
var registerFile = new RegisterFile();
var lookupTables = new LookupTables();
var cpuStack = new CpuStack(_memory, registerFile);
_keyboard = new Keyboard();
_video = new Video(_memory);
var outputDevice = (IOutputDevice)_video;
var inputDevice = (IInputDevice) _keyboard;
_inputOutputDevice = new Z48IO(inputDevice, outputDevice) { Keyboard = inputDevice, Video = outputDevice };
var alu = new Alu(_memory, registerFile, cpuStack, lookupTables);
var executionUnit = new ExecutionUnit(_memory, registerFile, cpuStack, alu, _inputOutputDevice, lookupTables);
_zilogZ80Cpu = new ZilogZ80Cpu(_memory, _inputOutputDevice, new CpuStack(_memory, registerFile), lookupTables, executionUnit, registerFile);
}
/// <summary>
/// Creates a new WRAMP CPU.
/// </summary>
/// <param name="addressBus">The address bus.</param>
/// <param name="dataBus">The data bus.</param>
/// <param name="irqs">The interrupt request lines (IRQs).</param>
/// <param name="cs">The chip-select lines.</param>
public SimpleWrampCpu(Bus addressBus, Bus dataBus, Bus irqs)
{
mAddressBus = addressBus;
mDataBus = dataBus;
mIrqs = irqs;
mGpRegisters = new RegisterFile("General Purpose Registers");
mSpRegisters = new RegisterFile("Special Purpose Registers");
mAlu = new ALU();
mIR = new IR();
mMPU = new MPU(mSpRegisters, mAddressBus, mDataBus);
}
public void TestMethod1()
{
// testing s_load_4byte
RegisterFile <Vector4> vRF = new RegisterFile <Vector4>(32);
RegisterFile <Scalar> sRF = new RegisterFile <Scalar>(32);
Memory m = new Memory(5000);
Memory m_ic = new Memory(5000);
IntersectionCore ic = new IntersectionCore(m_ic);
m.Write(15, BitConverter.GetBytes(2500));
s_load_4byte ld = new s_load_4byte(0, 1, 15);
ld.Process(vRF, sRF, m, ic);
Assert.AreEqual <int>(2500, sRF[0].i);
}
public void TestMethod34()
{
// Test s_sqrt
RegisterFile <Vector4> vRF = new RegisterFile <Vector4>(32);
RegisterFile <Scalar> sRF = new RegisterFile <Scalar>(32);
Memory m = new Memory(5000);
Memory m_ic = new Memory(5000);
IntersectionCore ic = new IntersectionCore(m_ic);
sRF[1] = (float)16.0;
s_sqrt sq = new s_sqrt(0, 1);
sq.Process(vRF, sRF, m, ic);
Assert.AreEqual(4.0, sRF[0].f);
}
public void TestMethod35()
{
// Test v_reduce
RegisterFile <Vector4> vRF = new RegisterFile <Vector4>(32);
RegisterFile <Scalar> sRF = new RegisterFile <Scalar>(32);
Memory m = new Memory(5000);
Memory m_ic = new Memory(5000);
IntersectionCore ic = new IntersectionCore(m_ic);
vRF[0] = new Vector4(1, 2, 3, 4);
v_reduce vr = new v_reduce(0, 0);
vr.Process(vRF, sRF, m, ic);
Assert.AreEqual(10, sRF[0].f);
}
public void TestMethod5()
{
// testing s_get_from_v
RegisterFile <Vector4> vRF = new RegisterFile <Vector4>(32);
RegisterFile <Scalar> sRF = new RegisterFile <Scalar>(32);
Memory m = new Memory(5000);
Memory m_ic = new Memory(5000);
IntersectionCore ic = new IntersectionCore(m_ic);
vRF[0] = new Vector4(5, 6, 7, 8);
s_get_from_v g = new s_get_from_v(0, 0, 1);
g.Process(vRF, sRF, m, ic);
Assert.AreEqual <int>(6, sRF[0].i);
}
public void TestMethod3()
{
// testing s_write_high
RegisterFile <Vector4> vRF = new RegisterFile <Vector4>(32);
RegisterFile <Scalar> sRF = new RegisterFile <Scalar>(32);
Memory m = new Memory(5000);
Memory m_ic = new Memory(5000);
IntersectionCore ic = new IntersectionCore(m_ic);
s_write_high swh = new s_write_high(0, 43724);
swh.Process(vRF, sRF, m, ic);
Assert.AreEqual <int>(-1429471232, sRF[0].i);
}
public void TestMethod4()
{
// testing s_write_low
RegisterFile <Vector4> vRF = new RegisterFile <Vector4>(32);
RegisterFile <Scalar> sRF = new RegisterFile <Scalar>(32);
Memory m = new Memory(5000);
Memory m_ic = new Memory(5000);
IntersectionCore ic = new IntersectionCore(m_ic);
s_write_low swl = new s_write_low(0, 43724);
swl.Process(vRF, sRF, m, ic);
Assert.AreEqual <int>(43724, sRF[0].i);
}
public void TestMethod29()
{
// testing real_jmp
RegisterFile <Vector4> vRF = new RegisterFile <Vector4>(32);
RegisterFile <Scalar> sRF = new RegisterFile <Scalar>(33);
Memory m = new Memory(5000);
Memory m_ic = new Memory(5000);
IntersectionCore ic = new IntersectionCore(m_ic);
real_jmp j = new real_jmp(10);
j.Process(vRF, sRF, m, ic);
Assert.AreEqual <int>(10, sRF[31].i);
}
protected virtual void ReadStatus(byte[] buffer)
{
Status = new RegisterFile();
Status.A = buffer[0];
Status.F = buffer[1];
Status.BC = (ushort)(buffer[2] | buffer[3] << 8);
Status.HL = (ushort)(buffer[4] | buffer[5] << 8);
Status.PC = (ushort)(buffer[6] | buffer[7] << 8);
Status.SP = (ushort)(buffer[8] | buffer[9] << 8);
Status.I = buffer[10];
Status.R = buffer[11];
byte12 = buffer[12];
Status.R7 = (byte)(byte12 & 0x80);
BorderColour = (byte)((byte12 >> 1) & 0x07);
BasicSamRom = (byte12 & 0x10) != 0;
DataCompressed = (byte12 & 0x20) != 0;
Status.DE = (ushort)(buffer[13] | buffer[14] << 8);
Status.RegisterBC_.Word = (ushort)(buffer[15] | buffer[16] << 8);
Status.RegisterDE_.Word = (ushort)(buffer[17] | buffer[18] << 8);
Status.RegisterHL_.Word = (ushort)(buffer[19] | buffer[20] << 8);
Status.RegisterAFAlt.High.Value = buffer[21];
Status.RegisterAFAlt.Low.Value = buffer[22];
Status.IY = (ushort)(buffer[23] | buffer[24] << 8);
Status.IX = (ushort)(buffer[25] | buffer[26] << 8);
Status.IFF1 = buffer[27] != 0;
Status.IFF2 = buffer[28] != 0;
byte29 = buffer[29];
Status.IM = (byte)(byte29 & 0x03);
}
