public static void EnableRxFramerPrbs([Values(Mykonos.MYK_PRBS_ORDER.PRBS7, Mykonos.MYK_PRBS_ORDER.PRBS15, Mykonos.MYK_PRBS_ORDER.PRBS31)] Mykonos.MYK_PRBS_ORDER prbsorder)
{
AdiCommandServerClient Link = AdiCommandServerClient.Instance;
Link.hw.Connect(TestSetupConfig.ipAddr, TestSetupConfig.port);
//reset the device
Link.Mykonos.resetDevice();
System.Threading.Thread.Sleep(100);
//setting SPI channel for 4-wire mode
Link.setSpiChannel(1);
Link.spiWrite(0x000, 0x18);
Link.Mykonos.enableRxFramerPrbs(prbsorder, 1);
byte PRBSspi = Link.spiRead(0x72);
if (prbsorder == Mykonos.MYK_PRBS_ORDER.PRBS7)
{
Assert.AreEqual(PRBSspi, 0x01, "PRBS7 mismatch");
}
else if (prbsorder == Mykonos.MYK_PRBS_ORDER.PRBS15)
{
Assert.AreEqual(PRBSspi, 0x03, "PRBS15 mismatch");
}
else
{
Assert.AreEqual(PRBSspi, 0x05, "PRBS31 mismatch");
}
Link.Disconnect();
}
public static void EnableDeframerPrbsChecker([Values(Mykonos.MYK_PRBS_ORDER.PRBS7, Mykonos.MYK_PRBS_ORDER.PRBS15, Mykonos.MYK_PRBS_ORDER.PRBS31)] Mykonos.MYK_PRBS_ORDER prbsorder)
{
AdiCommandServerClient Link = AdiCommandServerClient.Instance;
Link.hw.Connect(TestSetupConfig.ipAddr, TestSetupConfig.port);
//setting SPI channel for 4-wire mode
Link.setSpiChannel(1);
Link.spiWrite(0x000, 0x18);
Link.Mykonos.enableDeframerPrbsChecker(0xF, prbsorder, 1);
byte PRBSspi = Link.spiRead(0xA5);
if (prbsorder == Mykonos.MYK_PRBS_ORDER.PRBS7)
{
Assert.AreEqual(PRBSspi, 0xF1, "PRBS7 mismatch");
}
else if (prbsorder == Mykonos.MYK_PRBS_ORDER.PRBS15)
{
Assert.AreEqual(PRBSspi, 0xF3, "PRBS15 mismatch");
}
else
{
Assert.AreEqual(PRBSspi, 0xF5, "PRBS31 mismatch");
}
Link.Disconnect();
}
public static void TxDeFramerRunPrbsErrorCheck([Values(Mykonos.MYK_PRBS_ORDER.PRBS7, Mykonos.MYK_PRBS_ORDER.PRBS15, Mykonos.MYK_PRBS_ORDER.PRBS31)] Mykonos.MYK_PRBS_ORDER PrbsOrder)
{
AdiCommandServerClient Link = AdiCommandServerClient.Instance;
Link.hw.Connect(TestSetupConfig.ipAddr, TestSetupConfig.port);
UInt32 fpgaData = 0;
byte mykData = 0;
mykData = Link.spiRead(0x78); Console.WriteLine("SPI Reg x78 = " + mykData.ToString("X"));
//Initialise System and JESD Links
TestSetup.PrbsRxTestSetupInit(settings);
Link.hw.Connect(TestSetupConfig.ipAddr, TestSetupConfig.port);
fpgaData = Link.fpgaRead(0x410);
Console.WriteLine("FPGA Reg x410: REFCLK Frequency Detect = 0x" + fpgaData.ToString("X") + " = " + fpgaData.ToString());
fpgaData = Link.fpgaRead(0x10);
Console.WriteLine("FPGA Version x10:" + fpgaData.ToString("X"));
//Enable PRBS Generator on FPGA
//GTX PRBS Config FPGA 0x404[10:8]
//Then Enable PRBS Error Checker on Tx Deframer
fpgaData = Link.fpgaRead(0x404);
switch (PrbsOrder)
{
case Mykonos.MYK_PRBS_ORDER.PRBS7:
fpgaData |= 0x100;
break;
case Mykonos.MYK_PRBS_ORDER.PRBS15:
fpgaData |= 0x200;
break;
case Mykonos.MYK_PRBS_ORDER.PRBS31:
fpgaData |= 0x400;
break;
default:
Assert.Fail("Invalid PRBS Order");
break;
}
Link.fpgaWrite(0x404, fpgaData);
Link.Mykonos.enableDeframerPrbsChecker(0xF, PrbsOrder, 1);
Link.Mykonos.clearDeframerPrbsCounters();
//Let PRBS Run
uint [] LaneError = { 0xFF, 0xFF, 0xFF, 0xFF };
System.Threading.Thread.Sleep(5000);
for (byte i = 0; i < 4; i++)
{
Link.Mykonos.ReadDeframerPrbsCounters(i, ref LaneError[i]);
Assert.AreEqual(0x0, LaneError[i]);
LaneError[i] = 0x0;
}
//Enable Error Injection of FPGA PRBS Generator
fpgaData = Link.fpgaRead(0x404);
Link.fpgaWrite(0x404, (fpgaData | 0x800));
//Let PRBS Run
System.Threading.Thread.Sleep(5000);
for (byte i = 0; i < 4; i++)
{
Link.Mykonos.ReadDeframerPrbsCounters(i, ref LaneError[i]);
Assert.GreaterOrEqual(LaneError[i], 0x1);
}
//Check ClearDeframerPrbsCounters Clears Injected Errors
Link.Mykonos.clearDeframerPrbsCounters();
for (byte i = 0; i < 4; i++)
{
Link.Mykonos.ReadDeframerPrbsCounters(i, ref LaneError[i]);
Assert.AreEqual(0x0, LaneError[i]);
LaneError[i] = 0x0;
}
Link.Mykonos.enableDeframerPrbsChecker(0xF, PrbsOrder, 0);
Link.Disconnect();
}
public static void ObsFramerInjectPrbsErrorCheck([Values(Mykonos.MYK_PRBS_ORDER.PRBS7, Mykonos.MYK_PRBS_ORDER.PRBS15, Mykonos.MYK_PRBS_ORDER.PRBS31)] Mykonos.MYK_PRBS_ORDER PrbsOrder)
{
AdiCommandServerClient Link = AdiCommandServerClient.Instance;
Link.hw.Connect(TestSetupConfig.ipAddr, TestSetupConfig.port);
UInt32 fpgaData = 0;
byte mykData = 0;
UInt32 FpgaLane2ErrCnt = 0;
UInt32 FpgaLane3ErrCnt = 0;
mykData = Link.spiRead(0x78); Console.WriteLine("SPI Reg x78 = " + mykData.ToString("X"));
//Initialise System and JESD Links
TestSetup.PrbsORxTestSetupInit(settings);
Link.hw.Connect(TestSetupConfig.ipAddr, TestSetupConfig.port);
fpgaData = Link.fpgaRead(0x410); Console.WriteLine("FPGA Reg x410: REFCLK Frequency Detect = 0x" + fpgaData.ToString("X") + " = " + fpgaData.ToString());
fpgaData = Link.fpgaRead(0x10); Console.WriteLine("FPGA Version x10:" + fpgaData.ToString("X"));
//Enable PRBS Test Mode ON Mykonos and FPGA
//Clear counters
//Then Check error count is 0 following some delay
Link.Mykonos.enableRxFramerPrbs(PrbsOrder, 1);
fpgaData = Link.fpgaRead(0x404);
switch (PrbsOrder)
{
case Mykonos.MYK_PRBS_ORDER.PRBS7:
fpgaData |= 0x1;
break;
case Mykonos.MYK_PRBS_ORDER.PRBS15:
fpgaData |= 0x2;
break;
case Mykonos.MYK_PRBS_ORDER.PRBS31:
fpgaData |= 0x4;
break;
default:
Assert.Fail("Invalid PRBS Order");
break;
}
//GTX PRBS Check Counter + GTX PRBS Config
Link.fpgaWrite(0x404, fpgaData | 0x18);
//Disable PRBS Error Counter Reset
fpgaData = Link.fpgaRead(0x404);
Link.fpgaWrite(0x404, (fpgaData & 0xFFFFFFF7));
fpgaData = Link.fpgaRead(0x404);
Console.WriteLine("FPGA Reg 0x404 = " + fpgaData.ToString("X"));
//Read Counters for Lane 0 & 1
fpgaData = Link.fpgaRead(0x420);
Console.WriteLine("FPGA Reg 0x420 = " + fpgaData.ToString("X"));
//Check Reset Was Successful
Assert.AreEqual(fpgaData, 0x0);
//Let PRBS Checker Run
System.Threading.Thread.Sleep(5000);
fpgaData = Link.fpgaRead(0x420);
FpgaLane2ErrCnt = fpgaData & 0xFFFF;
FpgaLane3ErrCnt = fpgaData >> 16;
Console.WriteLine("FPGA Lane 2 Error = " + FpgaLane2ErrCnt.ToString("X"));
Console.WriteLine("FPGA Lane 3 Error = " + FpgaLane3ErrCnt.ToString("X"));
Assert.Less(FpgaLane2ErrCnt, 0x1);
Assert.Less(FpgaLane3ErrCnt, 0x1);
//Start Injecting Prbs Errors
//Then Check FPGA error count
Link.Mykonos.rxInjectPrbsError();
System.Threading.Thread.Sleep(1000);
fpgaData = Link.fpgaRead(0x420);
FpgaLane2ErrCnt = fpgaData & 0xFFFF;
FpgaLane3ErrCnt = fpgaData >> 16;
Console.WriteLine("FPGA Lane 2 Error = " + FpgaLane2ErrCnt.ToString("X"));
Console.WriteLine("FPGA Lane 3 Error = " + FpgaLane3ErrCnt.ToString("X"));
Assert.LessOrEqual(FpgaLane2ErrCnt + FpgaLane3ErrCnt, 0xA);
Assert.GreaterOrEqual(FpgaLane2ErrCnt + FpgaLane3ErrCnt, 0x1);
Link.Disconnect();
}