private IContainerIO GetModuleContainer(Span <string> modulePath, bool isVerilogVCD)
{
IContainerIO rootContainer = MainModule;
IContainerIO moduleIO = null;
if (rootContainer.TryGetIO(modulePath, out moduleIO))
{
return(moduleIO);
}
if (!(!isVerilogVCD && (modulePath[^ 1].EndsWith("_w") || modulePath[^ 1].EndsWith("_r"))))
private bool TryFindIO(string ioName, IContainerIO container, bool isVerilogVCD, out IContainerIO foundIO)
{
string remainingName = ioName;
string searchName = remainingName;
while (true)
{
if (container.TryGetIO(searchName, out foundIO))
{
container = foundIO;
//Remove found name from what still needs to be found
remainingName = remainingName.Substring(searchName.Length);
//Also remove _ from the name as firrtl uses it as an io name
//separator
if (remainingName.Length > 0)
{
remainingName = remainingName.Substring(1);
}
if (remainingName.Length == 0)
{
return(true);
}
//Verilog represents memport names in a wierd way in the vcd
//which is why that case has to be specially handled
if (isVerilogVCD && container is MemoryIO memory && memory.GetDataType() is AggregateIO)
{
if (TryFindVerilogMemPort(remainingName, memory, out foundIO))
{
return(true);
}
foundIO = null;
return(false);
}
if (container is ScalarIO)
{
foundIO = null;
return(false);
}
if (container is DuplexIO duplex)
{
if (remainingName.EndsWith("/in"))
{
container = duplex.GetInput();
remainingName = remainingName.Substring(0, remainingName.Length - "/in".Length);
}
else
{
container = duplex.GetOutput();
}
}
searchName = remainingName;
}
else
{
int _index = searchName.LastIndexOf('_');
if (_index == -1)
{
foundIO = null;
return(false);
}
searchName = searchName.Substring(0, _index);
}
}
}