private void InitLUTRouting()
{
m_grdViewLUTRouting.Rows.Clear();
// LUT routing requires wire lists
if (FPGA.FPGA.Instance.WireListCount == 0)
{
return;
}
if (IdentifierManager.Instance.IsMatch(m_tile.Location, IdentifierManager.RegexTypes.CLB))
{
Regex filter1 = null;
Regex filter2 = null;
Regex filter3 = null;
Regex filter4 = null;
bool filter1Valid = false;
bool filter2Valid = false;
bool filter3Valid = false;
bool filter4Valid = false;
GetFilter(m_txtLRLutOutFilter.Text, out filter1, out filter1Valid);
GetFilter(m_txtLREndFilter.Text, out filter2, out filter2Valid);
GetFilter(m_txtLRBegFilter.Text, out filter3, out filter3Valid);
GetFilter(m_txtLRLUTInFilter.Text, out filter4, out filter4Valid);
if (!filter1Valid || !filter2Valid || !filter3Valid || !filter4Valid)
{
return;
}
foreach (LUTRoutingInfo info in FPGATypes.GetLUTRouting(m_tile))
{
string port1 = info.Port1 != null ? info.Port1.Name : "";
string port2 = info.Port2 != null ? info.Port2.Name : "";
string port3 = info.Port3 != null ? info.Port3.Name : "";
string port4 = info.Port4 != null ? info.Port4.Name : "";
if (filter1.IsMatch(port1) && filter2.IsMatch(port2) && filter3.IsMatch(port3) && filter4.IsMatch(port4))
{
m_grdViewLUTRouting.Rows.Add(port1, port2, port3, port4);
}
}
}
}