Exemplo n.º 1
0
        protected override void DoCommandAction()
        {
            FPGATypes.InterfaceDirection dir = (FPGATypes.InterfaceDirection)Enum.Parse(typeof(FPGATypes.InterfaceDirection), SignalDirection);

            Signal s = new Signal(SignalName, SignalMode, dir, PartialRegion, Column);

            Objects.InterfaceManager.Instance.Add(s);
        }
Exemplo n.º 2
0
 /// <summary>
 /// Parse SignalEntry members from atoms which must contain 7 entries
 /// </summary>
 /// <param name="atoms"></param>
 public Signal(string signalName, string signalMode, FPGATypes.InterfaceDirection signalDirection, string partialRegion, int column)
 {
     m_signalName      = signalName;
     m_signalMode      = signalMode;
     m_signalDirection = signalDirection;
     m_partialRegion   = partialRegion;
     m_column          = column;
 }
        private void AddSignal(string subSignal)
        {
            string[] atoms = subSignal.Split(',');
            FPGATypes.InterfaceDirection dir = (FPGATypes.InterfaceDirection)Enum.Parse(typeof(FPGATypes.InterfaceDirection), atoms[2]);

            Signal s = new Signal(atoms[0], atoms[1], dir, PartialArea, int.Parse(atoms[3]));

            Objects.InterfaceManager.Instance.Add(s);
        }
        protected override void DoCommandAction()
        {
            Signal signalToMidify = Objects.InterfaceManager.Instance.GetSignal(CurrentSignalName);

            FPGATypes.InterfaceDirection dir = (FPGATypes.InterfaceDirection)Enum.Parse(typeof(FPGATypes.InterfaceDirection), NewSignaDirection);

            signalToMidify.SignalName      = NewSignalName;
            signalToMidify.SignalMode      = NewSignalMode;
            signalToMidify.SignalDirection = dir;
            signalToMidify.PartialRegion   = PartialRegion;
            signalToMidify.Column          = Columns;
        }
Exemplo n.º 5
0
        private List <Command> GetTunnelCommands(FPGATypes.InterfaceDirection direction, List <Command> placementCommands)
        {
            List <Command> result = new List <Command>();

            // TODO make parameter?
            foreach (Command placeCmd in placementCommands.Where(c => c is AddSingleInstantiationByTile))
            {
                AddSingleInstantiationByTile addCmd = (AddSingleInstantiationByTile)placeCmd;
                Tile clb          = FPGA.FPGA.Instance.GetTile(addCmd.AnchorLocation);
                Tile interconnect = FPGATypes.GetInterconnectTile(clb);

                ExcludePortsFromBlockingOnTileByRegexp exclude = new ExcludePortsFromBlockingOnTileByRegexp();
                exclude.CheckForExistence = false;
                exclude.IncludeAllPorts   = false;
                exclude.Location          = interconnect.Location;

                if (BuildTarget == Target.Static && direction == FPGATypes.InterfaceDirection.East)
                {
                    exclude.PortNameRegexp = "(WW2E[0|1|2|3])|(EE2B[0|1|2|3])";
                }
                else if (BuildTarget == Target.Static && direction == FPGATypes.InterfaceDirection.West)
                {
                    exclude.PortNameRegexp = "(EE2E[0|1|2|3])|(WW2B[0|1|2|3])";
                }
                else if (BuildTarget == Target.Module && direction == FPGATypes.InterfaceDirection.East)
                {
                    exclude.PortNameRegexp = "(EE2E[0|1|2|3])|(WW2B[0|1|2|3])";
                }
                else if (BuildTarget == Target.Module && direction == FPGATypes.InterfaceDirection.West)
                {
                    exclude.PortNameRegexp = "(WW2E[0|1|2|3])|(EE2B[0|1|2|3])";
                }
                else
                {
                    throw new ArgumentException("Direction " + direction + " not implemented");
                }
                //exclude.PortNameRegexp = "((EE)|(WW))2(B|E)[0|1|2|3]"; // the epxression parser cant handle [0-3]

                if (result.Count == 0)
                {
                    exclude.Comment = " exclude tunnel wires from blocking";
                }

                result.Add(exclude);
            }
            return(result);
        }
        protected override void DoCommandAction()
        {
            FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);

            DesignParser parser    = DesignParser.CreateDesignParser(XDLFile);
            XDLContainer container = new XDLContainer();

            parser.ParseDesign(container, this);

            VHDLParser       moduleParser = new VHDLParser(VHDLModule);
            VHDLParserEntity ent          = moduleParser.GetEntity(0);

            Dictionary <int, List <Signal> > east = new Dictionary <int, List <Signal> >();
            Dictionary <int, List <Signal> > west = new Dictionary <int, List <Signal> >();

            double xCenter, yCenter;

            TileSelectionManager.Instance.GetCenterOfSelection(t => TileSelectionManager.Instance.IsSelected(t.TileKey), out xCenter, out yCenter);

            foreach (HDLEntitySignal signal in ent.InterfaceSignals)
            {
                foreach (XDLNet net in container.Nets.Where(n => n.Name.StartsWith(signal.SignalName) && ((XDLNet)n).HasIndex()).OrderBy(n => ((XDLNet)n).GetIndex()))
                {
                    Tile fromTile;
                    Tile toTile;
                    GetSourceAndSink(container, net, out fromTile, out toTile);

                    GetSourceAndSink(container, net, out fromTile, out toTile);

                    Tile   innerTile  = null;
                    Tile   outerTile  = null;
                    string signalMode = "";
                    if (!TileSelectionManager.Instance.IsSelected(fromTile.TileKey) && TileSelectionManager.Instance.IsSelected(toTile.TileKey))
                    {
                        innerTile  = toTile;
                        outerTile  = fromTile;
                        signalMode = "in";
                    }
                    else if (TileSelectionManager.Instance.IsSelected(fromTile.TileKey) && !TileSelectionManager.Instance.IsSelected(toTile.TileKey))
                    {
                        outerTile  = toTile;
                        innerTile  = fromTile;
                        signalMode = "out";
                    }
                    else
                    {
                        throw new ArgumentException("Expecting an instance inside the current selection");
                    }

                    FPGATypes.InterfaceDirection dir = outerTile.TileKey.X < (int)xCenter ? FPGATypes.InterfaceDirection.East : FPGATypes.InterfaceDirection.West;

                    Dictionary <int, List <Signal> > signalCollection = dir.Equals(FPGATypes.InterfaceDirection.East) ? east : west;
                    if (!signalCollection.ContainsKey(innerTile.TileKey.Y))
                    {
                        signalCollection.Add(innerTile.TileKey.Y, new List <Signal>());
                    }

                    Signal s = new Signal();
                    s.Column          = -1;
                    s.SignalDirection = dir;
                    s.SignalMode      = signalMode;
                    s.SignalName      = net.Name;

                    signalCollection[innerTile.TileKey.Y].Add(s);

                    // weiter: vor verlaesst das gummiband die partielle flaeche?
                    // vektoren nach osten oder westen?
                }
            }


            bool interleaveEast = east.Any(t => t.Value.Count > 4);
            bool interleaveWest = west.Any(t => t.Value.Count > 4);

            Dictionary <FPGA.FPGATypes.Direction, Dictionary <int, List <Signal> > > interfaces = new Dictionary <FPGATypes.Direction, Dictionary <int, List <Signal> > >();

            interfaces.Add(FPGATypes.Direction.East, new Dictionary <int, List <Signal> >());
            interfaces[FPGATypes.Direction.East][0] = new List <Signal>();
            interfaces[FPGATypes.Direction.East][1] = new List <Signal>();
            interfaces.Add(FPGATypes.Direction.West, new Dictionary <int, List <Signal> >());
            interfaces[FPGATypes.Direction.West][0] = new List <Signal>();
            interfaces[FPGATypes.Direction.West][1] = new List <Signal>();


            if (interleaveEast)
            {
                int columnIndex = 0;
                foreach (KeyValuePair <int, List <Signal> > tupel in east)
                {
                    foreach (Signal s in tupel.Value)
                    {
                        Signal copy = new Signal(s.SignalName, s.SignalMode, s.SignalDirection, "", columnIndex);
                        interfaces[FPGATypes.Direction.East][columnIndex].Add(copy);

                        columnIndex++;
                        columnIndex %= 2;
                    }
                }
            }

            //ent.InterfaceSignals
        }