// WriteEnable signals on rxd and txd lines are not required, so
// native types cannot be used, so special types were introduced
public static async Task Aggregator(FPGA.InputSignal <bool> RXD, FPGA.OutputSignal <bool> TXD)
{
const uint buffSize = 100;
const uint period = 1000;
// declare circular memory buffer for incoming data
byte[] buff = new byte[100];
byte readAddr = 0, writeAddr = 0;
object guard = new object();
// trigger signal, indicates that there is something in the buffer
Func <bool> hasData = () => writeAddr != readAddr;
// this is infinite receiving handler, stores all stuff in buffer
Action receiverHandler = () =>
{
byte data = 0;
while (true)
{
Drivers.UART.Read(RXD, out data);
lock (guard)
{
buff[writeAddr] = data;
writeAddr++;
// normally, remainder operation should be used,
// but it takes a lot of FPGA resources
if (writeAddr >= buffSize)
{
writeAddr = 0;
}
}
}
};
// handler kicks in when there is something in the buffer
Action transmitterHandler = () =>
{
byte data = 0;
lock (guard)
{
data = buff[readAddr];
readAddr++;
// normally, remainder operation should be used,
// but it takes a lot of FPGA resources
if (readAddr >= buffSize)
{
readAddr = 0;
}
}
Drivers.UART.Write(data, TXD);
};
// hack, no OnStartup event on the board yet, coming soon
// just start handler on timer event
FPGA.Config.OnTimer(period, receiverHandler);
// Trigger transmitter handler when data is in the buffer
FPGA.Config.OnSignal(hasData, transmitterHandler);
}
public static async Task Aggregator(
FPGA.InputSignal <bool> RXD,
FPGA.OutputSignal <bool> TXD
)
{
Sequential handler = () =>
{
FPU.FPUScopeNoSync();
while (true)
{
FPGA.Optimizations.AddOptimizer <DefaultOptimizer>();
const uint baud = 115200;
UART.ReadFloat(baud, RXD, out float mass);
UART.ReadFloat(baud, RXD, out float radius);
var vOrbit = FPGAOrbitalCalc.TOrbit(mass, radius);
UART.WriteFloat(baud, vOrbit, TXD);
}
};
FPGA.Config.OnStartup(handler);
}
public static async Task Aggregator(
FPGA.InputSignal <bool> RXD,
FPGA.OutputSignal <bool> TXD
)
{
DTOs.IsPrimeRequest request = new DTOs.IsPrimeRequest();
FPGA.Signal <bool> deserialized = new FPGA.Signal <bool>();
Drivers.JSON.DeserializeFromUART <DTOs.IsPrimeRequest>(request, RXD, deserialized);
Action handler = () =>
{
bool result = false;
uint source = request.value;
// TODO: member access is not supported in function call
SequentialMath.Calculators.IsPrime((uint)source, out result);
DTOs.IsPrimeResponse response = new DTOs.IsPrimeResponse();
response.value = request.value;
response.result = (byte)((result == true) ? 1 : 0);
Drivers.JSON.SerializeToUART <DTOs.IsPrimeResponse>(response, TXD);
};
FPGA.Config.OnSignal(deserialized, handler);
}
// module has one non-registered input bit, and one registered output byte
public static byte Read(uint baud, FPGA.InputSignal <bool> RXD)
{
FPGA.Const <ulong> delay = 1000000000 / baud;
byte result = 0;
// all combinational logic is expressed as delegates
Func <bool> invertedRXD = () => !RXD;
// wait for start bit
FPGA.Runtime.WaitForAllConditions(invertedRXD);
// wait for half bit time to allow some time shift errors
FPGA.Runtime.Delay(delay / 2);
// read 8 bits
for (uint i = 0; i < 8; i++)
{
FPGA.Config.SetInclusiveRange(0, 8, i);
FPGA.Runtime.Delay(delay);
// this is assign of combinational expression
// evaluated and assigned during single clock cycle
result = (byte)((result >> 1) | ((byte)RXD << 7));
}
// stop bit
FPGA.Runtime.Delay(delay);
return(result);
}
public static void ReadFloat(uint baud, FPGA.InputSignal <bool> RXD, out float data)
{
uint uns = 0;
UART.ReadUnsigned32(baud, RXD, ref uns);
FPGA.Runtime.Assign(FPGA.Expressions.Unchecked(uns, out data));
}
public static async Task Aggregator(
FPGA.InputSignal <bool> RXD,
FPGA.OutputSignal <bool> TXD
)
{
Action mainHandler = () =>
{
byte data = 0;
byte[] buff = new byte[1000];
for (int i = 0; i < 1000; i++)
{
Drivers.UART.Read(RXD, out data);
buff[i] = data;
}
byte sum = 0;
for (int i = 0; i < 1000; i++)
{
data = buff[i];
sum += data;
}
Drivers.UART.Write(sum, TXD);
};
bool trigger = true;
FPGA.Config.OnSignal(trigger, mainHandler);
}
public static async Task Aggregator(
FPGA.InputSignal <bool> RXD,
FPGA.OutputSignal <bool> TXD
)
{
byte data = 0;
FPGA.Signal <bool> completed = false;
Action dataHandler = () =>
{
Drivers.UART.Write(data, TXD);
completed = true;
};
FPGA.Config.OnRegisterWritten(data, dataHandler);
Action mainHandler = () =>
{
data = 48;
FPGA.Runtime.WaitForAllConditions(completed);
data = 49;
FPGA.Runtime.WaitForAllConditions(completed);
};
bool trigger = true;
FPGA.Config.OnSignal(trigger, mainHandler);
}
public static async Task Aggregator(
FPGA.InputSignal <bool> RXD,
FPGA.OutputSignal <bool> TXD
)
{
Action handler = () =>
{
byte data = 0;
Drivers.UART.Read(RXD, out data);
Func <byte> dFunc = () => (byte)(data * 2);
FPGA.Signal <bool> writeEnable = false;
FPGA.Register <byte> result = new FPGA.Register <byte>(0);
FPGA.Config.RegisterOverride(result, dFunc, writeEnable);
FPGA.Runtime.Assign(FPGA.Expressions.AssignSignal(true, writeEnable));
Drivers.UART.Write(result, TXD);
};
bool trigger = true;
FPGA.Config.OnSignal(trigger, handler);
}
public static async Task Aggregator(
[PassThrough]
FPGA.InputSignal <byte> InUnsigned,
[PassThrough]
FPGA.InputSignal <sbyte> InSigned,
FPGA.OutputSignal <bool> OutEqual,
FPGA.OutputSignal <bool> OutNotEqual,
FPGA.OutputSignal <bool> OutGreater,
FPGA.OutputSignal <bool> OutLess,
FPGA.OutputSignal <ushort> OutAddUnsigned,
FPGA.OutputSignal <short> OutAddSigned,
FPGA.OutputSignal <ushort> OutSubUnsigned,
FPGA.OutputSignal <short> OutSubSigned,
FPGA.OutputSignal <ushort> OutMltUnsigned,
FPGA.OutputSignal <short> OutMltSigned
)
{
// TODO direct combinational logic in non-sequential methods
OutEqual = FPGA.Config.Compare(InUnsigned, FPGA.CompareType.Equal, InSigned);
OutNotEqual = FPGA.Config.Compare(InUnsigned, FPGA.CompareType.NotEqual, InSigned);
OutGreater = FPGA.Config.Compare(InUnsigned, FPGA.CompareType.Greater, InSigned);
OutLess = FPGA.Config.Compare(InUnsigned, FPGA.CompareType.Less, InSigned);
OutAddUnsigned = (ushort)(InUnsigned + InSigned);
OutAddSigned = (short)(InUnsigned + InSigned);
OutSubUnsigned = (ushort)(InUnsigned - InSigned);
OutSubSigned = (short)(InUnsigned - InSigned);
OutMltUnsigned = (ushort)(InUnsigned * InSigned);
OutMltSigned = (short)(InUnsigned * InSigned);
}
public static async Task Aggregator(
FPGA.InputSignal <bool> RXD,
FPGA.OutputSignal <bool> TXD
)
{
Action handler = () =>
{
while (true)
{
byte start = 0;
Drivers.UART.Read(RXD, out start);
ulong result = 0;
SequentialMath.Calculators.Fibonacci(start, out result);
for (byte i = 0; i < 8; i++)
{
byte data = (byte)result;
Drivers.UART.Write(data, TXD);
result = result >> 8;
}
}
};
bool trigger = true;
FPGA.Config.OnSignal(trigger, handler);
}
// module has one non-registered input bit, and one registered output byte
public static void Read(FPGA.InputSignal <bool> RXD, out byte data)
{
// 115200, delay is expressed in nanosecods, baud rate is hardcoded for now
const uint delay = 8680;
const uint halfDelay = 4340;
byte result = 0;
// all combinational logic is expressed as delegates
Func <bool> invertedRXD = () => !RXD;
// wait for start bit
FPGA.Runtime.WaitForAllConditions(invertedRXD);
// wait for half bit time to allow some time shift errors
FPGA.Runtime.Delay(halfDelay);
// read 8 bits
for (uint i = 0; i < 8; i++)
{
FPGA.Runtime.Delay(delay);
// this is assign of combinational expression
// evaluated and assigned during single clock cycle
result = (byte)((result >> 1) | (RXD << 7));
}
// stop bit
FPGA.Runtime.Delay(delay);
// assign result and complete method call
data = result;
}
public static async Task Aggregator(
FPGA.InputSignal <bool> RXD,
FPGA.OutputSignal <bool> TXD
)
{
Sequential handler = () =>
{
FPU.FPUScopeNoSync();
while (true)
{
FPGA.Optimizations.AddOptimizer <DefaultOptimizer>();
const uint baud = 115200;
float[] buff = new float[4];
for (byte i = 0; i < 4; i++)
{
UART.ReadFloat(baud, RXD, out float tmp);
buff[i] = tmp;
}
var deltaV = FPGAOrbitalCalc.DeltaVInclinationOrbit(
buff[0],
buff[1],
buff[2],
buff[3]
);
UART.WriteFloat(baud, deltaV, TXD);
}
};
FPGA.Config.OnStartup(handler);
}
public static async Task Aggregator(
FPGA.InputSignal <bool> RXD,
FPGA.OutputSignal <bool> TXD
)
{
byte data = 0;
Action processingHandler = () =>
{
DTOs.RoundTrip response = new DTOs.RoundTrip();
response.b = data;
Drivers.JSON.SerializeToUART <DTOs.RoundTrip>(response, TXD);
};
FPGA.Config.OnRegisterWritten(data, processingHandler);
Action deserializeHandler = () =>
{
Drivers.UART.Read(RXD, out data);
};
bool trigger = true;
FPGA.Config.OnSignal(trigger, deserializeHandler);
}
public static void ReadUnsigned32(uint baud, FPGA.InputSignal <bool> RXD, ref uint data)
{
for (byte i = 0; i < 4; i++)
{
FPGA.Config.SetInclusiveRange(0, 4, i);
var part = UART.Read(baud, RXD);
data = (data >> 8) | ((uint)part << 24);
}
}
public static void ReadUnsigned64(uint baud, FPGA.InputSignal <bool> RXD, ref ulong data)
{
for (byte i = 0; i < 8; i++)
{
FPGA.Config.SetInclusiveRange(0, 8, i);
var part = UART.Read(baud, RXD);
data = (data >> 8) | ((ulong)part << 56);
}
}
public static async Task Aggregator(
FPGA.InputSignal <bool> RXD,
FPGA.OutputSignal <bool> TXD
)
{
object testLock = new object();
byte data = 0;
Action dataHandler = () =>
{
Drivers.UART.Write(data, TXD);
};
FPGA.Config.OnRegisterWritten(data, dataHandler);
Action mainHandler1 = () =>
{
lock (testLock)
{
FPGA.Runtime.Delay(TimeSpan.FromMilliseconds(5));
data = 48;
FPGA.Runtime.Delay(TimeSpan.FromMilliseconds(20));
data = 49;
FPGA.Runtime.Delay(TimeSpan.FromMilliseconds(5));
}
};
Action mainHandler2 = () =>
{
lock (testLock)
{
FPGA.Runtime.Delay(TimeSpan.FromMilliseconds(5));
data = 50;
FPGA.Runtime.Delay(TimeSpan.FromMilliseconds(20));
data = 51;
FPGA.Runtime.Delay(TimeSpan.FromMilliseconds(5));
}
};
bool trigger = true;
FPGA.Config.OnSignal(trigger, mainHandler1);
FPGA.Config.OnSignal(trigger, mainHandler2);
Action resetHandler1 = () =>
{
FPGA.Runtime.ResetSequence(mainHandler1);
};
Action resetHandler2 = () =>
{
FPGA.Runtime.ResetSequence(mainHandler2);
};
FPGA.Config.OnTimer(TimeSpan.FromMilliseconds(10), resetHandler1);
FPGA.Config.OnTimer(TimeSpan.FromMilliseconds(19), resetHandler2);
}
public static async Task Aggregator(
FPGA.InputSignal <bool> RXD,
FPGA.OutputSignal <bool> TXD
)
{
TryControllers_Blocks.Bootstrap(
RXD,
TXD,
Controllers.TryControllers_Blocks.SmokeTest);
}
public static async Task Aggregator(
FPGA.InputSignal <bool> RXD,
FPGA.OutputSignal <bool> TXD
)
{
TryControllers_Blocks.Bootstrap(
RXD,
TXD,
Controllers.TryControllers_Blocks.TryCatchAll_ReturnRethrow);
}
public static async Task Aggregator(
FPGA.InputSignal <bool> RXD,
FPGA.OutputSignal <bool> TXD
)
{
TryControllers_Blocks.Bootstrap(
RXD,
TXD,
Controllers.TryControllers_Blocks.TryCatchExplicitFinally);
}
public static void Read(
out ushort IN1Value,
out ushort IN2Value,
FPGA.OutputSignal <bool> NCS,
FPGA.OutputSignal <bool> SCLK,
FPGA.OutputSignal <bool> DIN,
FPGA.InputSignal <bool> DOUT
)
{
bool internalDIN = false, internalNCS = true, internalSCLK = true;
FPGA.Config.Link(internalDIN, DIN);
FPGA.Config.Link(internalNCS, NCS);
FPGA.Config.Link(internalSCLK, SCLK);
ushort[] buff = new ushort[2];
for (byte channel = 0; channel < 2; channel++)
{
byte controlRegister = (byte)((channel & 1) << 3);
ushort current = 0;
Func <bool> controlMSB = () => FPGA.Config.HighBit(controlRegister);
internalNCS = false;
FPGA.Runtime.Delay(TimeSpanEx.FromMicroseconds(1));
for (byte i = 0; i < 16; i++)
{
internalSCLK = false;
if (i < 8)
{
internalDIN = controlMSB();
controlRegister = (byte)(controlRegister << 1);
}
FPGA.Runtime.Delay(TimeSpanEx.FromMicroseconds(1));
if (i > 3)
{
current = (ushort)(current << 1 | (byte)DOUT);
}
internalSCLK = true;
FPGA.Runtime.Delay(TimeSpanEx.FromMicroseconds(1));
}
internalSCLK = true;
internalNCS = true;
buff[channel] = (ushort)(current << 4);
}
IN1Value = buff[0];
IN2Value = buff[1];
}
public static void ReadUnsigned32(uint baud, FPGA.InputSignal <bool> RXD, ref uint data)
{
byte part = 0;
for (byte i = 0; i < 4; i++)
{
FPGA.Config.SetInclusiveRange(0, 4, i);
UART.Read(baud, RXD, out part);
data = (uint)((data >> 8) | (part << 24));
}
}
public static async Task Test(
FPGA.InputSignal <bool> InSignal,
FPGA.OutputSignal <bool> OutSignal)
{
Action handler = () =>
{
OutSignal = true;
FPGA.Runtime.Delay(TimeSpan.FromMilliseconds(1));
OutSignal = true;
};
FPGA.Config.OnSignal(InSignal, handler);
}
public static async Task Aggregator(
FPGA.InputSignal <bool> RXD,
FPGA.OutputSignal <bool> TXD)
{
byte data = 0;
FPGA.Signal <byte> externalInput = new FPGA.Signal <byte>();
FPGA.Config.Link(data, out externalInput);
FPGA.Signal <byte> externalOutput = new FPGA.Signal <byte>();
FPGA.Signal <bool> externalTrigger = new FPGA.Signal <bool>();
FPGA.Signal <bool> externalReady = new FPGA.Signal <bool>();
Action handler = () =>
{
Drivers.UART.Read(RXD, out data);
for (byte i = 0; i < 3; i++)
{
byte result = 0;
switch (i)
{
case 0:
FPGA.Config.Entity <IConcreteExternalPackage1>().ExternalEntity(externalInput, externalOutput, externalTrigger, externalReady);
externalTrigger = true;
FPGA.Runtime.WaitForAllConditions(externalReady);
result = externalOutput;
break;
case 1:
Controllers.External_ExistingEntity.NestedLevel1 <IConcreteExternalPackage1>(data, out result);
break;
case 2:
Controllers.External_ExistingEntity.NestedLevel2 <IConcreteExternalPackage2>(40, out result);
break;
}
Drivers.UART.Write(result, TXD);
}
};
const bool trigger = true;
FPGA.Config.OnSignal(trigger, handler);
}
public static async Task Aggregator(
FPGA.InputSignal <bool> RXD,
FPGA.OutputSignal <bool> TXD
)
{
const bool trigger = true;
Action handler = () =>
{
byte data = 0;
Drivers.UART.Read(RXD, out data);
Drivers.UART.Write(data, TXD);
};
FPGA.Config.OnSignal(trigger, handler);
}
public static async Task Aggregator(
FPGA.InputSignal <bool> RXD,
FPGA.OutputSignal <bool> TXD
)
{
DTOs.RoundTrip request = new DTOs.RoundTrip();
FPGA.Signal <bool> deserialized = new FPGA.Signal <bool>();
Drivers.JSON.DeserializeFromUART <DTOs.RoundTrip>(request, RXD, deserialized);
Action processingHandler = () =>
{
Drivers.JSON.SerializeToUART <DTOs.RoundTrip>(request, TXD);
};
FPGA.Config.OnSignal(deserialized, processingHandler);
}
static void KeypadToLEDs(
FPGA.OutputSignal <bool> LED1,
FPGA.OutputSignal <bool> LED2,
FPGA.OutputSignal <bool> LED3,
FPGA.OutputSignal <bool> LED4,
FPGA.OutputSignal <bool> K7,
FPGA.OutputSignal <bool> K6,
FPGA.OutputSignal <bool> K5,
FPGA.OutputSignal <bool> K4,
FPGA.InputSignal <bool> K3,
FPGA.InputSignal <bool> K2,
FPGA.InputSignal <bool> K1,
FPGA.InputSignal <bool> K0,
FPGA.OutputSignal <bool> Bank1,
FPGA.OutputSignal <bool> Bank2,
out byte code
)
{
byte internalCode = 0;
FPGA.Config.Link(internalCode, out code);
Drivers.QuokkaBoard.OutputBank(Bank1);
Drivers.QuokkaBoard.InputBank(Bank2);
bool internalLED1 = false, internalLED2 = false, internalLED3 = false, internalLED4 = false;
FPGA.Config.Link(internalLED1, LED1);
FPGA.Config.Link(internalLED2, LED2);
FPGA.Config.Link(internalLED3, LED3);
FPGA.Config.Link(internalLED4, LED4);
Action keypadHandler = () =>
{
Drivers.Keypad4x4.ReadCode(K7, K6, K5, K4, K3, K2, K1, K0, out internalCode);
internalLED1 = (internalCode & 1) > 0;
internalLED2 = (internalCode & 2) > 0;
internalLED3 = (internalCode & 4) > 0;
internalLED4 = (internalCode & 8) > 0;
};
FPGA.Config.OnTimer(TimeSpan.FromMilliseconds(100), keypadHandler);
}
public static async Task Aggregator(
FPGA.InputSignal <bool> RXD,
FPGA.OutputSignal <bool> TXD
)
{
Action handler = () =>
{
byte data = 0;
Drivers.UART.Read(RXD, out data);
byte result = 0;
Controllers.Lock_ParallelAssign.TestMethod(data, out result);
Drivers.UART.Write(result, TXD);
};
bool trigger = true;
FPGA.Config.OnSignal(trigger, handler);
}
public static async Task Aggregator(
FPGA.InputSignal <bool> RXD,
FPGA.OutputSignal <bool> TXD
)
{
Action handler = () =>
{
byte data = 0;
Drivers.UART.Read(RXD, out data);
byte result = 0;
Controllers.Branch_Switch_For_While_IfElse_Break.TestMethod(data, out result);
Drivers.UART.Write(result, TXD);
};
bool trigger = true;
FPGA.Config.OnSignal(trigger, handler);
}
public static void Measure(FPGA.InputSignal <bool> Echo, FPGA.OutputSignal <bool> Trigger, out ushort Distance)
{
FPGA.Config.Default(out Trigger, false);
FPGA.Config.Default(out Distance, 0);
// sound does 1 cm return trip in that time
const uint measurePeriod = 58822;
object guard = new object();
ushort counter = 0;
bool internalTrigger = false;
FPGA.Config.Link(internalTrigger, Trigger);
Action measureHandler = () =>
{
if (Echo)
{
lock (guard)
{
counter = (ushort)(counter + 1);
}
}
};
FPGA.Config.OnTimer(measurePeriod, measureHandler);
lock (guard)
{
counter = 0;
}
internalTrigger = true;
// keep triger signal for 20ms
FPGA.Runtime.Delay(TimeSpan.FromMilliseconds(20));
internalTrigger = false;
// wait for 100ms to complete measurements
// this is not really good design, need to wait for echo to become high
// and then wait for echo to become low
FPGA.Runtime.Delay(TimeSpan.FromMilliseconds(100));
Distance = counter;
}
public static async Task Aggregator(
FPGA.InputSignal <bool> RXD,
FPGA.OutputSignal <bool> TXD
)
{
bool internalTXD = true;
FPGA.Config.Link(internalTXD, TXD);
Action mainHandler = () =>
{
byte data = 0;
byte[] buff = new byte[] { 0, 1, 2, 3, 4 };
for (int i = 0; i < buff.Length; i++)
{
Drivers.UART.Read(RXD, out data);
byte existing = 0;
existing = buff[i];
buff[i] = (byte)(data + existing);
}
for (int i = 0; i < buff.Length; i++)
{
data = buff[i];
Drivers.UART.Write1(data, out internalTXD);
}
byte sum = 0;
for (int i = 0; i < buff.Length; i++)
{
data = buff[i];
sum += data;
}
Drivers.UART.Write1(sum, out internalTXD);
};
bool trigger = true;
FPGA.Config.OnSignal(trigger, mainHandler);
}
