private SimulationModel ExecuteTest(Register16Table reg, bool write)
{
var ob = OpcodeByte.New(x: 1, z: 3,
q: (byte)(write ? 0: 1), p: (byte)reg);
var cpuZ80 = new CpuZ80();
var buffer = write ?
new byte[] { 0xED, ob.Value, AddressLo, AddressHi, 0, 0, 0 }:
new byte[] { 0xED, ob.Value, AddressLo, AddressHi, 0, ExpectedLo, ExpectedHi };
var model = cpuZ80.Initialize(buffer);
cpuZ80.FillRegisters();
if (write)
{
if (reg == Register16Table.SP)
{
cpuZ80.Registers.SP = Expected;
}
else
{
cpuZ80.Registers[reg] = Expected;
}
}
model.ClockGen.SquareWave(20);
Console.WriteLine(model.LogicAnalyzer.ToWaveJson());
return(model);
}
public static void AssertRegisters(this CpuZ80 cpu,
byte i = 0, byte r = 0,
UInt16 pc = 0, UInt16 sp = 0,
UInt16 ix = MagicValue, UInt16 iy = MagicValue,
byte a = MagicValue, UInt16 bc = MagicValue, UInt16 de = MagicValue, UInt16 hl = MagicValue,
byte a_a = MagicValue, UInt16 a_bc = MagicValue, UInt16 a_de = MagicValue, UInt16 a_hl = MagicValue)
{
if (pc != 0)
{
cpu.Registers.PC.Should().Be(pc, "pc");
}
if (sp != 0)
{
cpu.Registers.SP.Should().Be(sp, "sp");
}
cpu.Registers.IX.Should().Be(ix, "ix");
cpu.Registers.IY.Should().Be(iy, "iy");
if (i != 0)
{
cpu.Registers.I.Should().Be(i, "i");
}
if (r != 0)
{
cpu.Registers.R.Should().Be(r, "r");
}
cpu.Registers.A.Should().Be(a, "a");
cpu.Registers.BC.Should().Be(bc, "bc");
cpu.Registers.DE.Should().Be(de, "de");
cpu.Registers.HL.Should().Be(hl, "hl");
cpu.Registers.AlternateSet.A.Should().Be(a_a, "a'");
cpu.Registers.AlternateSet.BC.Should().Be(a_bc, "bc'");
cpu.Registers.AlternateSet.DE.Should().Be(a_de, "de'");
cpu.Registers.AlternateSet.HL.Should().Be(a_hl, "hl'");
}
private SimulationModel ExecuteTest(OpcodeByte ob, byte extension = 0)
{
var cpuZ80 = new CpuZ80();
var buffer = extension == 0 ?
new byte[] { ob.Value, 0, 0, 0, 0, 0 } :
new byte[] { extension, ob.Value, 0, 0, 0, 0 };
var model = cpuZ80.Initialize(buffer);
cpuZ80.FillRegisters(sp: Stack);
if (extension == 0xDD)
{
cpuZ80.Registers.IX = Expected;
}
else if (extension == 0xFD)
{
cpuZ80.Registers.IY = Expected;
}
else
{
cpuZ80.Registers.HL = Expected;
}
model.ClockGen.SquareWave(extension == 0 ? 19 : 23);
Console.WriteLine(model.LogicAnalyzer.ToWaveJson());
return(model);
}
public static void Clock(this CpuZ80 cpu,
CycleNames toCycle, DigitalLevel toLevel)
{
var gen = new SignalGenerator();
var clock = cpu.Clock.ConnectTo(gen.Output);
gen.SquareWave(1, toCycle, toLevel);
}
public CpuExecute(CpuZ80 cpu, bool createInstruction = true)
: base(cpu)
{
if (createInstruction)
{
CreateInstruction();
}
}
public CpuReadParameterThenExecute(CpuZ80 cpu)
: base(cpu, createInstruction: false)
{
// turn off refresh logic - not a true M1 cycle.
RefreshEnabled = false;
// read d-offset that comes before the opcode
_currentPart = new ReadT3InstructionPart(Cpu, MachineCycleNames.M1);
}
private static SimulationModel CreateModel()
{
var ob = OpcodeByte.New(x: 1, z: 6, y: 6);
var cpuZ80 = new CpuZ80();
var model = cpuZ80.Initialize(new byte[] { ob.Value });
cpuZ80.FillRegisters();
return(model);
}
public static DigitalSignalProvider Clock(this CpuZ80 cpu,
CycleNames toCycle, DigitalLevel toLevel)
{
var gen = new SignalGenerator();
var clock = cpu.Clock.CreateConnection(gen.Output);
gen.SquareWave(1, toCycle, toLevel);
return(clock);
}
public static void FillRegisters(this CpuZ80 cpu,
byte i = (byte)MagicValue, byte r = (byte)MagicValue,
UInt16 pc = 0, UInt16 sp = MagicValue,
UInt16 ix = MagicValue, UInt16 iy = MagicValue,
byte a = MagicValue, UInt16 bc = MagicValue, UInt16 de = MagicValue, UInt16 hl = MagicValue,
byte a_a = MagicValue, UInt16 a_bc = MagicValue, UInt16 a_de = MagicValue, UInt16 a_hl = MagicValue)
{
FillRegisters(cpu.Registers, i, r, pc, sp, ix, iy,
a, bc, de, hl,
a_a, a_bc, a_de, a_hl);
}
public RepeatInstructionPart(CpuZ80 cpu, MachineCycleNames activeMachineCycle, sbyte deltaPC)
: base(cpu, activeMachineCycle)
{
if (deltaPC >= 0)
{
throw new ArgumentException(
"The value must be negative.", "deltaPC");
}
_deltaPC = deltaPC;
}
public void IntDI_After2Cycles()
{
var cpu = new CpuZ80();
var interruptProvider = cpu.Interrupt.CreateConnection();
var model = cpu.Initialize(new byte[] { 0 });
model.ClockGen.SquareWave(2);
interruptProvider.Write(DigitalLevel.Low);
model.ClockGen.SquareWave(2);
cpu.Registers.Interrupt.IFF1.Should().BeFalse();
}
public void Nop()
{
var cpuZ80 = new CpuZ80();
var model = cpuZ80.Initialize(new byte[] { 0x00 });
cpuZ80.FillRegisters(pc: 0);
model.ClockGen.SquareWave(4);
Console.WriteLine(model.LogicAnalyzer.ToWaveJson());
cpuZ80.AssertRegisters(pc: 1);
}
public void ExAFAF()
{
var ob = OpcodeByte.New(x: 0, z: 0, y: 1);
var cpuZ80 = new CpuZ80();
var model = cpuZ80.Initialize(new byte[] { ob.Value });
cpuZ80.FillRegisters(a: 0x55, a_a: 0xAA);
model.ClockGen.SquareWave(4);
cpuZ80.AssertRegisters(a: 0xAA, a_a: 0x55);
}
public void ExDE_HL()
{
var ob = OpcodeByte.New(x: 3, z: 3, y: 5);
var cpuZ80 = new CpuZ80();
var model = cpuZ80.Initialize(new byte[] { ob.Value });
cpuZ80.FillRegisters(de: 0x1234, hl: 0x9876);
model.ClockGen.SquareWave(4);
cpuZ80.AssertRegisters(hl: 0x1234, de: 0x9876);
}
private CpuZ80 ExecuteTest(OpcodeByte ob, Action <CpuZ80> preTest)
{
var cpuZ80 = new CpuZ80();
var model = cpuZ80.Initialize(new[] { ob.Value });
cpuZ80.FillRegisters();
preTest(cpuZ80);
model.ClockGen.SquareWave(4);
Console.WriteLine(model.LogicAnalyzer.ToWaveJson());
return(cpuZ80);
}
private static SimulationModel ExecuteTest(OpcodeByte ret)
{
var cpuZ80 = new CpuZ80();
var buffer = new byte[] { 0xED, ret.Value, 0, 0, 0x55, 0xAA };
var model = cpuZ80.Initialize(buffer);
model.Cpu.FillRegisters(sp: Stack);
model.ClockGen.SquareWave(14);
Console.WriteLine(model.LogicAnalyzer.ToWaveJson());
return model;
}
public static SimulationModel Initialize(this CpuZ80 cpu, byte[] program, byte[] ioSpace = null)
{
new InstructionLogger(cpu);
var model = new SimulationModel();
model.Cpu = cpu;
model.Cpu.Name = "U1";
model.ClockGen = new SignalGenerator();
model.ClockGen.Output.ConnectTo(model.Cpu.Clock, "Clock");
model.Memory = MemoryTestExtensions.NewRam(program);
model.Memory.Name = "U2";
model.Cpu.MemoryRequest.ConnectTo(model.Memory.ChipEnable, "MREQ");
model.Cpu.Read.ConnectTo(model.Memory.OutputEnable, "RD");
model.Cpu.Write.ConnectTo(model.Memory.WriteEnable, "WE");
model.Address = cpu.Address.ConnectTo(model.Memory.Address, "Address");
model.Data = cpu.Data.ConnectTo(model.Memory.Data.Slave, "Data");
new MemoryLogger <BusData16, BusData8>().Attach(model.Memory);
if (ioSpace != null)
{
model.IoSpace = MemoryTestExtensions.NewRam(ioSpace);
model.IoSpace.Name = "U3";
model.Cpu.IoRequest.ConnectTo(model.IoSpace.ChipEnable, "IORQ");
model.IoSpace.OutputEnable.ConnectTo(model.Cpu.Read.DigitalSignal);
model.IoSpace.WriteEnable.ConnectTo(model.Cpu.Write.DigitalSignal);
model.IoSpace.Address.ConnectTo(cpu.Address.Bus);
model.IoSpace.Data.ConnectTo(cpu.Data.Bus);
new MemoryLogger <BusData16, BusData8>("IO").Attach(model.IoSpace);
}
model.LogicAnalyzer = new LogicAnalyzer();
model.LogicAnalyzer.Clock.ConnectTo(model.ClockGen.Output.DigitalSignal);
model.Cpu.MachineCycle1.ConnectTo(model.LogicAnalyzer.AddInput("M1"));
model.Cpu.Refresh.ConnectTo(model.LogicAnalyzer.AddInput("RFSH"));
model.LogicAnalyzer.ConnectInput(model.Cpu.MemoryRequest.DigitalSignal);
if (ioSpace != null)
{
model.LogicAnalyzer.ConnectInput(model.Cpu.IoRequest.DigitalSignal);
}
model.LogicAnalyzer.ConnectInput(model.Cpu.Read.DigitalSignal);
model.LogicAnalyzer.ConnectInput(model.Cpu.Write.DigitalSignal);
model.LogicAnalyzer.ConnectInput(model.Address);
model.LogicAnalyzer.ConnectInput(model.Data);
model.LogicAnalyzer.Start();
return(model);
}
private static CpuZ80 ExecuteTest(OpcodeByte ob, Action <SimulationModel> fnPreTest)
{
var cpuZ80 = new CpuZ80();
byte[] buffer = new byte[] { 0xCB, ob.Value };
var model = cpuZ80.Initialize(buffer);
fnPreTest(model);
model.ClockGen.SquareWave(8);
Console.WriteLine(model.LogicAnalyzer.ToWaveJson());
return(cpuZ80);
}
private SimulationModel ExecuteTest(OpcodeByte ob)
{
var cpu = new CpuZ80();
var model = cpu.Initialize(new byte[] { ob.Value });
cpu.FillRegisters();
model.ClockGen.SquareWave(4);
Console.WriteLine(model.LogicAnalyzer.ToWaveJson());
cpu.AssertRegisters();
return(model);
}
private static SimulationModel ExecuteTest(OpcodeByte pop, byte extension = 0)
{
var cpuZ80 = new CpuZ80();
var buffer = (extension == 0) ?
new byte[] { pop.Value, 0, 0, 0, 0x55, 0xAA } :
new byte[] { extension, pop.Value, 0, 0, 0x55, 0xAA };
var model = cpuZ80.Initialize(buffer);
model.Cpu.FillRegisters(sp: Stack);
model.ClockGen.SquareWave(extension == 0 ? 10 : 14);
Console.WriteLine(model.LogicAnalyzer.ToWaveJson());
return(model);
}
private static SimulationModel ExecuteTest(OpcodeByte ob, byte value)
{
var cpuZ80 = new CpuZ80();
byte[] buffer = new byte[] { 0xCB, ob.Value, 0, 0, 0, value };
var model = cpuZ80.Initialize(buffer);
cpuZ80.FillRegisters(hl: AddressHL);
model.ClockGen.SquareWave(ob.X == 1 ? 12 : 15);
Console.WriteLine(model.LogicAnalyzer.ToWaveJson());
return(model);
}
private static SimulationModel ExecuteTest(OpcodeByte ob, byte value, Action <CpuZ80> preTest, byte extension)
{
var cpuZ80 = new CpuZ80();
byte[] buffer = new byte[] { extension, 0xCB, Offset, ob.Value, value };
var model = cpuZ80.Initialize(buffer);
cpuZ80.FillRegisters();
preTest(cpuZ80);
model.ClockGen.SquareWave(ob.X == 1 ? 20 : 23);
Console.WriteLine(model.LogicAnalyzer.ToWaveJson());
return(model);
}
private static CpuZ80 ExecuteTest(OpcodeByte ob, bool carry)
{
var cpuZ80 = new CpuZ80();
byte[] buffer = new byte[] { ob.Value };
var model = cpuZ80.Initialize(buffer);
cpuZ80.FillRegisters();
cpuZ80.Registers.Flags.C = carry;
model.ClockGen.SquareWave(4);
Console.WriteLine(model.LogicAnalyzer.ToWaveJson());
return(cpuZ80);
}
// TODO: make OUTIR/OUTDR tests that actually repeat.
private SimulationModel ExecuteTest(OpcodeByte ob, Action <CpuZ80> preTest, bool isConditionMet)
{
var cpu = new CpuZ80();
var model = cpu.Initialize(
new byte[] { 0xED, ob.Value, 0, 0, Value, 0, 0 },
new byte[] { 0, 0, 0, 0, 0, 0, 0 });
cpu.FillRegisters();
preTest(cpu);
model.ClockGen.SquareWave(isConditionMet ? 16 : 21);
Console.WriteLine(model.LogicAnalyzer.ToWaveJson());
return(model);
}
public void Clock_PosEdgeCycleT1_SignalsCorrect()
{
var cpu = new CpuZ80();
cpu.Clock(CycleNames.T1, DigitalLevel.PosEdge);
// active
cpu.MachineCycle1.Level.Should().Be(DigitalLevel.Low);
// inactive
cpu.Refresh.Level.Should().Be(DigitalLevel.High);
cpu.IoRequest.Level.Should().Be(DigitalLevel.High);
cpu.Write.Level.Should().Be(DigitalLevel.High);
// bus
cpu.Address.Value.Should().Be(new BusData16(0));
}
private static CpuZ80 ExecuteTest(OpcodeByte ob, Action <CpuZ80> preTest)
{
var cpuZ80 = new CpuZ80();
byte[] buffer = new byte[] { 0xED, ob.Value };
var model = cpuZ80.Initialize(buffer);
cpuZ80.FillRegisters();
preTest(cpuZ80);
model.ClockGen.SquareWave(9);
Console.WriteLine(model.LogicAnalyzer.ToWaveJson());
return(cpuZ80);
}
public void Exx()
{
var ob = OpcodeByte.New(x: 3, z: 1, q: 1, p: 1);
var cpuZ80 = new CpuZ80();
var model = cpuZ80.Initialize(new byte[] { ob.Value });
cpuZ80.FillRegisters(bc: 0x1234, de: 0x5678, hl: 0x9ABC,
a_bc: 0x4321, a_de: 8765, a_hl: 0xCBA9);
model.ClockGen.SquareWave(4);
Console.WriteLine(model.LogicAnalyzer.ToWaveJson());
cpuZ80.AssertRegisters(a_bc: 0x1234, a_de: 0x5678, a_hl: 0x9ABC,
bc: 0x4321, de: 8765, hl: 0xCBA9);
}
private static SimulationModel ExecuteTest(OpcodeByte push,
Action <SimulationModel> preTest, byte extension = 0)
{
var cpuZ80 = new CpuZ80();
var buffer = (extension == 0) ?
new byte[] { push.Value, 0, 0, 0, 0, 0 } :
new byte[] { extension, push.Value, 0, 0, 0, 0 };
var model = cpuZ80.Initialize(buffer);
preTest(model);
model.ClockGen.SquareWave(extension == 0 ? 11 : 15);
Console.WriteLine(model.LogicAnalyzer.ToWaveJson());
return(model);
}
private static CpuZ80 ExecuteTest(OpcodeByte ob, Action <CpuZ80> preTest, byte extension = 0)
{
var cpuZ80 = new CpuZ80();
var buffer = extension == 0 ?
new byte[] { ob.Value, 0, 0, 0, 0, Value } :
new byte[] { extension, ob.Value, Offset, 0, Value, 0 };
var model = cpuZ80.Initialize(buffer);
cpuZ80.FillRegisters();
preTest(cpuZ80);
model.ClockGen.SquareWave(extension == 0 ? 7 : 19);
Console.WriteLine(model.LogicAnalyzer.ToWaveJson());
return(cpuZ80);
}
private static CpuZ80 ExecuteTest(OpcodeByte ob, Func <RegisterSet, bool> preTest)
{
var cpuZ80 = new CpuZ80();
var buffer = new[] { ob.Value, AddressLsb, AddressMsb };
var model = cpuZ80.Initialize(buffer);
model.Cpu.FillRegisters();
var conditionMet = preTest(cpuZ80.Registers);
var def = OpcodeDefinition.Find(ob);
model.ClockGen.SquareWave(def.Cycles.Sum());
Console.WriteLine(model.LogicAnalyzer.ToWaveJson());
return(cpuZ80);
}
