Exemplo n.º 1
0
        public static ulong GetMaxAddress(this CpuBitness @this)
        {
            switch (@this)
            {
            case CpuBitness.Bits32:
                return(uint.MaxValue);

            case CpuBitness.Bits64:
                return(ulong.MaxValue);

            default:
                throw new ArgumentException($"Unsupported cpu bitness encountered: {@this}");
            }
        }
Exemplo n.º 2
0
        protected BaseRiscV(CoreLevelInterruptor clint, uint hartId, string cpuType, Machine machine, PrivilegeArchitecture privilegeArchitecture, Endianess endianness, CpuBitness bitness) : base(cpuType, machine, endianness, bitness)
        {
            HartId = hartId;
            clint.RegisterCPU(this);
            this.clint = clint;
            this.privilegeArchitecture = privilegeArchitecture;

            var architectureSets = DecodeArchitecture(cpuType);

            foreach (var @set in architectureSets)
            {
                if (Enum.IsDefined(typeof(InstructionSet), set))
                {
                    TlibAllowFeature((uint)set);
                }
                else if ((int)set == 'G' - 'A')
                {
                    //G is a wildcard denoting multiple instruction sets
                    foreach (var gSet in new[] { InstructionSet.I, InstructionSet.M, InstructionSet.F, InstructionSet.D, InstructionSet.A })
                    {
                        TlibAllowFeature((uint)gSet);
                    }
                }
                else
                {
                    this.Log(LogLevel.Warning, $"Undefined instruction set: {char.ToUpper((char)(set + 'A'))}.");
                }
            }
            TlibSetPrivilegeArchitecture109(privilegeArchitecture == PrivilegeArchitecture.Priv1_09 ? 1 : 0u);
        }
        protected BaseRiscV(IRiscVTimeProvider timeProvider, uint hartId, string cpuType, Machine machine, PrivilegeArchitecture privilegeArchitecture, Endianess endianness, CpuBitness bitness) : base(hartId, cpuType, machine, endianness, bitness)
        {
            HartId                     = hartId;
            this.timeProvider          = timeProvider;
            this.privilegeArchitecture = privilegeArchitecture;
            ShouldEnterDebugMode       = true;
            nonstandardCSR             = new Dictionary <ulong, Tuple <Func <ulong>, Action <ulong> > >();
            customInstructionsMapping  = new Dictionary <ulong, Action <UInt64> >();

            architectureSets = DecodeArchitecture(cpuType);
            EnableArchitectureVariants();
        }
Exemplo n.º 4
0
        protected BaseRiscV(IRiscVTimeProvider timeProvider, uint hartId, string cpuType, Machine machine, PrivilegeArchitecture privilegeArchitecture, Endianess endianness, CpuBitness bitness, ulong?nmiVectorAddress = null, uint?nmiVectorLength = null, bool allowUnalignedAccesses = false, InterruptMode interruptMode = InterruptMode.Auto)
            : base(hartId, cpuType, machine, endianness, bitness)
        {
            HartId                     = hartId;
            this.timeProvider          = timeProvider;
            this.privilegeArchitecture = privilegeArchitecture;
            shouldEnterDebugMode       = true;
            nonstandardCSR             = new Dictionary <ulong, NonstandardCSR>();
            customInstructionsMapping  = new Dictionary <ulong, Action <UInt64> >();
            this.NMIVectorLength       = nmiVectorLength;
            this.NMIVectorAddress      = nmiVectorAddress;

            architectureSets = DecodeArchitecture(cpuType);
            EnableArchitectureVariants();

            if (this.NMIVectorAddress.HasValue && this.NMIVectorLength.HasValue && this.NMIVectorLength > 0)
            {
                this.Log(LogLevel.Noisy, "Non maskable interrupts enabled with paramters: {0} = {1}, {2} = {3}",
                         nameof(this.NMIVectorAddress), this.NMIVectorAddress, nameof(this.NMIVectorLength), this.NMIVectorLength);
                TlibSetNmiVector(this.NMIVectorAddress.Value, this.NMIVectorLength.Value);
            }
            else
            {
                this.Log(LogLevel.Noisy, "Non maskable interrupts disabled");
                TlibSetNmiVector(0, 0);
            }

            TlibAllowUnalignedAccesses(allowUnalignedAccesses ? 1 : 0);

            try
            {
                this.interruptMode = interruptMode;
                TlibSetInterruptMode((int)interruptMode);
            }
            catch (CpuAbortException)
            {
                throw new ConstructionException(string.Format("Unsupported interrupt mode: 0x{0:X}", interruptMode));
            }

            UserState = new Dictionary <string, object>();
        }
Exemplo n.º 5
0
        protected BaseRiscV(IRiscVTimeProvider timeProvider, uint hartId, string cpuType, Machine machine, PrivilegeArchitecture privilegeArchitecture, Endianess endianness, CpuBitness bitness, ulong?nmiVectorAddress = null, uint?nmiVectorLength = null, bool allowUnalignedAccesses = false)
            : base(hartId, cpuType, machine, endianness, bitness)
        {
            HartId                     = hartId;
            this.timeProvider          = timeProvider;
            this.privilegeArchitecture = privilegeArchitecture;
            ShouldEnterDebugMode       = true;
            nonstandardCSR             = new Dictionary <ulong, Tuple <Func <ulong>, Action <ulong> > >();
            customInstructionsMapping  = new Dictionary <ulong, Action <UInt64> >();
            this.NMIVectorLength       = nmiVectorLength;
            this.NMIVectorAddress      = nmiVectorAddress;

            architectureSets = DecodeArchitecture(cpuType);
            EnableArchitectureVariants();

            if (this.NMIVectorAddress.HasValue && this.NMIVectorLength.HasValue && this.NMIVectorLength > 0)
            {
                this.Log(LogLevel.Noisy, "Non maskable interrupts enabled with paramters: {0} = {1}, {2} = {3}",
                         nameof(this.NMIVectorAddress), this.NMIVectorAddress, nameof(this.NMIVectorLength), this.NMIVectorLength);
                TlibSetNmiVector(this.NMIVectorAddress.Value, this.NMIVectorLength.Value);
            }
            else
            {
                this.Log(LogLevel.Noisy, "Non maskable interrupts disabled");
                TlibSetNmiVector(0, 0);
            }

            TlibAllowUnalignedAccesses(allowUnalignedAccesses ? 1 : 0);

            UserState = new Dictionary <string, object>();
        }