private static Z80CPU GetZ80Cpu()
{
var dataBus = new DataBus();
var addressBus = new AddressBus();
var z80Clock = new PassthroughClock();
var cpuLines = new Z80CPULines
{
AddressBus = addressBus,
DataBus = dataBus,
SystemClock = z80Clock,
BUSACK = new TristateWire(),
BUSREQ = new TristateWire(TristateWireState.PullUp),
HALT = new TristateWire(),
INT = new TristateWire(TristateWireState.PullUp),
IORQ = new TristateWire(),
M1 = new TristateWire(),
MREQ = new TristateWire(),
NMI = new TristateWire(TristateWireState.PullUp),
RD = new TristateWire(),
RESET = new TristateWire(TristateWireState.PullUp),
RFSH = new TristateWire(),
WAIT = new TristateWire(TristateWireState.PullUp),
WR = new TristateWire()
};
var memoryConnects = new MemoryLines
{
AddressBus = addressBus,
Clock = z80Clock,
DataBus = dataBus,
MREQ = cpuLines.MREQ,
RD = cpuLines.RD,
WAIT = cpuLines.WAIT,
WR = cpuLines.WR
};
var unused = new RandomAccessMemory(0, 0x4000, memoryConnects);
return(new Z80CPU(cpuLines));
}
protected NesMemory(Nes nes, AddressBus bus)
{
this.Nes = nes;
this.Bus = bus;
}
public MemoryMapAttribute(AddressBus bus, ushort start, ushort end)
{
this.Bus = bus;
this.Start = start;
this.End = end;
}
// Mapper handling range definitions
private MemoryMapAttribute GetMemoryMapAttribute(AddressBus bus)
{
var attrs = this.GetType().GetCustomAttributes(typeof(MemoryMapAttribute), true).Cast <MemoryMapAttribute>();
return(attrs.First(a => a.Bus == bus));
}
public IllegalMemoryAccessException(AddressBus bus, ushort address, string message = null)
: base(string.Format("Illegal {0} memory access at address 0x{1:X4}" + (message != null ? ": " + message : ""), bus, address))
{
this.Address = address;
}
public UnderhandledMemoryException(AddressBus bus, ushort address, string message = null)
: base(string.Format("Underhandled {0} memory access at address 0x{1:X4}" + (message != null ? ": " + message : ""), bus, address))
{
this.Address = address;
}
