public testbench_XilinxDivider()
{
_m_clk = new Clock(ClockPeriod)
{
Clk = _clk
};
_m_signal = new XilinxDivider()
{
CLK = _clk,
DIVIDEND = _DIVIDEND,
DIVISOR = _DIVISOR,
QUOTIENT = _QUOTIENT,
FRACTIONAL = _FRACTION
};
_m_logger1 = new ConsoleLogger<StdLogicVector>()
{
DataIn = _DIVIDEND
};
_m_logger2 = new ConsoleLogger<StdLogicVector>()
{
DataIn = _DIVISOR
};
_m_logger3 = new ConsoleLogger<StdLogicVector>()
{
DataIn = _QUOTIENT
};
}
public IXILMapping TryMapOne(ITransactionSite taSite, XILInstr instr, TypeDescriptor[] operandTypes, TypeDescriptor[] resultTypes)
{
var fu = taSite.Host;
XilinxDivider divider = fu as XilinxDivider;
if (divider == null)
{
return(null);
}
if (instr.Name != InstructionCodes.Div &&
instr.Name != InstructionCodes.DivQF)
{
return(null);
}
FixFormat fmtDividend = GetFixFormat(operandTypes[0]);
FixFormat fmtDivisor = GetFixFormat(operandTypes[1]);
FixFormat fmtQuotient = GetFixFormat(resultTypes[0]);
FixFormat fmtFractional = null;
if (instr.Name == InstructionCodes.DivQF)
{
fmtFractional = GetFixFormat(resultTypes[1]);
}
if (fmtDividend.IsSigned != fmtDivisor.IsSigned ||
fmtDividend.IsSigned != fmtQuotient.IsSigned)
{
return(null);
}
if (fmtDividend.TotalWidth != fmtQuotient.TotalWidth)
{
return(null);
}
int qFracWidth = fmtDividend.FracWidth - fmtDivisor.FracWidth;
if (qFracWidth != fmtQuotient.FracWidth)
{
return(null);
}
int fracWidth = 0;
if (fmtFractional != null)
{
fracWidth = fmtFractional.TotalWidth;
}
if (divider.DividendAndQuotientWidth != fmtDividend.TotalWidth)
{
return(null);
}
if (divider.DivisorWidth != fmtDivisor.TotalWidth)
{
return(null);
}
if ((divider.OperandSign == XilinxDivider.ESignedness.Signed) !=
fmtDividend.IsSigned)
{
return(null);
}
if (divider.FractionWidth != fracWidth)
{
return(null);
}
return(new DividerXILMapping(divider));
}
public DividerXILMapping(XilinxDivider host)
{
_host = host;
}
public TransactionSite(XilinxDivider host) :
base(host)
{
_host = host;
}
public IXILMapping TryAllocate(Component host, XILInstr instr, TypeDescriptor[] operandTypes, TypeDescriptor[] resultTypes, IProject proj)
{
if (instr.Name != InstructionCodes.Div &&
instr.Name != InstructionCodes.DivQF)
{
return(null);
}
FixFormat fmtDividend = GetFixFormat(operandTypes[0]);
FixFormat fmtDivisor = GetFixFormat(operandTypes[1]);
FixFormat fmtQuotient = GetFixFormat(resultTypes[0]);
if (fmtDividend == null ||
fmtDivisor == null ||
fmtQuotient == null)
{
return(null);
}
FixFormat fmtFractional = null;
if (instr.Name == InstructionCodes.DivQF)
{
fmtFractional = GetFixFormat(resultTypes[1]);
}
if (fmtDividend.IsSigned != fmtDivisor.IsSigned ||
fmtDividend.IsSigned != fmtQuotient.IsSigned)
{
return(null);
}
if (fmtDividend.TotalWidth != fmtQuotient.TotalWidth)
{
return(null);
}
int qFracWidth = fmtDividend.FracWidth - fmtDivisor.FracWidth;
if (qFracWidth != fmtQuotient.FracWidth)
{
return(null);
}
int fracWidth = 0;
if (fmtFractional != null)
{
fracWidth = fmtFractional.TotalWidth;
}
XilinxDivider divider = new XilinxDivider()
{
DividendAndQuotientWidth = fmtDividend.TotalWidth,
DivisorWidth = fmtDivisor.TotalWidth,
FractionWidth = fracWidth,
OperandSign = fmtDividend.IsSigned ? XilinxDivider.ESignedness.Signed : XilinxDivider.ESignedness.Unsigned,
AlgorithmType = XilinxDivider.ERadix.HighRadix,
RemainderType = XilinxDivider.ERemainder.Fractional,
HasCE = false,
HasSCLR = false,
DivideByZeroDetect = false,
LatencyConfiguration = XilinxDivider.ELatencyConfiguration.Manual,
ClocksPerDivision = 1
};
int min = divider.MinLatency;
int max = divider.MaxLatency;
int scaledStages = (int)Math.Round(min + Config.PipeStageScaling * (max - min));
if (scaledStages < min)
{
scaledStages = min;
}
else if (scaledStages > max)
{
scaledStages = max;
}
divider.Latency = scaledStages;
return(new DividerXILMapping(divider));
}
public IXILMapping TryAllocate(Component host, XILInstr instr, TypeDescriptor[] operandTypes, TypeDescriptor[] resultTypes, IProject proj)
{
if (instr.Name != InstructionCodes.Div &&
instr.Name != InstructionCodes.DivQF)
return null;
FixFormat fmtDividend = GetFixFormat(operandTypes[0]);
FixFormat fmtDivisor = GetFixFormat(operandTypes[1]);
FixFormat fmtQuotient = GetFixFormat(resultTypes[0]);
if (fmtDividend == null ||
fmtDivisor == null ||
fmtQuotient == null)
return null;
FixFormat fmtFractional = null;
if (instr.Name == InstructionCodes.DivQF)
fmtFractional = GetFixFormat(resultTypes[1]);
if (fmtDividend.IsSigned != fmtDivisor.IsSigned ||
fmtDividend.IsSigned != fmtQuotient.IsSigned)
return null;
if (fmtDividend.TotalWidth != fmtQuotient.TotalWidth)
return null;
int qFracWidth = fmtDividend.FracWidth - fmtDivisor.FracWidth;
if (qFracWidth != fmtQuotient.FracWidth)
return null;
int fracWidth = 0;
if (fmtFractional != null)
fracWidth = fmtFractional.TotalWidth;
XilinxDivider divider = new XilinxDivider()
{
DividendAndQuotientWidth = fmtDividend.TotalWidth,
DivisorWidth = fmtDivisor.TotalWidth,
FractionWidth = fracWidth,
OperandSign = fmtDividend.IsSigned ? XilinxDivider.ESignedness.Signed : XilinxDivider.ESignedness.Unsigned,
AlgorithmType = XilinxDivider.ERadix.HighRadix,
RemainderType = XilinxDivider.ERemainder.Fractional,
HasCE = false,
HasSCLR = false,
DivideByZeroDetect = false,
LatencyConfiguration = XilinxDivider.ELatencyConfiguration.Manual,
ClocksPerDivision = 1
};
int min = divider.MinLatency;
int max = divider.MaxLatency;
int scaledStages = (int)Math.Round(min + Config.PipeStageScaling * (max - min));
if (scaledStages < min)
scaledStages = min;
else if (scaledStages > max)
scaledStages = max;
divider.Latency = scaledStages;
return new DividerXILMapping(divider);
}
public TransactionSite(XilinxDivider host) :
base(host)
{
_host = host;
}
public DividerXILMapping(XilinxDivider host)
{
_host = host;
}
