public XCore200Rewriter(XCore200Architecture arch, EndianImageReader rdr, ProcessorState state, IStorageBinder binder, IRewriterHost host)
{
this.arch = arch;
this.rdr = rdr;
this.state = state;
this.binder = binder;
this.host = host;
this.dasm = new XCore200Disassembler(arch, rdr).GetEnumerator();
this.instr = null !;
this.m = null !;
}
public override XCoreInstruction Decode(uint wInstr, XCore200Disassembler dasm)
{
foreach (var m in mutators)
{
if (!m(wInstr, dasm))
{
return(dasm.CreateInvalidInstruction());
}
}
var instr = new XCoreInstruction
{
InstructionClass = iclass,
Mnemonic = mnemonic,
Operands = dasm.ops.ToArray()
};
return(instr);
}
public IEnumerator <RtlInstructionCluster> GetEnumerator()
{
while (dasm.MoveNext())
{
this.instr = dasm.Current;
this.iclass = instr.InstructionClass;
var rtls = new List <RtlInstruction>();
this.m = new RtlEmitter(rtls);
switch (instr.Mnemonic)
{
default:
EmitUnitTest();
break;
case Mnemonic.Invalid: m.Invalid(); break;
case Mnemonic.add: RewriteBinOp(m.IAdd); break;
case Mnemonic.addi: RewriteBinOp(m.IAdd); break;
case Mnemonic.and: RewriteBinOp(m.And); break;
case Mnemonic.andnot: RewriteAndNot(); break;
case Mnemonic.bau: RewriteBau(); break;
case Mnemonic.bla: RewriteBla(); break;
case Mnemonic.eq: RewriteBinOp(m.Eq); break;
}
yield return(new RtlInstructionCluster(instr.Address, instr.Length, rtls.ToArray())
{
Class = iclass
});
}
}
