예제 #1
0
        static void run()
        {
            //DateTime start_time = DateTime.Now;

            bool[] is_done = new bool[Config.N];
            for (int i = 0; i < Config.N; i++)
            {
                is_done[i] = false;
            }

            bool   finished       = false;
            string OutputFileName = Config.output + ".csv";

            while (!finished)
            {
                finished = true;

                if (cycles % 1000000 == 0)
                {
                    if (cycles != 0)
                    {
                        string OutputInformation = cycles.ToString() + " " + ((double)Dram_Utilization_size * 64 / 1073741824).ToString() + " " + ((double)Dram_req_num / (Dram_req_num + NVM_req_num + 0.001)).ToString();
                        using (StreamWriter sw = File.AppendText(OutputFileName))
                        {
                            sw.WriteLine(OutputInformation);
                        }
                        Dram_req_num = 0;
                        NVM_req_num  = 0;
                    }
                }

                //processors
                int pid = rand.Next(Config.N);
                for (int i = 0; i < Config.N; i++)
                {
                    Proc curr_proc = procs[pid];
//yang:
                    if (Config.sim_type == Config.SIM_TYPE.GROUPED && pid >= Config.group_boundary && pid < Config.N && is_done[pid] == false)
                    {
                        curr_proc.tick();
                    }
                    else if (Config.sim_type != Config.SIM_TYPE.PARALLEL || is_done[pid] == false)
                    {
                        curr_proc.tick();
                    }
                    pid = (pid + 1) % Config.N;
                }


                //memory controllers
                for (int n = 0; n < Config.mem.mctrl_num; n++)
                {
                    for (int i = 0; i < Config.mem.channel_max; i++)
                    {
                        mctrls[n][i].tick();
                    }
                }


                //blp tracker
                blptracker.tick();

                //xbar
                xbar.tick();

                //cache
                foreach (Cache c in caches)
                {
                    c.tick();
                }


                if (Config.proc.cache_insertion_policy == "PFA")
                {
                    mesur.tick();
                }


                //Jin: Row Migration Policies
                if (Config.proc.cache_insertion_policy == "RBLA" || Config.proc.cache_insertion_policy == "PFA")
                {
                    rmp.tick();
                }


                //progress simulation time
                cycles++;

                //warmup phase
                for (int p = 0; p < Config.N; p++)
                {
                    if (!proc_warmup[p])
                    {
                        if (Stat.procs[p].ipc.Count >= Config.warmup_inst_max)
                        {
                            proc_warmup[p] = true;
                            Stat.procs[p].Reset();
                            foreach (MemCtrlStat mctrl in Stat.mctrls)
                            {
                                mctrl.Reset(pid);
                            }
                            foreach (BankStat bank in Stat.banks)
                            {
                                bank.Reset(pid);
                            }
                            proc_warmup_cycles[p] = cycles;
                            Measurement.warmup_core_stall_cycles[p] = Measurement.core_stall_cycles[p];
                            processor_finished[p]        = false;
                            DRAM_processor_read_hit[p]   = 0;
                            DRAM_processor_read_miss[p]  = 0;
                            DRAM_processor_write_hit[p]  = 0;
                            DRAM_processor_write_miss[p] = 0;
                            DRAM_migration_read_hit[p]   = 0;
                            DRAM_migration_read_miss[p]  = 0;
                            DRAM_migration_write_hit[p]  = 0;
                            DRAM_migration_write_miss[p] = 0;
                            NVM_processor_read_hit[p]    = 0;
                            NVM_processor_read_miss[p]   = 0;
                            NVM_processor_write_hit[p]   = 0;
                            NVM_processor_write_miss[p]  = 0;
                            NVM_migration_read_hit[p]    = 0;
                            NVM_migration_read_miss[p]   = 0;
                            NVM_migration_write_hit[p]   = 0;
                            NVM_migration_write_miss[p]  = 0;
                            processor_cycles[p]          = 0;
                        }
                    }
                }



                //case #1: instruction constrained simulation
                if (Config.sim_type == Config.SIM_TYPE.INST)
                {
                    for (int p = 0; p < Config.N; p++)
                    {
                        if (is_done[p])
                        {
                            continue;
                        }

                        if (proc_warmup[p] && (Stat.procs[p].ipc.Count >= Config.sim_inst_max))
                        {
                            //simulation is now finished for this processor
                            finish_proc(p);
                            is_done[p] = true;

                            //Power Measurement:
                            processor_finished[p] = true;
                            processor_cycles[p]   = cycles - proc_warmup_cycles[p];

                            information_output(p);
                        }
                        else
                        {
                            //simulation is still unfinished for this processor
                            finished = false;
                        }
                    }
                }

                //case #2: cycle constrained simulation  // default case
                else if (Config.sim_type == Config.SIM_TYPE.CYCLE)
                {
                    if (cycles >= Config.sim_cycle_max)
                    {
                        finish_proc();
                        finished = true;
                    }
                    else
                    {
                        finished = false;
                    }
                }

                //case #3: run to completion
                else if (Config.sim_type == Config.SIM_TYPE.COMPLETION || Config.sim_type == Config.SIM_TYPE.PARALLEL)
                {
                    for (int p = 0; p < Config.N; p++)
                    {
                        if (is_done[p])
                        {
                            continue;
                        }

                        if (procs[p].trace.finished)
                        {
                            //simulation is now finished for this processor
                            finish_proc(p);
                            is_done[p] = true;
                        }
                        else
                        {
                            //simulation is still unfinished for this processor
                            finished = false;
                        }
                    }
                }

                //case #4: run to completion for the parallel group
                else if (Config.sim_type == Config.SIM_TYPE.GROUPED)
                {
                    for (int p = Config.group_boundary; p < Config.N; p++)
                    {
                        if (is_done[p])
                        {
                            continue;
                        }

                        if (procs[p].trace.finished)
                        {
                            //simulation is now finished for this processor
                            finish_proc(p);
                            is_done[p] = true;
                        }
                        else
                        {
                            //simulation is still unfinished for this processor
                            finished = false;
                        }
                    }
                    if (finished == true)
                    {
                        for (int p = 0; p < Config.group_boundary; p++)
                        {
                            finish_proc(p);
                        }
                    }
                }
            }
        }
예제 #2
0
        static void run()
        {
            //DateTime start_time = DateTime.Now;

            bool[] is_done = new bool[Config.N];
            for (int i = 0; i < Config.N; i++)
            {
                is_done[i] = false;
            }

            bool finished = false;

            while (!finished)
            {
                finished = true;

                //cache controller

                //processors
                int pid = rand.Next(Config.N);
                for (int i = 0; i < Config.N; i++)
                {
                    Proc curr_proc = procs[pid];
                    curr_proc.tick();
                    pid = (pid + 1) % Config.N;
                }

                //memory controllers
                for (int i = 0; i < Config.mem.channel_max; i++)
                {
                    mctrls[i].tick();
                }

                //blp tracker
                blptracker.tick();

                //xbar
                xbar.tick();

                //progress simulation time
                cycles++;

                //case #1: instruction constrained simulation
                if (Config.sim_type == Config.SIM_TYPE.INST)
                {
                    for (int p = 0; p < Config.N; p++)
                    {
                        if (is_done[p])
                        {
                            continue;
                        }

                        if (Stat.procs[p].ipc.Count >= Config.sim_inst_max)
                        {
                            //simulation is now finished for this processor
                            finish_proc(p);
                            is_done[p] = true;
                        }
                        else
                        {
                            //simulation is still unfinished for this processor
                            finished = false;
                        }
                    }
                }

                //case #2: cycle constrained simulation  // default case
                else if (Config.sim_type == Config.SIM_TYPE.CYCLE)
                {
                    if (cycles >= Config.sim_cycle_max)
                    {
                        finish_proc();
                        finished = true;
                    }
                    else
                    {
                        finished = false;
                    }
                }

                //case #3: run to completion
                else if (Config.sim_type == Config.SIM_TYPE.COMPLETION)
                {
                    for (int p = 0; p < Config.N; p++)
                    {
                        if (is_done[p])
                        {
                            continue;
                        }

                        if (procs[p].trace.finished)
                        {
                            //simulation is now finished for this processor
                            finish_proc(p);
                            is_done[p] = true;
                        }
                        else
                        {
                            //simulation is still unfinished for this processor
                            finished = false;
                        }
                    }
                }
            }
        }