//MemoryAddress public static MemAddr translate(ulong paddr, int pid) { MemAddr addr = new MemAddr(); addr.cid = (uint)((paddr & chan_mask) >> (int)chan_offset); addr.rid = (uint)((paddr & rank_mask) >> (int)rank_offset); if (!Config.mem.bank_spreading) { addr.bid = (uint)((paddr & bank_mask) >> (int)bank_offset); } else { addr.bid = (uint)(pid % 8); } addr.rowid = (ulong)(paddr >> (int)row_offset); if (col2_bits == 0) { addr.colid = (uint)((paddr & col_mask) >> (int)col_offset); } else { uint col2id = (uint)((paddr & col2_mask) >> (int)col2_offset); uint col1id = (uint)((paddr & col1_mask) >> (int)col1_offset); uint colid = col2id + (col1id << (int)col2_bits); addr.colid = colid; } return(addr); }
public void set(int pid, ReqType type, ReqType proc_req_type, ulong paddr) { //state this.pid = pid; this.type = type; this.proc_req_type = proc_req_type; this.row_hit = true; this.actual_addr = paddr; //address if (Config.mctrl.page_randomize) { this.paddr = prand.get_paddr(paddr); } else if (Config.mctrl.page_sequence){ this.paddr = pseq.get_paddr(paddr); } else { this.paddr = paddr; } this.block_addr = this.paddr >> Config.proc.block_size_bits; this.addr = MemMap.translate(this.paddr, pid); //misc this.reset(); }
public void set(int pid, ReqType type, ulong paddr) { //state this.pid = pid; this.type = type; //address if (Config.mctrl.page_randomize) { this.paddr = prand.get_paddr(paddr); } else if (Config.mctrl.page_sequence) { this.paddr = pseq.get_paddr(paddr); } // else if (Config.mctrl.remapping) { // if (mapping_table.contains(paddr >> PAGE_SIZE)) { // this.paddr = mapping_table[paddr >> PAGE_SIZE]; // } // } else { this.paddr = paddr; } this.block_addr = this.paddr >> Config.proc.block_size_bits; this.addr = MemMap.translate(this.paddr, pid); //misc this.reset(); }
public void enqueue_req(Req req) { //check if writeback hit List <Req> q = get_q(req); MemAddr addr = req.addr; // if (cid == 0) Sim.periodic_writer_cum.WriteLine(" Core " + req.pid + " Rank " + addr.rid + " Bank " + addr.bid + " Row " + addr.rowid + " Column " + addr.colid + "\n"); if (req.type == ReqType.RD) { List <Req> wq = writeqs[addr.rid, addr.bid]; int idx = wq.FindIndex(delegate(Req w) { return(w.block_addr == req.block_addr); }); if (idx != -1) { //writeback hit Sim.xbar.enqueue(req); return; } } //writeback dumpster if (req.type == ReqType.WR && Config.mctrl.wb_dump) { req.addr.rowid = 0; } //enqueue proper Dbg.Assert(q.Count < q.Capacity); __enqueue_req(req, q); }
private List <Cmd> decode_req(Req req) { MemAddr addr = req.addr; List <Cmd> cmd_q = cmdqs[addr.rid, addr.bid]; int pid = req.pid; Bank b = chan.ranks[addr.rid].banks[addr.bid]; List <Cmd> decode_cmd_q = new List <Cmd>(CMDQ_MAX); if (b.curr_rowid == -1) { //row-closed req.row_hit = false; decode_cmd_q.Add(new Cmd(Cmd.TypeEnum.ACTIVATE, addr, pid, req, cmd_q)); } else if (b.curr_rowid != (long)addr.rowid) { //row-conflict req.row_hit = false; decode_cmd_q.Add(new Cmd(Cmd.TypeEnum.PRECHARGE, addr, pid, req, cmd_q)); decode_cmd_q.Add(new Cmd(Cmd.TypeEnum.ACTIVATE, addr, pid, req, cmd_q)); } Cmd.TypeEnum RW = (req.type == ReqType.WR ? Cmd.TypeEnum.WRITE : Cmd.TypeEnum.READ); decode_cmd_q.Add(new Cmd(RW, addr, pid, req, cmd_q)); return(decode_cmd_q); }
public void set(int pid, ReqType type, ReqType proc_req_type, ulong paddr) { //state this.pid = pid; this.type = type; this.proc_req_type = proc_req_type; this.row_hit = true; this.actual_addr = paddr; //address if (Config.mctrl.page_randomize) { this.paddr = prand.get_paddr(paddr); } else if (Config.mctrl.page_sequence) { this.paddr = pseq.get_paddr(paddr); } else { this.paddr = paddr; } this.block_addr = this.paddr >> Config.proc.block_size_bits; this.addr = MemMap.translate(this.paddr); this.is_prefetch = false; //misc this.reset(); }
public void enqueue_req(Req req) { //check if writeback hit List <Req> q = get_q(req); MemAddr addr = req.addr; if (req.type == ReqType.RD) { List <Req> wq = writeqs[addr.rid, addr.bid]; int idx = wq.FindIndex(delegate(Req w) { return(w.block_addr == req.block_addr); }); if (idx != -1) { //writeback hit Sim.xbar.enqueue(req); Stat.procs[req.pid].wb_hit.Collect(); return; } } //writeback dumpster if (req.type == ReqType.WR && Config.mctrl.wb_dump) { req.addr.rowid = 0; } //enqueue proper Dbg.Assert(q.Count < q.Capacity); __enqueue_req(req, q); }
//constructor public Cmd(TypeEnum type, MemAddr addr, int pid, Req req, List<Cmd> cmd_q) { valid = true; this.pid = pid; this.addr = addr; this.type = type; this.req = req; this.cmd_q = cmd_q; }
public virtual void reset_rbhit_bit(MemAddr addr) { for (int p = 0; p < Config.N; p++) { if (addr.rowid == meta_mctrl.rbhit_interference_addr[p]) { meta_mctrl.interference_bit_rowbuffer[p] = false; } } }
//constructor public Cmd(TypeEnum type, MemAddr addr, int pid, Req req, List <Cmd> cmd_q) { valid = true; this.pid = pid; this.addr = addr; this.type = type; this.req = req; this.cmd_q = cmd_q; }
private bool insert_mctrl(Req req) { MemAddr addr = req.addr; if (Sim.mctrls[addr.cid].is_q_full(req.pid, req.type, addr.rid, addr.bid)) { return(false); } //success send_req(req); return(true); }
private bool can_write(MemAddr addr) { Dbg.Assert(bus_q.Count < bus_q.Capacity); BusTransaction trans = new BusTransaction(addr, cycles + (timing.tCWL + timing.tBL)); if (bus_q.Count > 0) { BusTransaction last_trans = bus_q[bus_q.Count - 1]; return(chan.can_write(addr.rid, addr.bid) && (trans.ts - last_trans.ts >= timing.tBL)); } return(chan.can_write(addr.rid, addr.bid)); }
private void write(MemAddr addr, int pid) { chan.write(addr.rid, addr.bid); Dbg.Assert(bus_q.Count < bus_q.Capacity); BusTransaction trans = new BusTransaction(addr, cycles + (timing.tCWL + timing.tBL), pid); //check for bus conflict if (bus_q.Count > 0) { BusTransaction last_trans = bus_q[bus_q.Count - 1]; Dbg.Assert(trans.ts - last_trans.ts >= timing.tBL); } bus_q.Add(trans); }
new public void CheckBusConflict() { if (bus_q.Count == 0) { return; } BusTransaction last_trans = bus_q[bus_q.Count - 1]; MemAddr addr = last_trans.addr; for (int i = 0; i < rmax; i++) { for (int j = 0; j < bmax; j++) { if (cmdqs[i, j].Count == 0) { continue; } if (inflightqs[i, j][0].pid == inflightqs[addr.rid, addr.bid][0].pid) { continue; } if (cmdqs[i, j][0].type == Cmd.TypeEnum.READ) { if (cycles + (timing.tCL + timing.tBL) - last_trans.ts < timing.tBL) { if (chan.can_read((uint)i, (uint)j)) { Measurement.Dram_bus_conflict_set(cmdqs[i, j][0].pid); } } } else if (cmdqs[i, j][0].type == Cmd.TypeEnum.WRITE) { if (cycles + (timing.tCWL + timing.tBL) - last_trans.ts < timing.tBL) { if (chan.can_write((uint)i, (uint)j)) { Measurement.Dram_bus_conflict_set(cmdqs[i, j][0].pid); } } } } } }
public void set_prefetch(int pid, ReqType type, ReqType proc_req_type, ulong paddr) { //state this.pid = pid; this.type = type; this.proc_req_type = proc_req_type; this.row_hit = true; this.actual_addr = paddr; this.paddr = paddr; //address this.block_addr = this.paddr >> Config.proc.block_size_bits; this.addr = MemMap.translate(this.paddr); this.is_prefetch = true; //misc this.reset(); }
public void set(int pid, ReqType type, ulong paddr, bool flag) { if (flag == false) { Console.Write("Mistakenly call request set\n"); } //state this.pid = pid; this.type = type; this.paddr = paddr; this.block_addr = this.paddr >> Config.proc.block_size_bits; this.addr = MemMap.translate(this.paddr, pid); //misc this.reset(); }
public bool can_schedule_cmd(Cmd cmd) { //drain reads during the first part of the writeback mode if (wb_mode && reads_to_drain > 0) { if (cmd.type == Cmd.TypeEnum.WRITE) { return(false); } } //drain writes right after the writeback mode if (!wb_mode && writes_to_drain > 0) { if (cmd.type == Cmd.TypeEnum.READ) { return(false); } } //DRAM timing MemAddr addr = cmd.addr; switch (cmd.type) { case Cmd.TypeEnum.ACTIVATE: return(can_activate(addr)); case Cmd.TypeEnum.PRECHARGE: return(can_precharge(addr)); case Cmd.TypeEnum.READ: return(can_read(addr)); case Cmd.TypeEnum.WRITE: return(can_write(addr)); } //should never get here throw new System.Exception("DRAM: Invalid Cmd."); }
private bool insert_mctrl(Req req) { MemAddr addr = req.addr; // req.type = ReqType.RD; //failure if (Sim.mctrls[addr.cid].is_q_full(pid, req.type, addr.rid, addr.bid)) { if (req.type == ReqType.RD) { Stat.procs[req.pid].stall_read_mctrl.Collect(); } else { Stat.procs[req.pid].stall_write_mctrl.Collect(); } return(false); } //success send_req(req); return(true); }
new public void enqueue_req(Req req) { //check if writeback hit List <Req> q = get_q(req); MemAddr addr = req.addr; if ((req.type == ReqType.RD) && (req.callback != null)) { List <Req> wq = writeqs[addr.rid, addr.bid]; int idx = wq.FindIndex(delegate(Req w) { return(w.block_addr == req.block_addr); }); if (idx != -1) { //writeback hit Sim.xbar.enqueue(req); Stat.procs[req.pid].wb_hit.Collect(); if ((!req.migrated_request) && (Config.proc.cache_insertion_policy == "PFA")) { Measurement.mem_num_dec(req);; // Measurement.DramCoreReqNumDec (req); } return; } } //writeback dumpster if (req.type == ReqType.WR && Config.mctrl.wb_dump) { req.addr.rowid = 0; } //enqueue proper Dbg.Assert(q.Count < q.Capacity); __enqueue_req(req, q); }
private void activate(MemAddr addr) { chan.activate(addr.rid, addr.bid, addr.rowid); }
//MemoryAddress public static MemAddr translate(ulong paddr) { MemAddr addr = new MemAddr(); addr.cid = (uint)((paddr & chan_mask) >> (int)chan_offset); addr.rid = (uint)((paddr & rank_mask) >> (int)rank_offset); addr.bid = (uint)((paddr & bank_mask) >> (int)bank_offset); addr.rowid = (ulong)(paddr >> (int)row_offset); if (col2_bits == 0) { addr.colid = (uint)((paddr & col_mask) >> (int)col_offset); } else { uint col2id = (uint)((paddr & col2_mask) >> (int)col2_offset); uint col1id = (uint)((paddr & col1_mask) >> (int)col1_offset); uint colid = col2id + (col1id << (int)col2_bits); addr.colid = colid; } return addr; }
private void issue_cmd(Cmd cmd) { MemAddr addr = cmd.addr; List <Cmd> cmd_q = cmdqs[addr.rid, addr.bid]; Dbg.Assert(cmd == cmd_q[0]); cmd_q.RemoveAt(0); BankStat bank_stat = Stat.banks[addr.cid, addr.rid, addr.bid]; BusStat bus_stat = Stat.busses[addr.cid]; //writeback mode stats if (wb_mode) { if (cmd.type == Cmd.TypeEnum.READ) { rds_per_wb_mode++; } else if (cmd.type == Cmd.TypeEnum.WRITE) { wbs_per_wb_mode++; } } //string dbg; switch (cmd.type) { case Cmd.TypeEnum.ACTIVATE: activate(addr); /*dbg = String.Format("@{0,6} DRAM ACTI: Channel {1}, Rank {2}, Bank {3}, Row {4}, Col {5}", * cycles, cid, addr.rid, addr.bid, addr.rowid, addr.colid);*/ //stats bank_stat.cmd_activate.Collect(); bank_stat.utilization.Collect(timing.tRCD); //shadow row-buffer id meta_mctrl.sched.count_queueing(cmd, pid_rowid_per_procrankbank[addr.rid, addr.bid]); shadow_rowid_per_procrankbank[cmd.pid, addr.rid, addr.bid] = addr.rowid; rowid_per_procrankbank[addr.rid, addr.bid] = addr.rowid; pid_rowid_per_procrankbank[addr.rid, addr.bid] = cmd.req.pid; break; case Cmd.TypeEnum.PRECHARGE: precharge(addr); /*dbg = String.Format("@{0,6} DRAM PREC: Channel {1}, Rank {2}, Bank {3}, Row {4}, Col {5}", * cycles, cid, addr.rid, addr.bid, addr.rowid, addr.colid);*/ //stats bank_stat.cmd_precharge.Collect(); bank_stat.utilization.Collect(timing.tRP); break; case Cmd.TypeEnum.READ: read(addr, cmd.req.pid); /*dbg = String.Format("@{0,6} DRAM READ: Channel {1}, Rank {2}, Bank {3}, Row {4}, Col {5}", * cycles, cid, addr.rid, addr.bid, addr.rowid, addr.colid);*/ //writeback mode if (wb_mode && cmd.is_drain) { Dbg.Assert(reads_to_drain > 0); reads_to_drain--; } //stats bank_stat.cmd_read.Collect(); bank_stat.utilization.Collect(timing.tCL); bus_stat.access.Collect(); bus_stat.utilization.Collect(timing.tBL); // Console.Write("HERE\n"); meta_mctrl.sched.bus_interference_count(cmd); break; case Cmd.TypeEnum.WRITE: write(addr, cmd.req.pid); //writeback mode if (!wb_mode && cmd.is_drain) { Dbg.Assert(writes_to_drain > 0); writes_to_drain--; } else { mwbmode.issued_write_cmd(cmd); } //stats bank_stat.cmd_write.Collect(); bank_stat.utilization.Collect(timing.tCL); bus_stat.access.Collect(); bus_stat.utilization.Collect(timing.tBL); break; default: //should never get here throw new System.Exception("DRAM: Invalid Cmd."); } //Debug.WriteLine(dbg); }
private void issue_req(Req req) { //remove request from waiting queue List <Req> q = get_q(req); Dbg.Assert(q.Contains(req)); q.Remove(req); req.queueing_latency = (int)(cycles - req.ts_arrival); total_queueing_latency[req.pid] += (ulong)req.queueing_latency; if (Sim.highest_rank_proc == req.pid) { Sim.procs[req.pid].queueing_latency += (ulong)req.queueing_latency; } Stat.mctrls[cid].queueing_latency_per_proc[req.pid].Collect(req.queueing_latency); //add to inflight queue MemAddr addr = req.addr; List <Req> inflight_q = inflightqs[addr.rid, addr.bid]; Dbg.Assert(inflight_q.Count < inflight_q.Capacity); inflight_q.Add(req); //add to command queue List <Cmd> cmd_q = cmdqs[addr.rid, addr.bid]; Dbg.Assert(cmd_q.Count == 0); List <Cmd> new_cmd_q = decode_req(req); Dbg.Assert(new_cmd_q.Count > 0); cmd_q.AddRange(new_cmd_q); Cmd cmd = cmd_q[0]; //meta_mctrl meta_mctrl.issue_req(req); req.ts_issue = cycles; //stats BankStat bstat = Stat.banks[addr.cid, addr.rid, addr.bid]; bstat.access.Collect(); if (cmd.type == Cmd.TypeEnum.PRECHARGE || cmd.type == Cmd.TypeEnum.ACTIVATE) { //bank stat bstat.row_miss.Collect(); bstat.row_miss_perproc[req.pid].Collect(); //proc stat if (cmd.req.type == ReqType.RD) { Stat.procs[req.pid].row_hit_rate_read.Collect(0); Stat.procs[req.pid].row_miss_read.Collect(); } else { Stat.procs[req.pid].row_hit_rate_write.Collect(0); Stat.procs[req.pid].row_miss_write.Collect(); } } else { //bank stat bstat.row_hit.Collect(); bstat.row_hit_perproc[req.pid].Collect(); //proc stat if (cmd.req.type == ReqType.RD) { Stat.procs[req.pid].row_hit_rate_read.Collect(1); Stat.procs[req.pid].row_hit_read.Collect(); } else { Stat.procs[req.pid].row_hit_rate_write.Collect(1); Stat.procs[req.pid].row_hit_write.Collect(); } } //issue command issue_cmd(cmd); }
public void paddr_set(ulong paddr, int pid) { // this.paddr = paddr; // this.block_addr = this.paddr >> Config.proc.block_size_bits; this.addr = MemMap.translate(paddr, pid); }
private bool can_write(MemAddr addr) { return chan.can_write(addr.rid, addr.bid); }
public void tick() { //must be the very first thing that's done cycles++; meta_mctrl.tick(cid); wbthrottle.tick(); mwbmode.tick(cid); //load stats for (int p = 0; p < Config.N; p++) { //read load if (rload_per_proc[p] > 0) { Stat.mctrls[cid].rbinaryloadtick_per_proc[p].Collect(); } Stat.mctrls[cid].rloadtick_per_proc[p].Collect(rload_per_proc[p]); //write load if (wload_per_proc[p] > 0) { Stat.mctrls[cid].wbinaryloadtick_per_proc[p].Collect(); } Stat.mctrls[cid].wloadtick_per_proc[p].Collect(wload_per_proc[p]); } //busy/idle stats if (rload > 0) { read_loaded_time++; if (read_unloaded_time > 0) { //Stat.mctrls[cid].read_unloaded_time.Collect(read_unloaded_time); } read_unloaded_time = 0; } else { read_unloaded_time++; if (read_loaded_time > 0) { //Stat.mctrls[cid].read_loaded_time.Collect(read_loaded_time); } read_loaded_time = 0; } /*** writeback mode ***/ update_wb_mode(); /*** clock factor ***/ if (cycles % Config.mem.clock_factor != 0) { return; } /*** serve completed request ***/ if (bus_q.Count > 0 && bus_q[0].ts <= cycles) { MemAddr addr = bus_q[0].addr; for (int p = 0; p < Config.N; p++) { meta_mctrl.interference_bit_bus[p] = false; } foreach (BusTransaction trans in bus_q) { if (trans.pid != bus_q[0].pid) { meta_mctrl.interference_bit_bus[trans.pid] = true; meta_mctrl.interference_bit_bus_proc[trans.pid] = bus_q[0].pid; } } bus_q.RemoveAt(0); meta_mctrl.sched.reset_rbhit_bit(addr); List <Req> inflight_q = inflightqs[addr.rid, addr.bid]; Dbg.Assert(inflight_q.Count > 0); Dbg.Assert(addr == inflight_q[0].addr); Req req = inflight_q[0]; inflight_q.RemoveAt(0); dequeue_req(req); } Cmd best_cmd = find_best_cmd(); Req best_req = find_best_req(); //nothing to issue if (best_cmd == null && best_req == null) { return; } //arbitrate between command and request bool is_issue_req = false; if (best_req != null && best_cmd == null) { is_issue_req = true; } else if (best_req == null && best_cmd != null) { is_issue_req = false; } else { if (best_req == __better_req(best_cmd.req, best_req)) { is_issue_req = true; } else { is_issue_req = false; } } //issue command or request if (is_issue_req) { issue_req(best_req); if (!meta_mctrl.is_omniscient) { meta_mctrl.prev_req_pid = best_req.pid; } else if (cid == 0) { meta_mctrl.prev_req_pid = best_req.pid; } } else { issue_cmd(best_cmd); if (!meta_mctrl.is_omniscient) { meta_mctrl.prev_req_pid = best_cmd.pid; } else if (cid == 0) { meta_mctrl.prev_req_pid = best_cmd.pid; } } }
private bool can_write(MemAddr addr) { return(chan.can_write(addr.rid, addr.bid)); }
private bool can_read(MemAddr addr) { return(chan.can_read(addr.rid, addr.bid)); }
private bool can_precharge(MemAddr addr) { return(chan.can_precharge(addr.rid, addr.bid)); }
public BusTransaction(MemAddr addr, long ts) { this.addr = addr; this.ts = ts; }
private bool can_precharge(MemAddr addr) { return chan.can_precharge(addr.rid, addr.bid); }
new public void tick() { //must be the very first thing that's done cycles++; meta_mctrl.tick(cid); wbthrottle.tick(); mwbmode.tick(cid); //load stats for (int p = 0; p < Config.N; p++) { //read load if (rload_per_proc[p] > 0) { Stat.mctrls2[cid].rbinaryloadtick_per_proc[p].Collect(); } Stat.mctrls2[cid].rloadtick_per_proc[p].Collect(rload_per_proc[p]); //write load if (wload_per_proc[p] > 0) { Stat.mctrls2[cid].wbinaryloadtick_per_proc[p].Collect(); } Stat.mctrls2[cid].wloadtick_per_proc[p].Collect(wload_per_proc[p]); } //busy/idle stats if (rload > 0) { read_loaded_time++; if (read_unloaded_time > 0) { //Stat.mctrls2[cid].read_unloaded_time.Collect(read_unloaded_time); } read_unloaded_time = 0; } else { read_unloaded_time++; if (read_loaded_time > 0) { //Stat.mctrls2[cid].read_loaded_time.Collect(read_loaded_time); } read_loaded_time = 0; } /*** writeback mode ***/ update_wb_mode(); /* * if (wb_mode && cid == 0) { * Console.WriteLine("==={0}==============================================", cycles); * Console.WriteLine("Reads to Drain: {0}", reads_to_drain); * Console.WriteLine("Writes Serviced: {0}", ((DecoupledWBFullServeN) mwbmode).serve_cnt[0]); * uint r = 0; * for (uint b = 0; b < bmax; b++) { * Console.Write("{0}\t", b); * foreach (Cmd cmd in cmdqs[r, b]) { * Console.Write("{0} {1}\t", cmd.type.ToString(), can_schedule_cmd(cmd)); * } * Console.WriteLine(); * } * } */ /*** clock factor ***/ if (cycles % Config.mem.clock_factor != 0) { return; } if ((Config.proc.cache_insertion_policy == "PFA") && (cycles % (6 * Config.mem.clock_factor) == 0)) { int indexi, indexj; for (indexi = 0; indexi < rmax; indexi++) { for (indexj = 0; indexj < bmax; indexj++) { Measurement.read_MLP_cal(ref readqs[indexi, indexj]); Measurement.write_MLP_cal(ref writeqs[indexi, indexj]); Measurement.MLP_cal(ref inflightqs[indexi, indexj]); } } } /*** serve completed request ***/ if (bus_q.Count > 0 && bus_q[0].ts <= cycles) { MemAddr addr = bus_q[0].addr; bus_q.RemoveAt(0); List <Req> inflight_q = inflightqs[addr.rid, addr.bid]; Dbg.Assert(inflight_q.Count > 0); Dbg.Assert(addr == inflight_q[0].addr); Req req = inflight_q[0]; inflight_q.RemoveAt(0); if (Config.proc.cache_insertion_policy == "PFA") { Measurement.DramBankPidDeUpdate(req); } dequeue_req(req); } Cmd best_cmd = find_best_cmd(); Req best_req = find_best_req(); //nothing to issue if (best_cmd == null && best_req == null) { if (Config.proc.cache_insertion_policy == "PFA") { CheckBusConflict(); } return; } //arbitrate between command and request bool is_issue_req = false; if (best_req != null && best_cmd == null) { is_issue_req = true; } else if (best_req == null && best_cmd != null) { is_issue_req = false; } else { if (best_req == __better_req(best_cmd.req, best_req)) { is_issue_req = true; } else { is_issue_req = false; } } //issue command or request if (is_issue_req) { if (!best_req.migrated_request) { if (Config.proc.cache_insertion_policy == "RBLA") { RowStat.UpdateDict(RowStat.DramDict, best_req, this); } else if (Config.proc.cache_insertion_policy == "PFA") { RowStat.UpdateDict(RowStat.DramDict, best_req, this); // Measurement.DramBankPidEnUpdate(best_req); } // if (Config.proc.cache_insertion_policy == "PFA") // Measurement.DramBankPidEnUpdate(best_req); } if (Config.proc.cache_insertion_policy == "PFA") { Measurement.DramBankPidEnUpdate(best_req); } issue_req(best_req); } else { issue_cmd(best_cmd); } if (Config.proc.cache_insertion_policy == "PFA") { CheckBusConflict(); } }
private bool can_read(MemAddr addr) { return chan.can_read(addr.rid, addr.bid); }
private void issue_cmd(Cmd cmd) { MemAddr addr = cmd.addr; /* * if (cid == 0 && wb_mode) { * Console.Write("@{0}\t", cycles - ts_start_wbmode); * for (uint b = 0; b < addr.bid; b++) { * Console.Write("{0,4}", "-"); * } * Console.Write("{0,4}", cmd.type.ToString()[0]); * for (uint b = addr.bid; b < bmax; b++) { * Console.Write("{0,4}", "-"); * } * Console.WriteLine(); * } */ List <Cmd> cmd_q = cmdqs[addr.rid, addr.bid]; Dbg.Assert(cmd == cmd_q[0]); cmd_q.RemoveAt(0); BankStat bank_stat = Stat.banks2[addr.cid, addr.rid, addr.bid]; BusStat bus_stat = Stat.busses2[addr.cid]; //writeback mode stats if (wb_mode) { if (cmd.type == Cmd.TypeEnum.READ) { rds_per_wb_mode++; } else if (cmd.type == Cmd.TypeEnum.WRITE) { wbs_per_wb_mode++; } } //string dbg; switch (cmd.type) { case Cmd.TypeEnum.ACTIVATE: activate(addr); /*dbg = String.Format("@{0,6} DRAM ACTI: Channel {1}, Rank {2}, Bank {3}, Row {4}, Col {5}", * cycles, cid, addr.rid, addr.bid, addr.rowid, addr.colid);*/ //stats bank_stat.cmd_activate.Collect(); bank_stat.utilization.Collect(timing.tRCD); //shadow row-buffer id shadow_rowid_per_procrankbank[cmd.pid, addr.rid, addr.bid] = addr.rowid; break; case Cmd.TypeEnum.PRECHARGE: precharge(addr); /*dbg = String.Format("@{0,6} DRAM PREC: Channel {1}, Rank {2}, Bank {3}, Row {4}, Col {5}", * cycles, cid, addr.rid, addr.bid, addr.rowid, addr.colid);*/ //stats bank_stat.cmd_precharge.Collect(); bank_stat.utilization.Collect(timing.tRP); break; case Cmd.TypeEnum.READ: read(addr); if (Config.proc.cache_insertion_policy == "PFA") { Measurement.Dram_bus_conflict_reset(cmd.req.pid); } /*dbg = String.Format("@{0,6} DRAM READ: Channel {1}, Rank {2}, Bank {3}, Row {4}, Col {5}", * cycles, cid, addr.rid, addr.bid, addr.rowid, addr.colid);*/ //writeback mode if (wb_mode && cmd.is_drain) { Dbg.Assert(reads_to_drain > 0); reads_to_drain--; } //stats bank_stat.cmd_read.Collect(); bank_stat.utilization.Collect(timing.tCL); bus_stat.access.Collect(); bus_stat.utilization.Collect(timing.tBL); break; case Cmd.TypeEnum.WRITE: write(addr); if (Config.proc.cache_insertion_policy == "PFA") { Measurement.Dram_bus_conflict_reset(cmd.req.pid); } /*dbg = String.Format("@{0,6} DRAM WRTE: Channel {1}, Rank {2}, Bank {3}, Row {4}, Col {5}", * cycles, cid, addr.rid, addr.bid, addr.rowid, addr.colid);*/ //writeback mode if (!wb_mode && cmd.is_drain) { Dbg.Assert(writes_to_drain > 0); writes_to_drain--; } else { mwbmode.issued_write_cmd(cmd); } //stats bank_stat.cmd_write.Collect(); bank_stat.utilization.Collect(timing.tCL); bus_stat.access.Collect(); bus_stat.utilization.Collect(timing.tBL); break; default: //should never get here throw new System.Exception("DRAM: Invalid Cmd."); } //Debug.WriteLine(dbg); }
private void precharge(MemAddr addr) { chan.precharge(addr.rid, addr.bid); }
public void tick() { //must be the very first thing that's done cycles++; meta_mctrl.tick(cid); wbthrottle.tick(); mwbmode.tick(cid); //load stats for (int p = 0; p < Config.N; p++) { //read load if (rload_per_proc[p] > 0) { Stat.mctrls[cid].rbinaryloadtick_per_proc[p].Collect(); } Stat.mctrls[cid].rloadtick_per_proc[p].Collect(rload_per_proc[p]); //write load if (wload_per_proc[p] > 0) { Stat.mctrls[cid].wbinaryloadtick_per_proc[p].Collect(); } Stat.mctrls[cid].wloadtick_per_proc[p].Collect(wload_per_proc[p]); } //busy/idle stats if (rload > 0) { read_loaded_time++; if (read_unloaded_time > 0) { //Stat.mctrls[cid].read_unloaded_time.Collect(read_unloaded_time); } read_unloaded_time = 0; } else { read_unloaded_time++; if (read_loaded_time > 0) { //Stat.mctrls[cid].read_loaded_time.Collect(read_loaded_time); } read_loaded_time = 0; } /*** writeback mode ***/ update_wb_mode(); /* * if (wb_mode && cid == 0) { * Console.WriteLine("==={0}==============================================", cycles); * Console.WriteLine("Reads to Drain: {0}", reads_to_drain); * Console.WriteLine("Writes Serviced: {0}", ((DecoupledWBFullServeN) mwbmode).serve_cnt[0]); * uint r = 0; * for (uint b = 0; b < bmax; b++) { * Console.Write("{0}\t", b); * foreach (Cmd cmd in cmdqs[r, b]) { * Console.Write("{0} {1}\t", cmd.type.ToString(), can_schedule_cmd(cmd)); * } * Console.WriteLine(); * } * } */ /*** clock factor ***/ if (cycles % Config.mem.clock_factor != 0) { return; } /*** serve completed request ***/ if (bus_q.Count > 0 && bus_q[0].ts <= cycles) { MemAddr addr = bus_q[0].addr; bus_q.RemoveAt(0); List <Req> inflight_q = inflightqs[addr.rid, addr.bid]; Dbg.Assert(inflight_q.Count > 0); Dbg.Assert(addr == inflight_q[0].addr); Req req = inflight_q[0]; inflight_q.RemoveAt(0); dequeue_req(req); } Cmd best_cmd = find_best_cmd(); Req best_req = find_best_req(); //nothing to issue if (best_cmd == null && best_req == null) { return; } //arbitrate between command and request bool is_issue_req = false; if (best_req != null && best_cmd == null) { is_issue_req = true; } else if (best_req == null && best_cmd != null) { is_issue_req = false; } else { if (best_req == __better_req(best_cmd.req, best_req)) { is_issue_req = true; } else { is_issue_req = false; } } //issue command or request if (is_issue_req) { // Console.Write(" Cycles " + meta_mctrl.get_cycles() + "\n"); issue_req(best_req); meta_mctrl.prev_req_pid = best_req.pid; } else { issue_cmd(best_cmd); meta_mctrl.prev_req_pid = best_cmd.req.pid; } }
public BusTransaction(MemAddr addr, long ts, int pid) { this.addr = addr; this.ts = ts; this.pid = pid; }