public void tick()
{
/*** Preamble ***/
cycles++;
Stat.procs[pid].cycle.Collect();
ulong inst_cnt = Stat.procs[pid].ipc.Count;
if (inst_cnt != 0 && inst_cnt % 1000000 == 0)
{
ulong quantum = inst_cnt / 1000000;
if (quantum > curr_quantum)
{
curr_quantum = quantum;
ulong read_req = Stat.procs[pid].read_req.Count;
Stat.procs[pid].read_quantum.EndQuantum(read_req - prev_read_req);
prev_read_req = read_req;
ulong write_req = Stat.procs[pid].write_req.Count;
Stat.procs[pid].write_quantum.EndQuantum(write_req - prev_write_req);
prev_write_req = write_req;
}
}
/*** Throttle ***/
if (throttle_fraction > 0)
{
if (rand.NextDouble() < throttle_fraction)
{
return;
}
}
/*** Retire ***/
int retired = inst_wnd.retire(Config.proc.ipc);
Stat.procs[pid].ipc.Collect(retired);
if (retired < 0.5 * Config.proc.ipc)
{
Measurement.core_stall_cycles[pid] += 1;
}
/*** Issue writeback request ***/
if (Config.proc.wb && wb_q.Count > 0)
{
bool wb_ok = issue_wb_req(wb_q[0]);
// Console.WriteLine("Issue Write {0}",wb_ok);
if (wb_ok)
{
wb_q.RemoveAt(0);
}
//writeback stall
bool stalled_wb = wb_q.Count > Config.proc.wb_q_max;
if (stalled_wb)
{
return;
}
}
/*** Reissue previous read request ***/
bool issued_rd_req = false;
if (mshr_retry || mctrl_retry)
{
Dbg.Assert(curr_rd_req != null && curr_cpu_inst_cnt == 0);
//mshr/mctrl stall
bool reissue_ok = reissue_rd_req();
// Console.Write("Reissue read {0}",reissue_ok);
if (!reissue_ok)
{
return;
}
//reissue success
Dbg.Assert(!mshr_retry && !mctrl_retry);
issued_rd_req = true;
curr_rd_req = get_req();
}
/*** Issue instructions ***/
Dbg.Assert(curr_rd_req != null);
issue_insts(issued_rd_req);
}
public void tick()
{
/*** Preamble ***/
cycles++;
Stat.procs[pid].cycle.Collect();
if (Config.asm && pid == Sim.highest_rank_proc)
{
high_priority_cycles++;
}
if (Config.asm && pid == Sim.highest_rank_proc && inflight_mem_requests > 0)
{
high_priority_total_miss_latency++;
}
if (inflight_mem_requests > 0)
{
total_miss_latency++;
}
ulong inst_cnt = Stat.procs[pid].ipc.Count;
Stat.procs[pid].num_outstanding_req.Collect(out_read_req);
// if ((inst_cnt/(ulong)Config.eriodicDumpWindow) > (ulong)prev_dump)
if (cycles % (ulong)Config.proc.quantum_cycles == 0)
{
prev_dump++;
// Sim.periodic_writer_ipc.WriteLine(" Proc " + pid + " Cycles " + cycles + " Instructions " + inst_cnt + " " + (double)(inst_cnt - prev_inst_cnt) / (double)(cycles - prev_cycle));
// Sim.periodic_writer_ipc.WriteLine(" Proc " + pid + " Cycles " + cycles + " Instructions " + ((ulong)prev_dump * (ulong)Config.periodicDumpWindow) + " " + (double)(inst_cnt - prev_inst_cnt) / (double)(cycles - prev_cycle));
prev_inst_cnt = inst_cnt;
prev_cycle = cycles;
Sim.periodic_writer_ipc.Flush();
}
if (Config.poll_filter && cycles % (ulong)Config.proc.clear_poll_filter_cycles == 0)
{
pollution_vector.clear_vector();
}
if (quantum_cycles_left > 0)
{
quantum_cycles_left--;
}
else
{
if (Config.fst)
{
double alone_counter = 0;
if (Config.aux_cache)
{
alone_counter = service_counter.get_together_counter() - (service_counter.get_excess_counter() * (Sim.cache_controller.hit_count_current_notsampled[pid] + Sim.cache_controller.miss_count_current_notsampled[pid]) / (Sim.cache_controller.hit_count_current[pid] + Sim.cache_controller.miss_count_current[pid]));
}
else
{
alone_counter = service_counter.get_together_counter() - service_counter.get_excess_counter();
}
slowdown = service_counter.get_together_counter() / alone_counter;
Sim.cache_controller.set_slowdown(pid, slowdown);
Sim.periodic_writer_service.WriteLine(" Proc " + pid + " Slowdown " + slowdown + "\n");
Sim.periodic_writer_service.Flush();
}
else if (Config.asm)
{
if (Config.count_queueing_cycles == false)
{
Sim.queuing_cycles[pid] = 0;
}
Sim.cache_controller.compute_mrc(pid, (int)(inst_cnt - prev_inst_cnt), (high_priority_cycles - Sim.queuing_cycles[pid]));
Sim.cache_controller.compute_hrc(pid, (int)(inst_cnt - prev_inst_cnt), (high_priority_cycles - Sim.queuing_cycles[pid]));
slowdown = Sim.cache_controller.compute_l1_mpkc_slowdown(pid, high_priority_cycles, (high_priority_total_miss_latency), high_priority_total_hit_latency, (ulong)Sim.queuing_cycles[pid]);
if (Config.slowdown_allocation || Config.speedup_allocation || Config.qos_allocation || Config.naive_qos_allocation)
{
Sim.cache_controller.compute_l1_mpkc_slowdown_associativity(pid, high_priority_cycles, high_priority_total_miss_latency, high_priority_total_hit_latency, total_miss_latency, total_hit_latency, (ulong)Sim.queuing_cycles[pid]);
}
Sim.periodic_writer_service.WriteLine(" Proc " + pid + " Slowdown " + slowdown + "\n");
Sim.periodic_writer_service.Flush();
Sim.cache_controller.clear_hits(pid);
high_priority_total_miss_latency = 0;
high_priority_total_hit_latency = 0;
total_miss_latency = 0;
total_hit_latency = 0;
high_priority_total_misses = 0;
high_priority_cycles = 0;
prev_inst_cnt = inst_cnt;
}
if (proc_count < Config.N - 1)
{
proc_count++;
}
else
{
proc_count = 0;
if (Config.ucp)
{
Sim.cache_controller.compute_ucp_allocation();
}
else if (Config.slowdown_allocation || Config.speedup_allocation)
{
Sim.cache_controller.compute_overall_slowdown_allocation();
}
else if (Config.qos_allocation)
{
Sim.cache_controller.compute_qos_slowdown_allocation();
}
else if (Config.naive_qos_allocation)
{
Sim.cache_controller.compute_naive_qos_slowdown_allocation();
}
if (Config.fst)
{
for (int i = 0; i < Config.N; i++)
{
Proc curr_proc = Sim.procs[i];
curr_proc.service_counter.clear_time_counters();
}
}
}
quantum_cycles_left = Config.proc.quantum_cycles;
}
if (!Config.model_memory)
{
service_mem_queue();
}
service_cache_queue();
if (inst_cnt != 0 && inst_cnt % 1000000 == 0)
{
ulong quantum = inst_cnt / 1000000;
if (quantum > curr_quantum)
{
curr_quantum = quantum;
ulong read_req = Stat.procs[pid].read_req.Count;
Stat.procs[pid].read_quantum.EndQuantum(read_req - prev_read_req);
prev_read_req = read_req;
ulong write_req = Stat.procs[pid].write_req.Count;
Stat.procs[pid].write_quantum.EndQuantum(write_req - prev_write_req);
prev_write_req = write_req;
}
}
/*** Retire ***/
int retired = inst_wnd.retire(Config.proc.ipc);
Stat.procs[pid].ipc.Collect(retired);
if (!inst_wnd.is_oldest_ready() && retired != Config.proc.ipc)
{
stall_shared_delta++; //used only in the STFM algorithm
num_stall_cycles++;
}
if (Config.fst)
{
dec_alone_counter();
service_counter.inc_together_counter();
if (Config.model_memory && Config.sched.is_omniscient)
{
if (Config.aux_cache)
{
if ((Sim.mctrls[0].meta_mctrl.interference_bit_bank[pid] == true || Sim.mctrls[0].meta_mctrl.interference_bit_rowbuffer[pid] == true || (interference_bit == true && inst_wnd.is_oldest_alone_hit() && inst_wnd.is_full())) && (inst_wnd.is_full() && cache.is_sampled_set(inst_wnd.addr_oldest())))
{
service_counter.inc_excess_counter();
}
}
else
{
if ((Sim.mctrls[0].meta_mctrl.interference_bit_bank[pid] == true || Sim.mctrls[0].meta_mctrl.interference_bit_rowbuffer[pid] == true || (interference_bit == true && inst_wnd.is_full())) && inst_wnd.is_full())
{
service_counter.inc_excess_counter();
}
}
}
}
if (is_req_outstanding())
{
Stat.procs[pid].memory_cycle.Collect();
memory_fraction_cycles++;
}
/*** Issue writeback request ***/
if (Config.proc.wb && wb_q.Count > 0)
{
bool wb_ok = issue_wb_req(wb_q[0]);
if (wb_ok)
{
wb_q.RemoveAt(0);
}
//writeback stall
bool stalled_wb = wb_q.Count > Config.proc.wb_q_max;
if (stalled_wb)
{
return;
}
}
/*** Reissue previous read request ***/
bool issued_rd_req = false;
if (mshr_retry || mctrl_retry)
{
if (inst_wnd.is_full())
{
Stat.procs[pid].stall_inst_wnd.Collect();
return;
}
Dbg.Assert(curr_rd_req != null && curr_cpu_inst_cnt == 0);
//mshr/mctrl stall
bool reissue_ok = reissue_rd_req();
if (!reissue_ok)
{
return;
}
//reissue success
Dbg.Assert(!mshr_retry && !mctrl_retry);
issued_rd_req = true;
curr_rd_req = get_req();
}
/*** Issue instructions ***/
Dbg.Assert(curr_rd_req != null);
issue_insts(issued_rd_req);
}
public void tick()
{
/*** Preamble ***/
cycles++;
Stat.procs[pid].cycle.Collect();
inst_cnt = Stat.procs[pid].ipc.Count;
if (cycles % 1000000 == 0)
{
Console.Write(" Processor " + pid + " Cycles " + cycles + " Instructions " + inst_cnt + "\n");
}
// if ((inst_cnt/(ulong)Config.periodicDumpWindow) > (ulong)prev_dump)
if (cycles % (ulong)Config.periodicDumpWindow == 0)
{
prev_dump++;
Sim.periodic_writer_ipc.WriteLine(" Proc " + pid + " Cycles " + cycles + " Instructions " + inst_cnt + " " + (double)(inst_cnt - prev_inst_cnt) / (double)(cycles - prev_cycle));
// Sim.periodic_writer_ipc.WriteLine(" Proc " + pid + " Cycles " + cycles + " Instructions " + ((ulong)prev_dump * (ulong)Config.periodicDumpWindow) + " " + (double)(inst_cnt - prev_inst_cnt) / (double)(cycles - prev_cycle));
prev_inst_cnt = inst_cnt;
prev_cycle = cycles;
Sim.periodic_writer_ipc.Flush();
}
if (!Config.model_memory)
{
service_mem_queue();
}
service_cache_queue();
if (inst_cnt != 0 && inst_cnt % 1000000 == 0)
{
ulong quantum = inst_cnt / 1000000;
if (quantum > curr_quantum)
{
curr_quantum = quantum;
ulong read_req = Stat.procs[pid].read_req.Count;
Stat.procs[pid].read_quantum.EndQuantum(read_req - prev_read_req);
prev_read_req = read_req;
ulong write_req = Stat.procs[pid].write_req.Count;
Stat.procs[pid].write_quantum.EndQuantum(write_req - prev_write_req);
prev_write_req = write_req;
}
}
/*** Retire ***/
int retired = inst_wnd.retire(Config.proc.ipc);
Stat.procs[pid].ipc.Collect(retired);
if (Config.pc_trace && inst_wnd.is_full())
{
just_set_full = true;
full_address = (inst_wnd.pc_oldest() >> 32) & (ulong)1023;
criticality_running_table[full_address]++;
}
else
{
if (just_set_full)
{
set_full = false;
}
if (set_full == false)
{
set_full = true;
just_set_full = false;
if (Config.sched.max_stall_crit)
{
if (criticality_running_table[full_address] > criticality_table[full_address])
{
criticality_table[full_address] = criticality_running_table[full_address];
criticality_running_table[full_address] = 0;
}
}
else
{
criticality_table[full_address] += criticality_running_table[full_address];
criticality_running_table[full_address] = 0;
}
}
}
if (is_req_outstanding())
{
Stat.procs[pid].memory_cycle.Collect();
}
/*** Issue writeback request ***/
if (Config.proc.wb && wb_q.Count > 0)
{
bool wb_ok = issue_wb_req(wb_q[0]);
if (wb_ok)
{
wb_q.RemoveAt(0);
}
//writeback stall
bool stalled_wb = wb_q.Count > Config.proc.wb_q_max;
if (stalled_wb)
{
return;
}
}
/*** Reissue previous read request ***/
bool issued_rd_req = false;
if (mshr_retry || mctrl_retry)
{
Dbg.Assert(curr_rd_req != null && curr_cpu_inst_cnt == 0);
//mshr/mctrl stall
bool reissue_ok = reissue_rd_req();
if (!reissue_ok)
{
return;
}
//reissue success
Dbg.Assert(!mshr_retry && !mctrl_retry);
issued_rd_req = true;
curr_rd_req = get_req();
}
/*** Issue instructions ***/
Dbg.Assert(curr_rd_req != null);
issue_insts(issued_rd_req);
}
