/// <summary>
///
/// </summary>
/// <param name="MemorySize">Mem in Bytes [Defaults to 1024 * 1024 * 128 (128MB)]</param>
public CPU(MainBus bus, ulong MemorySize = (1024 * 1024 * 128)) : base(bus)
{
this.alu = new ALU64();
this.MemorySize = MemorySize;
this.registers.setR(Register.sp, MemorySize - 1);
this.state = Cycle.Off;
}
public void Instantiate()
{
Kore.MainBus busTest = new Kore.MainBus();
Assert.AreEqual(typeof(Kore.MainBus), busTest.GetType());
}
public void Setup()
{
bus = new Kore.MainBus();
}
public StubMainBusComponent(Kore.MainBus bus) : base(bus)
{
}
public void Setup()
{
bus = new Kore.MainBus();
cpu = new Kore.CPU(bus);
ram = new Kore.RamController(bus, cpu.MemorySize);
}
/// <summary>
///
/// </summary>
/// <param name="MemorySize">Mem in Bytes [Defaults to 1024 * 1024 * 128 (128MB)]</param>
public RamController(MainBus bus, ulong MemorySize = (1024 * 1024 * 128), ulong firstAddress = 0) : base(bus)
{
this.MemorySize = MemorySize;
mem = new byte[MemorySize];
this.firstAddress = firstAddress;
}
