예제 #1
0
파일: GPARBS.cs 프로젝트: hirous/test
 public SchedGPARBS(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
 {
     bankLoad = new int[Config.Ng,Config.memory.numRanks,Config.memory.numBanks];
     maxBankLoad = new int[Config.Ng];
     totalLoad = new int[Config.Ng];
     overallRank = new int[Config.Ng];
 }
예제 #2
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//	public bool[] schedMask;
//	public int[] bank_reserve;
//	public int   data_bus_reserved_priority;
//	public bool[] bank_reserved_rowhit;

	public DualSlackSchedule(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
	{
	    mpki = new double[Config.Ng];
            prev_cache_miss = new ulong[Config.Ng];
            prev_inst_cnt = new ulong[Config.Ng];
	    top_index_in_buf = new int[Config.Ng];
	    oldest_when_arrived = new ulong[Config.Ng];

            quantum_cycles_left = Config.sched.quantum_cycles;

	    if( bw_required == null )
		bw_required = new int[Config.Ng];
	    if( bw_allocated == null )
		bw_allocated = new int[Config.Ng];
	    if( bw_consumed == null )
		bw_consumed = new int[Config.Ng];
	    if( rank == null )
		rank = new int[Config.Ng];
	    bw_consumed_per_sched = new int[Config.Ng];

	    if( shared_req_per_core == 0 )
		get_effective_req_sum();

	    priority = new int[Config.Ng];
//	    schedMask = new bool[Config.Ng];
//	    bank_reserve = new int[Config.memory.numBanks];
//	    bank_reserved_rowhit = new bool[Config.memory.numBanks];
//	    data_bus_reserved_priority = 0;

	}
예제 #3
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 public SchedPARBS(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf, mem, chan)
 {
     bankLoad    = new int[Config.Ng, Config.memory.numRanks, Config.memory.numBanks];
     maxBankLoad = new int[Config.Ng];
     totalLoad   = new int[Config.Ng];
     overallRank = new int[Config.Ng];
 }
예제 #4
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        public SchedTCMwithPriorHWA(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
        {
            rank = new int[Config.Ng];

            service = new double[Config.Ng];
            curr_service = new double[Config.Ng];
            service_bank_cnt = new uint[Config.Ng];

            mpki = new double[Config.Ng];
            prev_cache_miss = new ulong[Config.Ng];
            prev_inst_cnt = new ulong[Config.Ng];

            rbl = new double[Config.Ng];
            shadow_row_hits = new ulong[Config.Ng];

            blp = new double[Config.Ng];
            blp_sample_sum = new uint[Config.Ng];

            quantum_cycles_left = Config.sched.quantum_cycles;

            nice = new int[Config.Ng];
            shuffle_cycles_left = Config.sched.shuffle_cycles;
            this.chan = chan;
	    
	    log_cnt = 0;
	    req_num = new int[Config.Ng];
	    buf_num = new int[Config.Ng];

	    hwa_prior = new int[Config.HWANum];

	    memreq_cnt = new int[Config.Ng];
	    for( int i = 0; i < Config.Ng; i++ )
		memreq_cnt[i] = 0;
        }
예제 #5
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 public ATLAS(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf, mem, chan)
 {
     rank                = new int[Config.Ng];
     service_bank_cnt    = new uint[Config.Ng];
     curr_service        = new double[Config.Ng];
     service             = new double[Config.Ng];
     this.chan           = chan;
     quantum_cycles_left = Config.sched.quantum_cycles;
 }
예제 #6
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//	public bool[] schedMask;
//	public int[] bank_reserve;
//	public int   data_bus_reserved_priority;
//	public bool[] bank_reserved_rowhit;

        public SchedFRFCFSDeadLine(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
        {
	    hwa_prior = new int[Config.HWANum];
	    deadline_prior = new int[Config.Ng];
//	    schedMask = new bool[Config.Ng];
//	    bank_reserve = new int[Config.memory.numBanks];
//	    bank_reserved_rowhit = new bool[Config.memory.numBanks];
//	    data_bus_reserved_priority = 0;
        }
예제 #7
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//	public bool[] schedMask;
//	public int[] bank_reserve;
//	public int   data_bus_reserved_priority;
//	public bool[] bank_reserved_rowhit;

        public SchedFRFCFSDeadLine(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf, mem, chan)
        {
            hwa_prior      = new int[Config.HWANum];
            deadline_prior = new int[Config.Ng];
//	    schedMask = new bool[Config.Ng];
//	    bank_reserve = new int[Config.memory.numBanks];
//	    bank_reserved_rowhit = new bool[Config.memory.numBanks];
//	    data_bus_reserved_priority = 0;
        }
예제 #8
0
파일: ATLAS.cs 프로젝트: hirous/test
 public ATLAS(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
 {
     rank = new int[Config.Ng];
     service_bank_cnt = new uint[Config.Ng];
     curr_service = new double[Config.Ng];
     service = new double[Config.Ng];
     this.chan = chan;
     quantum_cycles_left = Config.sched.quantum_cycles;
 }
예제 #9
0
파일: Sched.cs 프로젝트: hirous/test
        public Scheduler(SchedBuf[] buf, DRAM mem, Channel chan)
        {
            this.buf  = buf;
            this.mem  = mem;
            this.chan = chan;

            schedMask                  = new bool[Config.Ng];
            bank_reserve               = new int[Config.memory.numBanks];
            bank_reserve_priority      = new int[Config.memory.numBanks];
            bank_reserved_rowhit       = new bool[Config.memory.numBanks];
            data_bus_reserved_priority = 0;
        }
예제 #10
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파일: DRAM.cs 프로젝트: hirous/test
 public Rank(int index, DRAM mem, Channel chan)
 {
     this.index = index;
     this.mem   = mem;
     this.chan  = chan;
     numBanks   = Config.memory.numBanks;
     banks      = new Bank[numBanks];
     for (int i = 0; i < numBanks; i++)
     {
         banks[i] = new Bank(i, mem, chan, this);
     }
 }
예제 #11
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파일: DRAM.cs 프로젝트: hirous/test
        public Bank(int index, DRAM mem, Channel chan, Rank rank)
        {
            this.index = index;
            this.mem   = mem;
            this.chan  = chan;
            this.rank  = rank;

            cRAS = Config.memory.cRAS;
            cCAS = Config.memory.cCAS;
            cWR  = Config.memory.cWR;
            cDQS = Config.memory.cDQS;
            cWTR = Config.memory.cWTR;
            cRCD = Config.memory.cRCD;
            cRP  = Config.memory.cRP;
            cRTP = Config.memory.cRTP;
            cRC  = Config.memory.cRC;
            cRRD = Config.memory.cRRD;
        }
예제 #12
0
파일: DRAM.cs 프로젝트: hirous/test
        public Bank(int index, DRAM mem, Channel chan, Rank rank)
        {
            this.index = index;
            this.mem = mem;
            this.chan = chan;
            this.rank = rank;

            cRAS = Config.memory.cRAS;
            cCAS = Config.memory.cCAS;
            cWR  = Config.memory.cWR;
            cDQS = Config.memory.cDQS;
            cWTR = Config.memory.cWTR;
            cRCD = Config.memory.cRCD;
            cRP  = Config.memory.cRP;
            cRTP = Config.memory.cRTP;
            cRC  = Config.memory.cRC;
            cRRD = Config.memory.cRRD;
        }
예제 #13
0
파일: TCM_deadline.cs 프로젝트: hirous/test
        public SchedTCMDeadLine(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
        {
            rank = new int[Config.Ng];

            service = new double[Config.Ng];
            curr_service = new double[Config.Ng];
            service_bank_cnt = new uint[Config.Ng];

            mpki = new double[Config.Ng];
            prev_cache_miss = new ulong[Config.Ng];
            prev_inst_cnt = new ulong[Config.Ng];

            rbl = new double[Config.Ng];
            shadow_row_hits = new ulong[Config.Ng];

            blp = new double[Config.Ng];
            blp_sample_sum = new uint[Config.Ng];

            quantum_cycles_left = Config.sched.quantum_cycles;

            nice = new int[Config.Ng];
            shuffle_cycles_left = Config.sched.shuffle_cycles;
            this.chan = chan;

	    Console.WriteLine("TCM Parameter Quantum:{0}, shuffle:{1}", quantum_cycles_left, shuffle_cycles_left );
	    Console.WriteLine("Exception Check!!");
	    catchflag = 0;

	    hwa_prior = new int[Config.HWANum];
	    deadline_prior = new int[Config.Ng];

	    mem_intensity_req_cnt = new int[Config.Ng];
	    mem_nonintensity_req_cnt = new int[Config.Ng];
	    next_cnt_disable = new bool[Config.Ng];

	    for( int i = 0; i < Config.Ng; i++ )
	    {
		mem_intensity_req_cnt[i] = 0;
		mem_nonintensity_req_cnt[i] = 0;
		next_cnt_disable[i] = false;
	    }

        }
예제 #14
0
파일: TCM_deadline.cs 프로젝트: hirous/test
        public SchedTCMDeadLine(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf, mem, chan)
        {
            rank = new int[Config.Ng];

            service          = new double[Config.Ng];
            curr_service     = new double[Config.Ng];
            service_bank_cnt = new uint[Config.Ng];

            mpki            = new double[Config.Ng];
            prev_cache_miss = new ulong[Config.Ng];
            prev_inst_cnt   = new ulong[Config.Ng];

            rbl             = new double[Config.Ng];
            shadow_row_hits = new ulong[Config.Ng];

            blp            = new double[Config.Ng];
            blp_sample_sum = new uint[Config.Ng];

            quantum_cycles_left = Config.sched.quantum_cycles;

            nice = new int[Config.Ng];
            shuffle_cycles_left = Config.sched.shuffle_cycles;
            this.chan           = chan;

            Console.WriteLine("TCM Parameter Quantum:{0}, shuffle:{1}", quantum_cycles_left, shuffle_cycles_left);
            Console.WriteLine("Exception Check!!");
            catchflag = 0;

            hwa_prior      = new int[Config.HWANum];
            deadline_prior = new int[Config.Ng];

            mem_intensity_req_cnt    = new int[Config.Ng];
            mem_nonintensity_req_cnt = new int[Config.Ng];
            next_cnt_disable         = new bool[Config.Ng];

            for (int i = 0; i < Config.Ng; i++)
            {
                mem_intensity_req_cnt[i]    = 0;
                mem_nonintensity_req_cnt[i] = 0;
                next_cnt_disable[i]         = false;
            }
        }
예제 #15
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        public SchedTCMwithPriorHWA(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf, mem, chan)
        {
            rank = new int[Config.Ng];

            service          = new double[Config.Ng];
            curr_service     = new double[Config.Ng];
            service_bank_cnt = new uint[Config.Ng];

            mpki            = new double[Config.Ng];
            prev_cache_miss = new ulong[Config.Ng];
            prev_inst_cnt   = new ulong[Config.Ng];

            rbl             = new double[Config.Ng];
            shadow_row_hits = new ulong[Config.Ng];

            blp            = new double[Config.Ng];
            blp_sample_sum = new uint[Config.Ng];

            quantum_cycles_left = Config.sched.quantum_cycles;

            nice = new int[Config.Ng];
            shuffle_cycles_left = Config.sched.shuffle_cycles;
            this.chan           = chan;

            log_cnt = 0;
            req_num = new int[Config.Ng];
            buf_num = new int[Config.Ng];

            hwa_prior = new int[Config.HWANum];

            memreq_cnt = new int[Config.Ng];
            for (int i = 0; i < Config.Ng; i++)
            {
                memreq_cnt[i] = 0;
            }
        }
예제 #16
0
파일: TCM.cs 프로젝트: hirous/test
        public SchedTCM(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
        {
            rank = new int[Config.Ng];

            service = new double[Config.Ng];
            curr_service = new double[Config.Ng];
            service_bank_cnt = new uint[Config.Ng];

            mpki = new double[Config.Ng];
            prev_cache_miss = new ulong[Config.Ng];
            prev_inst_cnt = new ulong[Config.Ng];

            rbl = new double[Config.Ng];
            shadow_row_hits = new ulong[Config.Ng];

            blp = new double[Config.Ng];
            blp_sample_sum = new uint[Config.Ng];

            quantum_cycles_left = Config.sched.quantum_cycles;

            nice = new int[Config.Ng];
            shuffle_cycles_left = Config.sched.shuffle_cycles;
            this.chan = chan;
        }
예제 #17
0
파일: TCM.cs 프로젝트: hirous/test
        public SchedTCM(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf, mem, chan)
        {
            rank = new int[Config.Ng];

            service          = new double[Config.Ng];
            curr_service     = new double[Config.Ng];
            service_bank_cnt = new uint[Config.Ng];

            mpki            = new double[Config.Ng];
            prev_cache_miss = new ulong[Config.Ng];
            prev_inst_cnt   = new ulong[Config.Ng];

            rbl             = new double[Config.Ng];
            shadow_row_hits = new ulong[Config.Ng];

            blp            = new double[Config.Ng];
            blp_sample_sum = new uint[Config.Ng];

            quantum_cycles_left = Config.sched.quantum_cycles;

            nice = new int[Config.Ng];
            shuffle_cycles_left = Config.sched.shuffle_cycles;
            this.chan           = chan;
        }
예제 #18
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        public SchedFRFCFSwithPriorHWA (SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
        {
	    hwa_prior = new int[Config.HWANum];
        }
예제 #19
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파일: INVFRFCFS.cs 프로젝트: hirous/test
 public SchedInvFRFCFS(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
 {
 }
예제 #20
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파일: FCFS.cs 프로젝트: hirous/test
 public SchedFCFS(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf, mem, chan)
 {
 }
예제 #21
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파일: Sched.cs 프로젝트: hirous/test
        /* HWA CODE END */

        public SchedBuf(int index, DRAM mem)
        {
            this.index = index;
            this.mem   = mem;
        }
예제 #22
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        public SchedTCMClusterOptProb4(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
        {
            rank = new int[Config.Ng];

            service = new double[Config.Ng];
            curr_service = new double[Config.Ng];
            service_bank_cnt = new uint[Config.Ng];

            mpki = new double[Config.Ng];
            prev_cache_miss = new ulong[Config.Ng];
            prev_inst_cnt = new ulong[Config.Ng];

            rbl = new double[Config.Ng];
            shadow_row_hits = new ulong[Config.Ng];

            blp = new double[Config.Ng];
            blp_sample_sum = new uint[Config.Ng];

            quantum_cycles_left = Config.sched.quantum_cycles;

            nice = new int[Config.Ng];
            shuffle_cycles_left = Config.sched.shuffle_cycles;
            this.chan = chan;

	    Console.WriteLine("TCM Parameter Quantum:{0}, shuffle:{1}", quantum_cycles_left, shuffle_cycles_left );
	    Console.WriteLine("Exception Check!!");
	    catchflag = 0;

	    hwa_prior = new int[Config.HWANum];
	    deadline_prior = new int[Config.Ng];

	    cRandom = new System.Random();

	    mem_intensity_req_cnt = new int[Config.Ng];
	    mem_nonintensity_req_cnt = new int[Config.Ng];
	    next_cnt_disable = new bool[Config.Ng];
	    memreq_cnt = new int[Config.Ng];
	    for( int i = 0; i < Config.Ng; i++ )
		memreq_cnt[i] = 0;

	    for( int i = 0; i < Config.Ng; i++ )
	    {
		mem_intensity_req_cnt[i] = 0;
		mem_nonintensity_req_cnt[i] = 0;
		next_cnt_disable[i] = false;
	    }

	    cluster_factor = Config.sched.AS_cluster_factor;
	    pre_req_num = new ulong[Config.Ng];
	    for( int i = 0; i < Config.Ng; i++ )
	    {
		pre_req_num[i] = 0;
	    }
	    accelerate_probability_nonint = new int[Config.Ng];
	    accelerate_probability_int = new int[Config.Ng];
	    
	    for( int i = 0; i < Config.Ng; i++ )
	    {
		accelerate_probability_nonint[i] = Config.sched.accelerate_probability_nonint;
		accelerate_probability_int[i] = Config.sched.accelerate_probability_int;
	    }

	    quantum_cycles_for_probability = Config.sched.quantum_cycles_for_probability;
	    quantum_cycles_left_for_probability = Config.sched.quantum_cycles_for_probability;

	    quantum_cycles_for_suspend = Config.sched.quantum_cycles_for_suspend;
	    quantum_cycles_left_for_suspend = 0;

	    bw_shortage_cnt = 0;
        }
예제 #23
0
파일: INVMPKI.cs 프로젝트: hirous/test
 public SchedInvMPKI(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
 {
     mpki = new double[Config.Ng];
 }
예제 #24
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파일: Mem.cs 프로젝트: hirous/test
	/* HWA Code End */

        public Channel(int mem_id, int id)
        {
            this.mem_id = mem_id;
            this.id = id;
            this.numRanks = Config.memory.numRanks;
            this.numBanks = Config.memory.numBanks;

            mem = new DRAM(this);

            this.IATCounter = new ulong[Config.Ng];
            this.RBHCount = new int[Config.Ng];
            this.insnsCount = new ulong[Config.Ng];
            this.memServiceCount = new int[Config.Ng];
            this.BLP = new double[Config.Ng];
            this.BufferUsed = new double[Config.Ng];
            this.loadPerProc = new int[Config.Ng];
            this.ComboHitsCounts = 0;

            for(int i=0;i<Config.Ng;i++)
                IATCounter[i]=0;
            // Scheduler
            buf = new SchedBuf[Config.memory.schedBufSize];
            for(int i=0;i<buf.Length;i++)
                buf[i] = new SchedBuf(i,mem);
 

            switch(Config.memory.DCTARBPolicy)
            {
                case "INVFCFS":
                    sched = new SchedInvFCFS(buf,mem,this); break;
                case "INVFRFCFS":
                    sched = new SchedInvFRFCFS(buf,mem,this); break;
                case "FCFS":
                    sched = new SchedFCFS(buf,mem,this); break;
                case "FRFCFS":
                    sched = new SchedFRFCFS(buf,mem,this); break;
                case "CoreID":
                    sched = new SchedCoreID(buf,mem,this); break;
                case "GFRFCFS":
                    sched = new SchedGFRFCFS(buf,mem,this); break;
                case "INVMPKI":
                    sched = new SchedInvMPKI(buf,mem,this); break;
                case "MPKI":
                    sched = new SchedMPKI(buf,mem,this); break;
                case "PARBS":
                    sched = new SchedPARBS(buf,mem,this); break;
                case "GPARBS":
                    sched = new SchedGPARBS(buf,mem,this); break;
                case "FRFCFS_PrioCPU":
                    sched = new SchedFRFCFS_PrioCPU(buf,mem,this); break;
                case "FRFCFS_CPUBURST":
                    sched = new SchedFRFCFS_PrioCPUWhenNonBursty(buf,mem,this); break;
                case "BLP":
                    sched = new SchedBLP(buf,mem,this); break;
                case "CTCM":
                    sched = new SchedCTCM(buf,mem,this); break;
                case "INVTCM":
                    sched = new SchedInvTCM(buf,mem,this); break;
                case "TCM":
                    sched = new SchedTCM(buf,mem,this); break;
                case "ATLAS":
                    sched = new ATLAS(buf,mem,this); break;
		/* HWA CODE */
                case "FRFCFS_DEADLINE":
                    sched = new SchedFRFCFSDeadLine(buf,mem,this); 
		    Console.WriteLine("FRFCFS_DeadLine selected");
		    break;
                case "FRFCFS_PRIORHWA":
                    sched = new SchedFRFCFSwithPriorHWA(buf,mem,this); 
		    Console.WriteLine("FRFCFS_withPriorHWA selected");
		    break;
                case "TCM_PRIORHWA":
                    sched = new SchedTCMwithPriorHWA(buf,mem,this);
		    Console.WriteLine("TCM_PriorHWA selected");
		    break;
                case "TCM_CLUSTEROPT":
                    sched = new SchedTCMClusterOpt(buf,mem,this);
		    Console.WriteLine("TCM_clusterOpt selected");
		    break;
                case "TCM_CLUSTEROPTPROB4":
                    sched = new SchedTCMClusterOptProb4(buf,mem,this);
		    Console.WriteLine("TCM_clusterOptProb4 selected");
		    break;
                case "TCM_DEADLINE":
                    sched = new SchedTCMDeadLine(buf,mem,this);
		    Console.WriteLine("TCM_deadline selected");
		    break;

		/* HWA CODE END */
                default:
                    Console.Error.WriteLine("Unknown DCT ARB Policy \"{0}\"",Config.memory.DCTARBPolicy);
                    Environment.Exit(-1);
                    break;
            }

            coreRequests = 0;
            GPURequests = 0;
            readRequests = 0;
            writeRequests = 0;
	    /* HWA CODE */
	    HWARequests = 0;
	    HWAUnIssueRequests = 0;
	    unIssueRequestsPerCore = new int[Config.Ng];
	    unIssueReadRequestsPerCore = new int[Config.Ng];
	    RequestsPerBank = new int[numBanks];

	    for(int i = 0; i < Config.Ng; i++ )
	    {
		unIssueRequestsPerCore[i] = 0;
		unIssueReadRequestsPerCore[i] = 0;
	    }
	    for(int i = 0; i < numBanks; i++ )
		RequestsPerBank[i] = 0;
	    /* HWA CODE End */

            lastBankActivity = new ulong[numRanks,numBanks];
            for(int r=0;r<numRanks;r++)
                for(int b=0;b<numBanks;b++)
                    lastBankActivity[r,b] = 0;

	    /* HWA Code Comment Out */
	    /*
            maxCoreRequests = buf.Length - Config.memory.reservedGPUEntries;
            if(maxCoreRequests < 8) maxCoreRequests = 8;
            maxGPURequests = buf.Length - Config.memory.reservedCoreEntries;
            if(maxGPURequests < 8) maxGPURequests = 8;
	    */
	    /* HWA Code Comment Out End */
            maxReads = Config.memory.RDBSize;
            maxWrites = Config.memory.WDBSize;
	    /* HWA Code */
            maxCoreRequests = buf.Length - Config.memory.reservedGPUEntries - Config.memory.reservedHWAEntries;
            if(maxCoreRequests < 8) maxCoreRequests = 8;
            maxGPURequests = buf.Length - Config.memory.reservedCoreEntries - Config.memory.reservedHWAEntries;
            if(maxGPURequests < 8) maxGPURequests = 8;
	    maxHWARequests = buf.Length - Config.memory.reservedCoreEntries - Config.memory.reservedGPUEntries;
	    if( maxHWARequests < 8 ) maxHWARequests = 8;

	    Console.WriteLine("maxRequests {0},{1},{2}",maxCoreRequests,maxGPURequests,maxHWARequests);
	    /* HWA Code End */
        }
예제 #25
0
 public SchedFRFCFSwithPriorHWA(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf, mem, chan)
 {
     hwa_prior = new int[Config.HWANum];
 }
예제 #26
0
 public SchedCoreID(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf, mem, chan)
 {
 }
예제 #27
0
 public SchedFRFCFS_PrioCPUWhenNonBursty(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf, mem, chan)
 {
     ch = chan;
 }
예제 #28
0
파일: Mem.cs 프로젝트: hirous/test
        /* HWA Code End */

        public Channel(int mem_id, int id)
        {
            this.mem_id   = mem_id;
            this.id       = id;
            this.numRanks = Config.memory.numRanks;
            this.numBanks = Config.memory.numBanks;

            mem = new DRAM(this);

            this.IATCounter      = new ulong[Config.Ng];
            this.RBHCount        = new int[Config.Ng];
            this.insnsCount      = new ulong[Config.Ng];
            this.memServiceCount = new int[Config.Ng];
            this.BLP             = new double[Config.Ng];
            this.BufferUsed      = new double[Config.Ng];
            this.loadPerProc     = new int[Config.Ng];
            this.ComboHitsCounts = 0;

            for (int i = 0; i < Config.Ng; i++)
            {
                IATCounter[i] = 0;
            }
            // Scheduler
            buf = new SchedBuf[Config.memory.schedBufSize];
            for (int i = 0; i < buf.Length; i++)
            {
                buf[i] = new SchedBuf(i, mem);
            }


            switch (Config.memory.DCTARBPolicy)
            {
            case "INVFCFS":
                sched = new SchedInvFCFS(buf, mem, this); break;

            case "INVFRFCFS":
                sched = new SchedInvFRFCFS(buf, mem, this); break;

            case "FCFS":
                sched = new SchedFCFS(buf, mem, this); break;

            case "FRFCFS":
                sched = new SchedFRFCFS(buf, mem, this); break;

            case "CoreID":
                sched = new SchedCoreID(buf, mem, this); break;

            case "GFRFCFS":
                sched = new SchedGFRFCFS(buf, mem, this); break;

            case "INVMPKI":
                sched = new SchedInvMPKI(buf, mem, this); break;

            case "MPKI":
                sched = new SchedMPKI(buf, mem, this); break;

            case "PARBS":
                sched = new SchedPARBS(buf, mem, this); break;

            case "GPARBS":
                sched = new SchedGPARBS(buf, mem, this); break;

            case "FRFCFS_PrioCPU":
                sched = new SchedFRFCFS_PrioCPU(buf, mem, this); break;

            case "FRFCFS_CPUBURST":
                sched = new SchedFRFCFS_PrioCPUWhenNonBursty(buf, mem, this); break;

            case "BLP":
                sched = new SchedBLP(buf, mem, this); break;

            case "CTCM":
                sched = new SchedCTCM(buf, mem, this); break;

            case "INVTCM":
                sched = new SchedInvTCM(buf, mem, this); break;

            case "TCM":
                sched = new SchedTCM(buf, mem, this); break;

            case "ATLAS":
                sched = new ATLAS(buf, mem, this); break;

            /* HWA CODE */
            case "FRFCFS_DEADLINE":
                sched = new SchedFRFCFSDeadLine(buf, mem, this);
                Console.WriteLine("FRFCFS_DeadLine selected");
                break;

            case "FRFCFS_PRIORHWA":
                sched = new SchedFRFCFSwithPriorHWA(buf, mem, this);
                Console.WriteLine("FRFCFS_withPriorHWA selected");
                break;

            case "TCM_PRIORHWA":
                sched = new SchedTCMwithPriorHWA(buf, mem, this);
                Console.WriteLine("TCM_PriorHWA selected");
                break;

            case "TCM_CLUSTEROPT":
                sched = new SchedTCMClusterOpt(buf, mem, this);
                Console.WriteLine("TCM_clusterOpt selected");
                break;

            case "TCM_CLUSTEROPTPROB4":
                sched = new SchedTCMClusterOptProb4(buf, mem, this);
                Console.WriteLine("TCM_clusterOptProb4 selected");
                break;

            case "TCM_DEADLINE":
                sched = new SchedTCMDeadLine(buf, mem, this);
                Console.WriteLine("TCM_deadline selected");
                break;

            /* HWA CODE END */
            default:
                Console.Error.WriteLine("Unknown DCT ARB Policy \"{0}\"", Config.memory.DCTARBPolicy);
                Environment.Exit(-1);
                break;
            }

            coreRequests  = 0;
            GPURequests   = 0;
            readRequests  = 0;
            writeRequests = 0;
            /* HWA CODE */
            HWARequests                = 0;
            HWAUnIssueRequests         = 0;
            unIssueRequestsPerCore     = new int[Config.Ng];
            unIssueReadRequestsPerCore = new int[Config.Ng];
            RequestsPerBank            = new int[numBanks];

            for (int i = 0; i < Config.Ng; i++)
            {
                unIssueRequestsPerCore[i]     = 0;
                unIssueReadRequestsPerCore[i] = 0;
            }
            for (int i = 0; i < numBanks; i++)
            {
                RequestsPerBank[i] = 0;
            }
            /* HWA CODE End */

            lastBankActivity = new ulong[numRanks, numBanks];
            for (int r = 0; r < numRanks; r++)
            {
                for (int b = 0; b < numBanks; b++)
                {
                    lastBankActivity[r, b] = 0;
                }
            }

            /* HWA Code Comment Out */

            /*
             * maxCoreRequests = buf.Length - Config.memory.reservedGPUEntries;
             * if(maxCoreRequests < 8) maxCoreRequests = 8;
             * maxGPURequests = buf.Length - Config.memory.reservedCoreEntries;
             * if(maxGPURequests < 8) maxGPURequests = 8;
             */
            /* HWA Code Comment Out End */
            maxReads  = Config.memory.RDBSize;
            maxWrites = Config.memory.WDBSize;
            /* HWA Code */
            maxCoreRequests = buf.Length - Config.memory.reservedGPUEntries - Config.memory.reservedHWAEntries;
            if (maxCoreRequests < 8)
            {
                maxCoreRequests = 8;
            }
            maxGPURequests = buf.Length - Config.memory.reservedCoreEntries - Config.memory.reservedHWAEntries;
            if (maxGPURequests < 8)
            {
                maxGPURequests = 8;
            }
            maxHWARequests = buf.Length - Config.memory.reservedCoreEntries - Config.memory.reservedGPUEntries;
            if (maxHWARequests < 8)
            {
                maxHWARequests = 8;
            }

            Console.WriteLine("maxRequests {0},{1},{2}", maxCoreRequests, maxGPURequests, maxHWARequests);
            /* HWA Code End */
        }
예제 #29
0
 public SchedFRFCFS_PrioCPU(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf, mem, chan)
 {
 }
예제 #30
0
파일: Sched.cs 프로젝트: hirous/test
	/* HWA CODE END */

        public SchedBuf(int index, DRAM mem)
        {
            this.index = index;
            this.mem = mem;
        }
예제 #31
0
파일: Sched.cs 프로젝트: hirous/test
        public Scheduler(SchedBuf[] buf, DRAM mem, Channel chan)
        {
            this.buf = buf;
            this.mem = mem;
            this.chan = chan;

	    schedMask = new bool[Config.Ng];
	    bank_reserve = new int[Config.memory.numBanks];
	    bank_reserve_priority = new int[Config.memory.numBanks];
	    bank_reserved_rowhit = new bool[Config.memory.numBanks];
	    data_bus_reserved_priority = 0;
	    
        }
예제 #32
0
 public SchedBLP(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
 {
 }
예제 #33
0
파일: MPKI.cs 프로젝트: hirous/test
 public SchedMPKI(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf, mem, chan)
 {
     mpki = new double[Config.Ng];
 }
예제 #34
0
 public SchedFRFCFS_PrioCPUWhenNonBursty(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
 {
     ch = chan;
 }
예제 #35
0
파일: DRAM.cs 프로젝트: hirous/test
 public Rank(int index, DRAM mem, Channel chan)
 {
     this.index = index;
     this.mem = mem;
     this.chan = chan;
     numBanks = Config.memory.numBanks;
     banks = new Bank[numBanks];
     for(int i=0;i<numBanks;i++)
         banks[i] = new Bank(i,mem,chan,this);
 }
예제 #36
0
파일: invTCM.cs 프로젝트: hirous/test
 public SchedInvTCM(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf, mem, chan)
 {
 }
예제 #37
0
 public SchedFRFCFS_PrioCPU(SchedBuf[] buf, DRAM mem, Channel chan) : base(buf,mem,chan)
 {
 }