public override NetlistContainer GetSelectedDesignElements()
{
// resulting design
TCLContainer result = new TCLContainer("GetSelectedDesignElements");
result.Name = Name;
// filter instances
foreach (Instance inst in Instances)
{
if (TileSelectionManager.Instance.IsSelected(inst.TileKey))
{
result.Add(inst);
}
}
// filter nets
foreach (TCLNet inNet in Nets)
{
// create copy
TCLNet outNet = TCLNet.Copy(inNet);
outNet.NodeNet = true;
// cleat net pins and readd only he selected ones in the for each loop
outNet.ClearNetPins();
foreach (NetPin pin in inNet.NetPins)
{
if (!m_instances.ContainsKey(pin.InstanceName))
{
if (TileSelectionManager.Instance.IsSelected(FPGA.FPGA.Instance.GetTile(pin.TileName)))
{
outNet.Add(pin);
}
}
else
{
if (TileSelectionManager.Instance.IsSelected(GetInstanceByName(pin.InstanceName).TileKey))
{
outNet.Add(pin);
}
}
}
if (outNet.RoutingTree.GetAllRoutingNodes().Any(n => !n.VirtualNode && !TileSelectionManager.Instance.IsSelected(n.Tile)))
{
outNet.FlattenNet();
outNet.Remove(node => !node.VirtualNode && !TileSelectionManager.Instance.IsSelected(node.Tile));
}
if (outNet.RoutingTree.GetAllRoutingNodes().Any(n => !n.VirtualNode))
{
result.Add(outNet);
}
}
return(result);
}