protected static void m6803_mem(address_map map, device_t owner)
{
m6801_cpu_device m6801 = (m6801_cpu_device)owner;
m6801_io(map, m6801);
map.op(0x0080, 0x00ff).ram(); /* 6803 internal RAM */
}
/*************************************
*
* Address maps
*
*************************************/
/* complete address map verified from Moon Patrol/10 Yard Fight schematics */
/* large map uses 8k ROMs, small map uses 4k ROMs; this is selected via a jumper */
protected void m52_small_sound_map(address_map map, device_t device)
{
map.global_mask(0x7fff);
map.op(0x0000, 0x0fff).w(m52_adpcm_w);
map.op(0x1000, 0x1fff).w(sound_irq_ack_w);
map.op(0x2000, 0x7fff).rom();
}
void mspacman_map(address_map map, device_t device)
{
/* start with 0000-3fff and 8000-bfff mapped to the ROMs */
map.op(0x0000, 0xffff).bankr("bank1");
map.op(0x4000, 0x7fff).mirror(0x8000).unmaprw();
map.op(0x4000, 0x43ff).mirror(0xa000).ram().w(pacman_videoram_w).share("videoram");
map.op(0x4400, 0x47ff).mirror(0xa000).ram().w(pacman_colorram_w).share("colorram");
map.op(0x4800, 0x4bff).mirror(0xa000).r(pacman_read_nop).nopw();
map.op(0x4c00, 0x4fef).mirror(0xa000).ram();
map.op(0x4ff0, 0x4fff).mirror(0xa000).ram().share("spriteram");
map.op(0x5000, 0x5007).mirror(0xaf38).w(m_mainlatch, (offset, data) => { m_mainlatch.op0.write_d0(offset, data); }); //FUNC(ls259_device::write_d0));
map.op(0x5040, 0x505f).mirror(0xaf00).w(m_namco_sound, (offset, data) => { m_namco_sound.op0.pacman_sound_w(offset, data); }); //FUNC(namco_device::pacman_sound_w));
map.op(0x5060, 0x506f).mirror(0xaf00).writeonly().share("spriteram2");
map.op(0x5070, 0x507f).mirror(0xaf00).nopw();
map.op(0x5080, 0x5080).mirror(0xaf3f).nopw();
map.op(0x50c0, 0x50c0).mirror(0xaf3f).w(m_watchdog, (data) => { m_watchdog.op0.reset_w(data); }); //FUNC(watchdog_timer_device::reset_w));
map.op(0x5000, 0x5000).mirror(0xaf3f).portr("IN0");
map.op(0x5040, 0x5040).mirror(0xaf3f).portr("IN1");
map.op(0x5080, 0x5080).mirror(0xaf3f).portr("DSW1");
map.op(0x50c0, 0x50c0).mirror(0xaf3f).portr("DSW2");
/* overlay decode enable/disable on top */
map.op(0x0038, 0x003f).rw(mspacman_disable_decode_r_0x0038, mspacman_disable_decode_w);
map.op(0x03b0, 0x03b7).rw(mspacman_disable_decode_r_0x03b0, mspacman_disable_decode_w);
map.op(0x1600, 0x1607).rw(mspacman_disable_decode_r_0x1600, mspacman_disable_decode_w);
map.op(0x2120, 0x2127).rw(mspacman_disable_decode_r_0x2120, mspacman_disable_decode_w);
map.op(0x3ff0, 0x3ff7).rw(mspacman_disable_decode_r_0x3ff0, mspacman_disable_decode_w);
map.op(0x3ff8, 0x3fff).rw(mspacman_enable_decode_r_0x3ff8, mspacman_enable_decode_w);
map.op(0x8000, 0x8007).rw(mspacman_disable_decode_r_0x8000, mspacman_disable_decode_w);
map.op(0x97f0, 0x97f7).rw(mspacman_disable_decode_r_0x97f0, mspacman_disable_decode_w);
}
/*************************************
*
* Special shifter circuit
*
*************************************/
//u8 mw8080bw_state::mw8080bw_shift_result_rev_r()
/*************************************
*
* Main CPU memory handlers
*
*************************************/
void main_map(address_map map, device_t device)
{
map.global_mask(0x7fff);
map.op(0x0000, 0x1fff).rom().nopw();
map.op(0x2000, 0x3fff).mirror(0x4000).ram().share("main_ram");
map.op(0x4000, 0x5fff).rom().nopw();
}
/*************************************
*
* Main CPU port handlers
*
*************************************/
void writeport(address_map map, device_t device)
{
pacman_state state = (pacman_state)device;
map.global_mask(0xff);
map.op(0x00, 0x00).w(state.pacman_interrupt_vector_w); /* Pac-Man only */
}
void mspacman_map(address_map map, device_t device)
{
pacman_state pacman_state = (pacman_state)device;
/* start with 0000-3fff and 8000-bfff mapped to the ROMs */
map.op(0x0000, 0xffff).bankr("bank1");
map.op(0x4000, 0x7fff).mirror(0x8000).unmaprw();
map.op(0x4000, 0x43ff).mirror(0xa000).ram().w(pacman_state.pacman_videoram_w).share("videoram");
map.op(0x4400, 0x47ff).mirror(0xa000).ram().w(pacman_state.pacman_colorram_w).share("colorram");
map.op(0x4800, 0x4bff).mirror(0xa000).r(pacman_state.pacman_read_nop).nopw();
map.op(0x4c00, 0x4fef).mirror(0xa000).ram();
map.op(0x4ff0, 0x4fff).mirror(0xa000).ram().share("spriteram");
map.op(0x5000, 0x5007).mirror(0xaf38).w(pacman_state.mainlatch.target, pacman_state.ls259_device_write_d0_mainlatch);
map.op(0x5040, 0x505f).mirror(0xaf00).w(pacman_state.namco_sound.target, pacman_state.namco_device_pacman_sound_w);
map.op(0x5060, 0x506f).mirror(0xaf00).writeonly().share("spriteram2");
map.op(0x5070, 0x507f).mirror(0xaf00).nopw();
map.op(0x5080, 0x5080).mirror(0xaf3f).nopw();
map.op(0x50c0, 0x50c0).mirror(0xaf3f).w(pacman_state.watchdog.target, pacman_state.watchdog_timer_device_reset_w);
map.op(0x5000, 0x5000).mirror(0xaf3f).portr("IN0");
map.op(0x5040, 0x5040).mirror(0xaf3f).portr("IN1");
map.op(0x5080, 0x5080).mirror(0xaf3f).portr("DSW1");
map.op(0x50c0, 0x50c0).mirror(0xaf3f).portr("DSW2");
/* overlay decode enable/disable on top */
map.op(0x0038, 0x003f).rw(pacman_state.mspacman_disable_decode_r_0x0038, pacman_state.mspacman_disable_decode_w);
map.op(0x03b0, 0x03b7).rw(pacman_state.mspacman_disable_decode_r_0x03b0, pacman_state.mspacman_disable_decode_w);
map.op(0x1600, 0x1607).rw(pacman_state.mspacman_disable_decode_r_0x1600, pacman_state.mspacman_disable_decode_w);
map.op(0x2120, 0x2127).rw(pacman_state.mspacman_disable_decode_r_0x2120, pacman_state.mspacman_disable_decode_w);
map.op(0x3ff0, 0x3ff7).rw(pacman_state.mspacman_disable_decode_r_0x3ff0, pacman_state.mspacman_disable_decode_w);
map.op(0x3ff8, 0x3fff).rw(pacman_state.mspacman_enable_decode_r_0x3ff8, pacman_state.mspacman_enable_decode_w);
map.op(0x8000, 0x8007).rw(pacman_state.mspacman_disable_decode_r_0x8000, pacman_state.mspacman_disable_decode_w);
map.op(0x97f0, 0x97f7).rw(pacman_state.mspacman_disable_decode_r_0x97f0, pacman_state.mspacman_disable_decode_w);
}
// device_disasm_interface overrides
//virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
protected static void m6803_mem(address_map map, device_t owner)
{
m6801_cpu_device m6801 = (m6801_cpu_device)owner;
map.op(0x0000, 0x001f).rw(m6801.m6801_io_r, m6801.m6801_io_w);
map.op(0x0020, 0x007f).noprw(); /* unused */
map.op(0x0080, 0x00ff).ram(); /* 6803 internal RAM */
}
void sound_map(address_map map, device_t device)
{
map.op(0x0000, 0x3fff).rom();
map.op(0x4000, 0x47ff).ram();
map.op(0x6000, 0x6000).r(soundlatch.target, generic_latch_8_device_read);
map.op(0x8000, 0x8001).w("ay1", ay8910_device_address_data_w_ay1);
map.op(0xc000, 0xc001).w("ay2", ay8910_device_address_data_w_ay2);
}
//void pa_w(u8 data) { port_input_w<0>(data); }
//void pb_w(u8 data) { port_input_w<1>(data); }
//void pc_w(u8 data) { port_input_w<2>(data); }
protected override void internal_map(address_map map)
{
base.internal_map(map);
map.op(0x0080, 0x0784).rw(eprom_r_0x0080, eprom_w_0x0080); // User EPROM
map.op(0x0785, 0x07f7).rom().region("bootstrap", 0);
map.op(0x07f8, 0x07ff).rw(eprom_r_0x07f8, eprom_w_0x07f8); // Interrupt vectors
}
void sound_map(address_map map, device_t device)
{
map.op(0x0000, 0x3fff).rom();
map.op(0x4000, 0x47ff).ram();
map.op(0x6000, 0x6000).r(m_soundlatch, () => { return(m_soundlatch.op0.read()); }); //r(m_soundlatch, FUNC(generic_latch_8_device::read));
map.op(0x8000, 0x8001).w("ay1", (offset, data) => { ((ay8910_device)subdevice("ay1")).address_data_w(offset, data); }); //w("ay1", FUNC(ay8910_device::address_data_w));
map.op(0xc000, 0xc001).w("ay2", (offset, data) => { ((ay8910_device)subdevice("ay2")).address_data_w(offset, data); }); //w("ay2", FUNC(ay8910_device::address_data_w));
}
void main_portmap(address_map map, device_t device)
{
map.global_mask(0xff);
map.op(0x00, 0x00).mirror(0x1f).w(m52_scroll_w);
map.op(0x40, 0x40).mirror(0x1f).w(m52_bg1xpos_w);
map.op(0x60, 0x60).mirror(0x1f).w(m52_bg1ypos_w);
map.op(0x80, 0x80).mirror(0x1f).w(m52_bg2xpos_w);
map.op(0xa0, 0xa0).mirror(0x1f).w(m52_bg2ypos_w);
map.op(0xc0, 0xc0).mirror(0x1f).w(m52_bgcontrol_w);
}
void io_map(address_map map, device_t device)
{
map.global_mask(0x7);
map.op(0x00, 0x00).mirror(0x04).portr("IN0");
map.op(0x01, 0x01).mirror(0x04).portr("IN1");
map.op(0x02, 0x02).mirror(0x04).portr("IN2");
map.op(0x03, 0x03).mirror(0x04).r(m_mb14241, () => { return(m_mb14241.op0.shift_result_r()); });
map.op(0x00, 0x07).w(io_w); // no decoder, just 3 AND gates
}
void taitosj_audio_map(address_map map, device_t device)
{
map.op(0x0000, 0x3fff).rom();
map.op(0x4000, 0x43ff).ram();
map.op(0x4800, 0x4801).mirror(0x07f8).w(m_ay.op(1), (data) => { m_ay.op(1).op0.data_w(data); }); //FUNC(ay8910_device::address_data_w));
map.op(0x4801, 0x4801).mirror(0x07f8).r(m_ay.op(1), () => { return(m_ay.op(1).op0.data_r()); }); //FUNC(ay8910_device::data_r));
map.op(0x4802, 0x4803).mirror(0x07f8).w(m_ay.op(2), (data) => { m_ay.op(2).op0.data_w(data); }); //FUNC(ay8910_device::address_data_w));
map.op(0x4803, 0x4803).mirror(0x07f8).r(m_ay.op(2), () => { return(m_ay.op(2).op0.data_r()); }); //FUNC(ay8910_device::data_r));
map.op(0x4804, 0x4805).mirror(0x07fa).w(m_ay.op(3), (data) => { m_ay.op(3).op0.data_w(data); }); //FUNC(ay8910_device::address_data_w));
map.op(0x4805, 0x4805).mirror(0x07fa).r(m_ay.op(3), () => { return(m_ay.op(3).op0.data_r()); }); //FUNC(ay8910_device::data_r));
map.op(0x5000, 0x5000).mirror(0x07fc).rw(soundlatch_r, soundlatch_clear7_w);
map.op(0x5001, 0x5001).mirror(0x07fc).rw(soundlatch_flags_r, sound_semaphore2_clear_w);
map.op(0xe000, 0xefff).rom(); // space for diagnostic ROM
}
/*************************************
*
* Memory maps
*
*************************************/
void main_map(address_map map, device_t device)
{
map.op(0x0000, 0x3fff).rom();
map.op(0x8000, 0x83ff).ram().w(m52_videoram_w).share("videoram");
map.op(0x8400, 0x87ff).ram().w(m52_colorram_w).share("colorram");
map.op(0x8800, 0x8800).mirror(0x07ff).r(m52_protection_r);
map.op(0xc800, 0xcbff).mirror(0x0400).writeonly().share("spriteram"); // only 0x100 of this used by video code?
map.op(0xd000, 0xd000).mirror(0x07fc).w("irem_audio", irem_audio_device_cmd_w);
map.op(0xd001, 0xd001).mirror(0x07fc).w(m52_flipscreen_w); /* + coin counters */
map.op(0xd000, 0xd000).mirror(0x07f8).portr("IN0");
map.op(0xd001, 0xd001).mirror(0x07f8).portr("IN1");
map.op(0xd002, 0xd002).mirror(0x07f8).portr("IN2");
map.op(0xd003, 0xd003).mirror(0x07f8).portr("DSW1");
map.op(0xd004, 0xd004).mirror(0x07f8).portr("DSW2");
map.op(0xe000, 0xe7ff).ram();
}
void _1942_map(address_map map, device_t device)
{
map.op(0x0000, 0x7fff).rom();
map.op(0x8000, 0xbfff).bankr("bank1");
map.op(0xc000, 0xc000).portr("SYSTEM");
map.op(0xc001, 0xc001).portr("P1");
map.op(0xc002, 0xc002).portr("P2");
map.op(0xc003, 0xc003).portr("DSWA");
map.op(0xc004, 0xc004).portr("DSWB");
map.op(0xc800, 0xc800).w(soundlatch.target, generic_latch_8_device_write);
map.op(0xc802, 0xc803).w(_1942_scroll_w);
map.op(0xc804, 0xc804).w(_1942_c804_w);
map.op(0xc805, 0xc805).w(_1942_palette_bank_w);
map.op(0xc806, 0xc806).w(_1942_bankswitch_w);
map.op(0xcc00, 0xcc7f).ram().share("spriteram");
map.op(0xd000, 0xd7ff).ram().w(_1942_fgvideoram_w).share("fg_videoram");
map.op(0xd800, 0xdbff).ram().w(_1942_bgvideoram_w).share("bg_videoram");
map.op(0xe000, 0xefff).ram();
}
/*************************************
*
* Main CPU memory handlers
*
*************************************/
void pacman_map(address_map map, device_t device)
{
//A lot of games don't have an a15 at the cpu. Generally only games with a cpu daughter board can access the full 32k of romspace.
map.op(0x0000, 0x3fff).mirror(0x8000).rom();
map.op(0x4000, 0x43ff).mirror(0xa000).ram().w(pacman_videoram_w).share("videoram");
map.op(0x4400, 0x47ff).mirror(0xa000).ram().w(pacman_colorram_w).share("colorram");
map.op(0x4800, 0x4bff).mirror(0xa000).r(pacman_read_nop).nopw();
map.op(0x4c00, 0x4fef).mirror(0xa000).ram();
map.op(0x4ff0, 0x4fff).mirror(0xa000).ram().share("spriteram");
map.op(0x5000, 0x5007).mirror(0xaf38).w(m_mainlatch, (offset, data) => { m_mainlatch.op0.write_d0(offset, data); }); //FUNC(addressable_latch_device::write_d0));
map.op(0x5040, 0x505f).mirror(0xaf00).w(m_namco_sound, (offset, data) => { m_namco_sound.op0.pacman_sound_w(offset, data); }); //FUNC(namco_device::pacman_sound_w));
map.op(0x5060, 0x506f).mirror(0xaf00).writeonly().share("spriteram2");
map.op(0x5070, 0x507f).mirror(0xaf00).nopw();
map.op(0x5080, 0x5080).mirror(0xaf3f).nopw();
map.op(0x50c0, 0x50c0).mirror(0xaf3f).w(m_watchdog, (data) => { m_watchdog.op0.reset_w(data); }); //FUNC(watchdog_timer_device::reset_w));
map.op(0x5000, 0x5000).mirror(0xaf3f).portr("IN0");
map.op(0x5040, 0x5040).mirror(0xaf3f).portr("IN1");
map.op(0x5080, 0x5080).mirror(0xaf3f).portr("DSW1");
map.op(0x50c0, 0x50c0).mirror(0xaf3f).portr("DSW2");
}
/*************************************
*
* Main CPU memory handlers
*
*************************************/
void dkong_map(address_map map, device_t device)
{
map.op(0x0000, 0x4fff).rom();
map.op(0x6000, 0x6bff).ram();
map.op(0x7000, 0x73ff).ram().share("sprite_ram"); /* sprite set 1 */
map.op(0x7400, 0x77ff).ram().w(dkong_videoram_w).share("video_ram");
map.op(0x7800, 0x780f).rw(m_dma8257, (offset) => { return(m_dma8257.op0.read(offset)); }, (offset, data) => { m_dma8257.op0.write(offset, data); }); //FUNC(i8257_device::read), FUNC(i8257_device::write)); /* P8257 control registers */
map.op(0x7c00, 0x7c00).portr("IN0").w("ls175.3d", (offset, data) => { ((latch8_device)subdevice("ls175.3d")).write(offset, data); }); //FUNC(latch8_device::write)); /* IN0, sound CPU intf */
map.op(0x7c80, 0x7c80).portr("IN1").w(radarscp_grid_color_w); /* IN1 */
map.op(0x7d00, 0x7d00).r(dkong_in2_r); /* IN2 */
map.op(0x7d00, 0x7d07).w(m_dev_6h, (offset, data) => { m_dev_6h.op0.bit0_w(offset, data); }); //FUNC(latch8_device::bit0_w)); /* Sound signals */
map.op(0x7d80, 0x7d80).portr("DSW0").w(dkong_audio_irq_w); /* DSW0 */
map.op(0x7d81, 0x7d81).w(radarscp_grid_enable_w);
map.op(0x7d82, 0x7d82).w(dkong_flipscreen_w);
map.op(0x7d83, 0x7d83).w(dkong_spritebank_w); /* 2 PSL Signal */
map.op(0x7d84, 0x7d84).w(nmi_mask_w);
map.op(0x7d85, 0x7d85).w(p8257_drq_w); /* P8257 ==> /DRQ0 /DRQ1 */
map.op(0x7d86, 0x7d87).w(dkong_palettebank_w);
}
/*************************************
*
* Centipede CPU memory handlers
*
*************************************/
void centiped_base_map(address_map map, device_t device)
{
map.global_mask(0x3fff);
map.op(0x0000, 0x03ff).ram().share("rambase");
map.op(0x0400, 0x07bf).ram().w(centiped_videoram_w).share("videoram");
map.op(0x07c0, 0x07ff).ram().share("spriteram");
map.op(0x0800, 0x0800).portr("DSW1");
map.op(0x0801, 0x0801).portr("DSW2");
map.op(0x0c00, 0x0c00).r(centiped_IN0_r);
map.op(0x0c01, 0x0c01).portr("IN1");
map.op(0x0c02, 0x0c02).r(centiped_IN2_r);
map.op(0x0c03, 0x0c03).portr("IN3");
map.op(0x1400, 0x140f).w(centiped_paletteram_w).share("paletteram");
map.op(0x1600, 0x163f).nopr().w(earom_write);
map.op(0x1680, 0x1680).w(earom_control_w);
map.op(0x1700, 0x173f).r(earom_read);
map.op(0x1800, 0x1800).w(irq_ack_w);
map.op(0x1c00, 0x1c07).nopr().w("outlatch", (offset, data) => { ((addressable_latch_device)subdevice("outlatch")).write_d7(offset, data); }); //FUNC(ls259_device::write_d7));
map.op(0x2000, 0x2000).w("watchdog", (data) => { ((watchdog_timer_device)subdevice("watchdog")).reset_w(data); }); //FUNC(watchdog_timer_device::reset_w));
map.op(0x2000, 0x3fff).rom();
}
/*************************************
*
* Main CPU memory handlers
*
*************************************/
public void dkong_map(address_map map, device_t device)
{
map.op(0x0000, 0x4fff).rom();
map.op(0x6000, 0x6bff).ram();
map.op(0x7000, 0x73ff).ram().share("sprite_ram"); /* sprite set 1 */
map.op(0x7400, 0x77ff).ram().w(dkong_videoram_w).share("video_ram");
map.op(0x7800, 0x780f).rw(i8257_device_read, i8257_device_write); /* P8257 control registers */
map.op(0x7c00, 0x7c00).portr("IN0").w("ls175.3d", latch8_device_write); /* IN0, sound CPU intf */
map.op(0x7c80, 0x7c80).portr("IN1").w(radarscp_grid_color_w); /* IN1 */
map.op(0x7d00, 0x7d00).r(dkong_in2_r); /* IN2 */
map.op(0x7d00, 0x7d07).w(latch8_device_bit0_w); /* Sound signals */
map.op(0x7d80, 0x7d80).portr("DSW0").w(dkong_audio_irq_w); /* DSW0 */
map.op(0x7d81, 0x7d81).w(radarscp_grid_enable_w);
map.op(0x7d82, 0x7d82).w(dkong_flipscreen_w);
map.op(0x7d83, 0x7d83).w(dkong_spritebank_w); /* 2 PSL Signal */
map.op(0x7d84, 0x7d84).w(nmi_mask_w);
map.op(0x7d85, 0x7d85).w(p8257_drq_w); /* P8257 ==> /DRQ0 /DRQ1 */
map.op(0x7d86, 0x7d87).w(dkong_palettebank_w);
}
/*************************************
*
* Main CPU memory handlers
*
*************************************/
void pacman_map(address_map map, device_t device)
{
pacman_state pacman_state = (pacman_state)device;
//A lot of games don't have an a15 at the cpu. Generally only games with a cpu daughter board can access the full 32k of romspace.
map.op(0x0000, 0x3fff).mirror(0x8000).rom();
map.op(0x4000, 0x43ff).mirror(0xa000).ram().w(pacman_state.pacman_videoram_w).share("videoram");
map.op(0x4400, 0x47ff).mirror(0xa000).ram().w(pacman_state.pacman_colorram_w).share("colorram");
map.op(0x4800, 0x4bff).mirror(0xa000).r(pacman_state.pacman_read_nop).nopw();
map.op(0x4c00, 0x4fef).mirror(0xa000).ram();
map.op(0x4ff0, 0x4fff).mirror(0xa000).ram().share("spriteram");
map.op(0x5000, 0x5007).mirror(0xaf38).w(pacman_state.mainlatch.target, pacman_state.ls259_device_write_d0_mainlatch);
map.op(0x5040, 0x505f).mirror(0xaf00).w(pacman_state.namco_sound.target, pacman_state.namco_device_pacman_sound_w);
map.op(0x5060, 0x506f).mirror(0xaf00).writeonly().share("spriteram2");
map.op(0x5070, 0x507f).mirror(0xaf00).nopw();
map.op(0x5080, 0x5080).mirror(0xaf3f).nopw();
map.op(0x50c0, 0x50c0).mirror(0xaf3f).w(pacman_state.watchdog.target, pacman_state.watchdog_timer_device_reset_w);
map.op(0x5000, 0x5000).mirror(0xaf3f).portr("IN0");
map.op(0x5040, 0x5040).mirror(0xaf3f).portr("IN1");
map.op(0x5080, 0x5080).mirror(0xaf3f).portr("DSW1");
map.op(0x50c0, 0x50c0).mirror(0xaf3f).portr("DSW2");
}
void main_nomcu_map(address_map map, device_t device)
{
map.op(0x0000, 0x5fff).rom();
map.op(0x6000, 0x7fff).bankr(m_mainbank);
map.op(0x8000, 0x87ff).ram();
map.op(0x8800, 0x8800).mirror(0x07fe).rw(fake_data_r, fake_data_w);
map.op(0x8801, 0x8801).mirror(0x07fe).r(fake_status_r);
map.op(0x9000, 0xbfff).w(characterram_w).share(m_characterram);
map.op(0xc000, 0xc3ff).ram();
map.op(0xc400, 0xc7ff).ram().share(m_videoram.op(0));
map.op(0xc800, 0xcbff).ram().share(m_videoram.op(1));
map.op(0xcc00, 0xcfff).ram().share(m_videoram.op(2));
map.op(0xd000, 0xd05f).ram().share(m_colscrolly);
map.op(0xd100, 0xd1ff).ram().share(m_spriteram);
map.op(0xd200, 0xd27f).mirror(0x0080).ram().share(m_paletteram);
map.op(0xd300, 0xd300).mirror(0x00ff).writeonly().share(m_video_priority);
map.op(0xd400, 0xd403).mirror(0x00f0).readonly_().share(m_collision_reg);
map.op(0xd404, 0xd404).mirror(0x00f3).r(gfxrom_r);
map.op(0xd408, 0xd408).mirror(0x00f0).portr("IN0");
map.op(0xd409, 0xd409).mirror(0x00f0).portr("IN1");
map.op(0xd40a, 0xd40a).mirror(0x00f0).portr("DSW1");
map.op(0xd40b, 0xd40b).mirror(0x00f0).portr("IN2");
map.op(0xd40c, 0xd40c).mirror(0x00f0).portr("IN3"); // Service
map.op(0xd40d, 0xd40d).mirror(0x00f0).portr("IN4");
map.op(0xd40e, 0xd40f).mirror(0x00f0).w(m_ay.op(0), (offset, data) => { m_ay.op(0).op0.address_data_w(offset, data); }); //map(0xd40e, 0xd40f).mirror(0x00f0).w(m_ay[0], FUNC(ay8910_device::address_data_w));
map.op(0xd40f, 0xd40f).mirror(0x00f0).r(m_ay.op(0), () => { return(m_ay.op(0).op0.data_r()); }); //map(0xd40f, 0xd40f).mirror(0x00f0).r(m_ay[0], FUNC(ay8910_device::data_r)); // DSW2 and DSW3
map.op(0xd500, 0xd505).mirror(0x00f0).writeonly().share(m_scroll);
map.op(0xd506, 0xd507).mirror(0x00f0).writeonly().share(m_colorbank);
map.op(0xd508, 0xd508).mirror(0x00f0).w(collision_reg_clear_w);
map.op(0xd509, 0xd50a).mirror(0x00f0).writeonly().share(m_gfxpointer);
map.op(0xd50b, 0xd50b).mirror(0x00f0).w(soundlatch_w);
map.op(0xd50c, 0xd50c).mirror(0x00f0).w(sound_semaphore2_w);
map.op(0xd50d, 0xd50d).mirror(0x00f0).w("watchdog", (data) => { ((watchdog_timer_device)subdevice("watchdog")).reset_w(data); }); //FUNC(watchdog_timer_device::reset_w));
map.op(0xd50e, 0xd50e).mirror(0x00f0).w(bankswitch_w);
map.op(0xd50f, 0xd50f).mirror(0x00f0).nopw();
map.op(0xd600, 0xd600).mirror(0x00ff).writeonly().share(m_video_mode);
map.op(0xd700, 0xdfff).noprw();
map.op(0xe000, 0xffff).rom();
}
protected virtual void internal_map(address_map map)
{
map.unmap_value_high();
map.op(0x0000, 0x0000).rw(port_r <u32_const_0>, port_latch_w <u32_const_0>);
map.op(0x0001, 0x0001).rw(port_r <u32_const_1>, port_latch_w <u32_const_1>);
map.op(0x0002, 0x0002).rw(port_r <u32_const_2>, port_latch_w <u32_const_2>);
map.op(0x0004, 0x0004).w(port_ddr_w <u32_const_0>);
map.op(0x0005, 0x0005).w(port_ddr_w <u32_const_1>);
map.op(0x0006, 0x0006).w(port_ddr_w <u32_const_2>);
map.op(0x0008, 0x0008).lrw8(() => { return(m_timer.tdr_r()); }, "", (data) => { m_timer.tdr_w(data); }, ""); //map(0x0008, 0x0008).lrw8(NAME([this]() { return m_timer.tdr_r(); }), NAME([this](u8 data) { m_timer.tdr_w(data); }));
map.op(0x0009, 0x0009).lrw8(() => { return(m_timer.tcr_r()); }, "", (data) => { m_timer.tcr_w(data); }, ""); //map(0x0009, 0x0009).lrw8(NAME([this]() { return m_timer.tcr_r(); }), NAME([this](u8 data) { m_timer.tcr_w(data); }));
// M68?05Px devices don't have Port D or the Miscellaneous register
if (m_port_mask[3] != 0xff)
{
map.op(0x0003, 0x0003).rw(port_r <u32_const_3>, port_latch_w <u32_const_3>);
map.op(0x000a, 0x000a).rw(misc_r, misc_w);
}
map.op(0x80 - m_ram_size, 0x007f).ram();
}
//auto in_p3_cb() { return m_in_port_func[2].bind(); }
//auto out_p3_cb() { return m_out_port_func[2].bind(); }
//auto in_p4_cb() { return m_in_port_func[3].bind(); }
//auto out_p4_cb() { return m_out_port_func[3].bind(); }
//auto out_sc2_cb() { return m_out_sc2_func.bind(); }
//auto out_ser_tx_cb() { return m_out_sertx_func.bind(); }
static void m6801_io(address_map map, m6801_cpu_device m6801) // FIXME: privatize this
{
map.op(0x0000, 0x0000).rw(m6801.ff_r, m6801.p1_ddr_w);
map.op(0x0001, 0x0001).rw(m6801.ff_r, m6801.p2_ddr_w);
map.op(0x0002, 0x0002).rw(m6801.p1_data_r, m6801.p1_data_w);
map.op(0x0003, 0x0003).rw(m6801.p2_data_r, m6801.p2_data_w);
map.op(0x0004, 0x0004).rw(m6801.ff_r, m6801.p3_ddr_w); // TODO: external in 6801 modes 0�& 6
map.op(0x0005, 0x0005).rw(m6801.ff_r, m6801.p4_ddr_w); // TODO: external in 6801 modes 0�
map.op(0x0006, 0x0006).rw(m6801.p3_data_r, m6801.p3_data_w); // TODO: external in 6801 modes 0�& 6
map.op(0x0007, 0x0007).rw(m6801.p4_data_r, m6801.p4_data_w); // TODO: external in 6801 modes 0�
map.op(0x0008, 0x0008).rw(m6801.tcsr_r, m6801.tcsr_w);
map.op(0x0009, 0x0009).rw(m6801.ch_r, m6801.ch_w);
map.op(0x000a, 0x000a).rw(m6801.cl_r, m6801.cl_w);
map.op(0x000b, 0x000b).rw(m6801.ocrh_r, m6801.ocrh_w);
map.op(0x000c, 0x000c).rw(m6801.ocrl_r, m6801.ocrl_w);
map.op(0x000d, 0x000d).r(m6801.icrh_r);
map.op(0x000e, 0x000e).r(m6801.icrl_r);
map.op(0x000f, 0x000f).rw(m6801.p3_csr_r, m6801.p3_csr_w); // TODO: external in 6801 modes 0� 5 & 6
map.op(0x0010, 0x0010).rw(m6801.sci_rmcr_r, m6801.sci_rmcr_w);
map.op(0x0011, 0x0011).rw(m6801.sci_trcsr_r, m6801.sci_trcsr_w);
map.op(0x0012, 0x0012).r(m6801.sci_rdr_r);
map.op(0x0013, 0x0013).w(m6801.sci_tdr_w);
map.op(0x0014, 0x0014).rw(m6801.rcr_r, m6801.rcr_w);
}
//virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
static void ram_map(address_map map, device_t owner)
{
throw new emu_unimplemented();
}
void program_11bit(address_map map, device_t owner)
{
map.op(0x000, 0x7ff).rom();
}
void data_7bit(address_map map, device_t owner)
{
map.op(0x00, 0x7f).ram();
}
void centiped_map(address_map map, device_t device)
{
centiped_base_map(map, device);
map.op(0x1000, 0x100f).rw("pokey", (offset) => { return(((pokey_device)subdevice("pokey")).read(offset)); }, (offset, data) => { ((pokey_device)subdevice("pokey")).write(offset, data); }); //rw("pokey", FUNC(pokey_device::read), FUNC(pokey_device::write));
}
//template <typename... T> address_map_bank_device& map(T &&... args) { set_addrmap(0, std::forward<T>(args)...); return *this; }
//address_map_bank_device& endianness(endianness_t endianness) { m_endianness = endianness; return *this; }
//address_map_bank_device& data_width(u8 data_width) { m_data_width = data_width; return *this; }
//address_map_bank_device& addr_width(u8 addr_width) { m_addr_width = addr_width; return *this; }
//address_map_bank_device& stride(u32 stride) { m_stride = stride; return *this; }
//address_map_bank_device& shift(u32 shift) { m_shift = shift; return *this; }
public void amap8(address_map map)
{
throw new emu_unimplemented();
}
public void amap16(address_map map)
{
map.op(0x00000000, 0xffffffff).rw((offset, mem_mask) => { return(read16(offset, mem_mask)); }, (offset, data, mem_mask) => { write16(offset, data, mem_mask); });
}
// only difference is fake_ replaced with actual MCU
void main_mcu_map(address_map map, device_t device)
{
main_nomcu_map(map, null);
map.op(0x8800, 0x8801).mirror(0x07fe).rw(m_mcu, (space, offset) => { return(m_mcu.op0.data_r(space, offset)); }, (offset, data) => { m_mcu.op0.data_w(offset, data); }); //map(0x8800, 0x8801).mirror(0x07fe).rw(m_mcu, FUNC(taito_sj_security_mcu_device::data_r), FUNC(taito_sj_security_mcu_device::data_w));
}