public bool CheckExitCondition(Z80CPU cpu, Z80CPU.InternalState internalState, Z80CPU.LifecycleEventType eventType)
{
if (eventType == Z80CPU.LifecycleEventType.InstructionStart)
{
if (internalState.InstructionOrigin.Address == instructionAddress)
{
return(true);
}
}
return(false);
}
public bool CheckExitCondition(Z80CPU cpu, Z80CPU.InternalState internalState, Z80CPU.LifecycleEventType eventType)
{
if (eventType == Z80CPU.LifecycleEventType.InstructionEnd)
{
if (internalInstructionCounterInitialValue < 0)
{
internalInstructionCounterInitialValue = internalState.InstructionCounter - 1;
}
if (internalState.InstructionCounter == internalInstructionCounterInitialValue + instructionCount)
{
return(true);
}
}
return(false);
}
private void LogCPUState(Z80CPU.InternalState internalState, Z80CPU.LifecycleEventType eventType)
{
// First column : event type
switch (eventType)
{
case Z80CPU.LifecycleEventType.HalfTState:
log.Append("HT");
break;
case Z80CPU.LifecycleEventType.InstructionEnd:
log.Append("IE");
break;
case Z80CPU.LifecycleEventType.InstructionStart:
log.Append("IS");
break;
case Z80CPU.LifecycleEventType.MachineCycleEnd:
log.Append("ME");
break;
case Z80CPU.LifecycleEventType.MachineCycleStart:
log.Append("MS");
break;
}
log.Append(';');
// Internal state : instruction, machine cycle, TStates
if (stateElementsToLog.HasFlag(CPUStateElements.InternalState))
{
log.Append(internalState.InstructionCounter);
log.Append(';');
if (internalState.InstructionOrigin.Source == InstructionSource.Memory)
{
log.Append(internalState.InstructionOrigin.Address);
log.Append(';');
log.Append(internalState.InstructionOrigin.OpCode != null ? internalState.InstructionOrigin.OpCode.InstructionText : "?");
log.Append(';');
}
else if (internalState.InstructionOrigin.Source == InstructionSource.Internal)
{
log.Append(""); // No address - internal
log.Append(';');
log.Append(internalState.Instruction.Type.OpCodeName);
log.Append(';');
}
else if (internalState.InstructionOrigin.Source == InstructionSource.InterruptingDevice)
{
log.Append(""); // No address - device
log.Append(';');
log.Append(internalState.InstructionOrigin.OpCode != null ? internalState.InstructionOrigin.OpCode.InstructionText : "?");
log.Append(';');
}
log.Append(internalState.MachineCycleIndex);
log.Append(';');
log.Append(internalState.MachineCycle != null ? internalState.MachineCycle.Type.ToString() : "?");
log.Append(';');
log.Append(internalState.HalfTStateIndex);
log.Append(';');
log.Append(internalState.TStateCounter);
log.Append(';');
}
// Micro instructions
if (stateElementsToLog.HasFlag(CPUStateElements.MicroInstructions))
{
for (int i = 0; i < cpu.MicroInstructions.Count; i++)
{
if (i > 0)
{
log.Append("|");
}
Z80Simulator.Instructions.MicroInstruction mi = cpu.MicroInstructions[i];
log.Append(mi.Type.Name);
if (mi.Parameter1 != null)
{
log.Append("(" + mi.Parameter1.ToString() + ")");
}
}
cpu.MicroInstructions.Clear();
log.Append(';');
}
// CPU registers
if (stateElementsToLog.HasFlag(CPUStateElements.Registers))
{
log.Append(String.Format("{0:X}", cpu.A));
log.Append(';');
log.Append(Convert.ToString(cpu.F, 2).PadLeft(8, '0'));
log.Append(';');
log.Append(String.Format("{0:X}", cpu.B));
log.Append(';');
log.Append(String.Format("{0:X}", cpu.C));
log.Append(';');
log.Append(String.Format("{0:X}", cpu.D));
log.Append(';');
log.Append(String.Format("{0:X}", cpu.E));
log.Append(';');
log.Append(String.Format("{0:X}", cpu.H));
log.Append(';');
log.Append(String.Format("{0:X}", cpu.L));
log.Append(';');
log.Append(String.Format("{0:X}", cpu.PC));
log.Append(';');
log.Append(String.Format("{0:X}", cpu.SP));
log.Append(';');
log.Append(String.Format("{0:X}", cpu.IX));
log.Append(';');
log.Append(String.Format("{0:X}", cpu.IY));
log.Append(';');
log.Append(String.Format("{0}", cpu.IFF1 ? 1 : 0));
log.Append(';');
log.Append(String.Format("{0}", cpu.IFF2 ? 1 : 0));
log.Append(';');
log.Append(String.Format("{0}", cpu.IM));
log.Append(';');
log.Append(String.Format("{0:X}", cpu.I));
log.Append(';');
log.Append(String.Format("{0:X}", cpu.R));
log.Append(';');
}
// Address and Data bus
if (stateElementsToLog.HasFlag(CPUStateElements.Buses))
{
log.Append(String.Format("{0:X}", cpu.Address.SampleValue()));
log.Append(';');
log.Append(String.Format("{0:X}", cpu.Data.SampleValue()));
log.Append(';');
}
// Control pins
if (stateElementsToLog.HasFlag(CPUStateElements.ControlPins))
{
log.Append(cpu.M1 == SignalState.LOW ? 0 : 1);
log.Append(';');
log.Append(cpu.MREQ == SignalState.LOW ? 0 : 1);
log.Append(';');
log.Append(cpu.IORQ == SignalState.LOW ? 0 : 1);
log.Append(';');
log.Append(cpu.RD == SignalState.LOW ? 0 : 1);
log.Append(';');
log.Append(cpu.WR == SignalState.LOW ? 0 : 1);
log.Append(';');
log.Append(cpu.RFSH == SignalState.LOW ? 0 : 1);
log.Append(';');
log.Append(cpu.HALT == SignalState.LOW ? 0 : 1);
log.Append(';');
log.Append(cpu.WAIT == SignalState.LOW ? 0 : 1);
log.Append(';');
log.Append(cpu.INT == SignalState.LOW ? 0 : 1);
log.Append(';');
log.Append(cpu.NMI == SignalState.LOW ? 0 : 1);
log.Append(';');
log.Append(cpu.RESET == SignalState.LOW ? 0 : 1);
log.Append(';');
log.Append(cpu.BUSACK == SignalState.LOW ? 0 : 1);
log.Append(';');
log.Append(cpu.BUSREQ == SignalState.LOW ? 0 : 1);
log.Append(';');
log.Append(cpu.CLK == SignalState.LOW ? 0 : 1);
log.Append(';');
}
log.AppendLine();
}
