private void SetSortModes(ref SortMode mode, ref HMode hMode, ref VMode vMode)
{
if (Mode.ToLower().Equals("row-wise"))
{
mode = SortMode.R;
}
else if (Mode.ToLower().Equals("column-wise"))
{
mode = SortMode.C;
}
else
{
throw new ArgumentException("Invalid value for Mode " + Mode + ". Use either row-wise or column-wise");
}
if (Horizontal.ToLower().Equals("left-to-right"))
{
hMode = HMode.L2R;
}
else if (Horizontal.ToLower().Equals("right-to-left"))
{
hMode = HMode.R2L;
}
else
{
throw new ArgumentException("Invalid value for Mode " + Horizontal + ". Use either left-to-right or right-to-left");
}
if (Vertical.ToLower().Equals("top-down"))
{
vMode = VMode.TD;
}
else if (Vertical.ToLower().Equals("bottom-up"))
{
vMode = VMode.BU;
}
else
{
throw new ArgumentException("Invalid value for Mode " + Horizontal + ". Use either top-down orbottom-up");
}
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE, FPGATypes.BackendType.Vivado);
SortMode mode = SortMode.Undefined;
HMode hMode = HMode.Undefined;
VMode vMode = VMode.Undefined;
SetSortModes(ref mode, ref hMode, ref vMode);
List <TileKey> keys = new List <TileKey>();
foreach (Tile clb in TileSelectionManager.Instance.GetSelectedTiles().Where(t =>
IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB) ||
IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.DSP) ||
IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.BRAM)))
{
keys.Add(clb.TileKey);
}
var preOrderedKey =
from key in keys
group key by(mode == SortMode.R?key.Y : key.X) into g
select g;
List <Tile> tilesInFinalOrder = new List <Tile>();
if (mode == SortMode.R)
{
foreach (IGrouping <int, TileKey> group in (vMode == VMode.TD ? preOrderedKey.OrderBy(g => g.Key) : preOrderedKey.OrderByDescending(g => g.Key)))
{
foreach (TileKey key in (hMode == HMode.L2R ? group.OrderBy(k => k.X) : group.OrderBy(k => k.X).Reverse()))
{
tilesInFinalOrder.Add(FPGA.FPGA.Instance.GetTile(key));
}
}
}
else
{
foreach (IGrouping <int, TileKey> group in (hMode == HMode.L2R ? preOrderedKey.OrderBy(g => g.Key) : preOrderedKey.OrderByDescending(g => g.Key)))
{
foreach (TileKey key in (vMode == VMode.TD ? group.OrderBy(k => k.Y) : group.OrderBy(k => k.Y).Reverse()))
{
tilesInFinalOrder.Add(FPGA.FPGA.Instance.GetTile(key));
}
}
}
// apply filter
tilesInFinalOrder.RemoveAll(t => !Regex.IsMatch(t.Location, Filter));
/*
* // check prior to plaecment of valid placement
* foreach (Tile t in tilesInFinalOrder)
* {
* LibraryElement libElement = Objects.Library.Instance.GetElement(this.LibraryElementName);
* StringBuilder errorList = null;
* bool placementOk = DesignRuleChecker.CheckLibraryElementPlacement(t, libElement, out errorList);
* if (!placementOk)
* {
* throw new ArgumentException("Macro " + this.LibraryElementName + " can not be placed at " + t + ": " + errorList.ToString());
* }
* }
*/
if (AutoClearModuleSlot)
{
LibraryElement libElement = Objects.Library.Instance.GetElement(LibraryElementName);
AutoClearModuleSlotBeforeInstantiation(libElement, tilesInFinalOrder);
}
foreach (Tile t in tilesInFinalOrder)
{
// check again prior to placement and now consider already placed tiles
/*
* StringBuilder errorList = null;
* bool placementOk = DesignRuleChecker.CheckLibraryElementPlacement(t, libElement, out errorList);
* if (!placementOk)
* {
* throw new ArgumentException("Library element " + this.LibraryElementName + " can not be placed at " + t + ": " + errorList.ToString());
* }*/
switch (FPGA.FPGA.Instance.BackendType)
{
case FPGATypes.BackendType.ISE:
AddISEInstantiation(t);
break;
case FPGATypes.BackendType.Vivado:
AddVivadoInstantiation(t);
break;
}
}
if (AutoFuse)
{
FuseNets fuseCmd = new FuseNets();
fuseCmd.NetlistContainerName = NetlistContainerName;
fuseCmd.Mute = Mute;
fuseCmd.Profile = Profile;
fuseCmd.PrintProgress = PrintProgress;
CommandExecuter.Instance.Execute(fuseCmd);
}
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE, FPGATypes.BackendType.Vivado);
SortMode mode = SortMode.Undefined;
HMode hMode = HMode.Undefined;
VMode vMode = VMode.Undefined;
SetSortModes(ref mode, ref hMode, ref vMode);
List <TileKey> keys = new List <TileKey>();
foreach (Tile tile in TileSelectionManager.Instance.GetSelectedTiles().Where(t =>
IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.Interconnect)))
{
keys.Add(tile.TileKey);
}
var preOrderedKey =
from key in keys
group key by(mode == SortMode.R?key.Y : key.X) into g
select g;
List <Tile> tilesInFinalOrder = new List <Tile>();
if (mode == SortMode.R)
{
foreach (IGrouping <int, TileKey> group in (vMode == VMode.TD ? preOrderedKey.OrderBy(g => g.Key) : preOrderedKey.OrderByDescending(g => g.Key)))
{
foreach (TileKey key in (hMode == HMode.L2R ? group.OrderBy(k => k.X) : group.OrderBy(k => k.X).Reverse()))
{
tilesInFinalOrder.Add(FPGA.FPGA.Instance.GetTile(key));
}
}
}
else
{
foreach (IGrouping <int, TileKey> group in (hMode == HMode.L2R ? preOrderedKey.OrderBy(g => g.Key) : preOrderedKey.OrderByDescending(g => g.Key)))
{
foreach (TileKey key in (vMode == VMode.TD ? group.OrderBy(k => k.Y) : group.OrderBy(k => k.Y).Reverse()))
{
tilesInFinalOrder.Add(FPGA.FPGA.Instance.GetTile(key));
}
}
}
int index = StartIndex;
foreach (Tile tile in tilesInFinalOrder)
{
foreach (string path in Paths)
{
string netName = Prefix + SignalName + "[" + index++ + "]";
PRLink link = new PRLink(tile, netName);
string[] portNames = path.Split(':');
foreach (string portName in portNames)
{
if (!tile.SwitchMatrix.Contains(portName))
{
throw new ArgumentException("Port " + portName + " not found on " + tile.Location);
}
link.Add(new Port(portName));
tile.BlockPort(portName, Tile.BlockReason.ExcludedFromBlocking);
}
PRLinkManager.Instance.Add(link);
}
}
}
