TCLParameterList FileName(TCLParameterList source)
{
if (source == null)
{
return(null);
}
return(new TCLParameterList(source.Params.Select(FileName).ToList()));
}
/// <summary>
/// <para>
/// Get a list of Pblocks in the current design<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: get_pblocks [-regexp] [-nocase] [-filter <arg>] [-of_objects <args>] [-include_nested_pblocks] [-quiet] [-verbose] [<patterns>]
/// <br/>
/// <para>
/// Gets a list of Pblocks defined in the current project that match a specific pattern. The default<br/>
/// command gets a list of all Pblocks in the project.<br/>
/// Note: To improve memory and performance, the get_* commands return a container list of a single type<br/>
/// of objects (e.g. cells, nets, pins, or ports). You can add new objects to the list (using lappend for instance),<br/>
/// but you can only add the same type of object that is currently in the list. Adding a different type of object,<br/>
/// or string, to the list is not permitted and will result in a Tcl error.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// </para>
/// <br/>
/// <para>
/// The following example gets a list of all Pblocks in the current project:<br/>
/// get_pblocks<br/>
/// This example gets a list of all Pblocks which do not have a Slice Range defined:<br/>
/// get_pblocks -filter {GRIDTYPES !~ SLICE}<br/>
/// The following example gets the Pblock assignments of the specified cell:<br/>
/// get_pblocks -of [get_cells CORE/BR_TOP/RLD67_MUX/REG_PMBIST_C1]<br/>
/// This example returns the specified Pblock, including any nested Pblocks:<br/>
/// get_pblocks -include_nested_pblocks usbTop<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 868<br/>
/// </para>
/// </summary>
/// <param name="regexp">(Optional) Patterns are full regular expressions</param>
/// <param name="nocase">(Optional) Perform case-insensitive matching (valid only when -regexp specified)</param>
/// <param name="filter">(Optional) Filter list with expression</param>
/// <param name="of_objects">(Optional) Get Pblocks of these cells</param>
/// <param name="include_nested_pblocks">(Optional) Display the the list of nested pblocks</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
/// <param name="patterns">(Optional) Match Pblock names against patterns Default: *</param>
/// <returns>list of Pblock objects</returns>
public TTCL get_pblocks(bool?regexp = null, bool?nocase = null, String filter = null, TCLParameterList of_objects = null, bool?include_nested_pblocks = null, bool?quiet = null, bool?verbose = null, TCLObject patterns = null)
{
// TCL Syntax: get_pblocks [-regexp] [-nocase] [-filter <arg>] [-of_objects <args>] [-include_nested_pblocks] [-quiet] [-verbose] [<patterns>]
_tcl.Entry(_builder.get_pblocks(regexp, nocase, filter, of_objects, include_nested_pblocks, quiet, verbose, patterns));
return(_tcl);
}
/// <summary>
/// <para>
/// Write QoR Suggestions to the given file<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: write_qor_suggestions [-strategy_dir <arg>] [-tcl_output_dir <arg>] [-force] [-of_objects <args>] [-quiet] [-verbose] <file>
/// <br/>
/// <para>
/// Write the QoR suggestions generated by the report_qor_suggestions command. You can<br/>
/// combine the suggestions from the latest report with suggestions read into the design with<br/>
/// read_qor_suggestions so that you can manage all suggestions in a single RQS file.<br/>
/// To write out specific QoR suggestions, use the -of_objects option. When this is not specified,<br/>
/// all suggestions will be written.<br/>
/// The recommended way to manage suggestions is using RQS objects. However, it is possible to<br/>
/// view and execute the commands using Tcl. Specifying the -tcl_output_dir option writes Tcl<br/>
/// scripts for the automated suggestions that are property based.<br/>
/// Implementation strategies that use machine learning to analyze the design can be generated<br/>
/// running report_qor_suggestions. If you specify the -strategy_dir option, multiple Tcl<br/>
/// files and one RQS file will be written for each strategy. The Tcl files aid integration into project or<br/>
/// non project flows. The main RQS file should not be used as the suggestions are contained in the<br/>
/// run specific files along with strategy information.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// This command returns the name of the output file created when successful, or returns an error if<br/>
/// it fails.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example reports QoR suggestions, then writes non-strategy suggestions to the<br/>
/// specified file.<br/>
/// report_qor_suggestions<br/>
/// write_qor_suggestions C:/Data/qor_results.rqs<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// The following example reports QoR suggestions, then writes both strategy and non-strategy<br/>
/// suggestions. It will create one RQS file for each strategy suggestion that exists, generating up to<br/>
/// three by default. Into each RQS file, it writes one strategy suggestion and all non-strategy<br/>
/// suggestions. This behavior means that for subsequent runs one RQS file per run is required.<br/>
/// report_qor_suggestions<br/>
/// write_qor_suggestions -strategy_dir C:/Data/strategy_dir C:/Data/<br/>
/// qor_suggestions.rqs<br/>
/// To make use of strategy suggestions, the directive for each implementation command<br/>
/// (opt_design, place_design, phys_opt_design, and route_design) must be set to RQS.<br/>
/// This can be configured automatically in project mode by sourcing the project mode Tcl script<br/>
/// generated for each RQS file in the strategy_dir. There is also a non-project example Tcl script<br/>
/// that demonstrates this requirement.<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1883<br/>
/// </para>
/// </summary>
/// <param name="file">
/// <para>
/// (Required)<br/>
/// QoR suggestions file Values: A filename with alphanumeric<br/>
/// characters and .rqs extension.<br/>
/// </para>
/// </param>
/// <param name="strategy_dir">
/// <para>
/// (Optional)<br/>
/// Directory to create Strategy RQS & TCL files Values: If<br/>
/// passed a directory path, for each strategy suggested one set<br/>
/// of RQS and TCL files will be generated.<br/>
/// </para>
/// </param>
/// <param name="tcl_output_dir">
/// <para>
/// (Optional)<br/>
/// Directory to create TCL files Values: TCL files for the QoR<br/>
/// suggestions will be generated in the provided directory.<br/>
/// </para>
/// </param>
/// <param name="force">(Optional) Overwrite existing suggestions file</param>
/// <param name="of_objects">(Optional) List of QoR suggestion objects</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL write_qor_suggestions(TCLObject file, String strategy_dir = null, String tcl_output_dir = null, bool?force = null, TCLParameterList of_objects = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: write_qor_suggestions [-strategy_dir <arg>] [-tcl_output_dir <arg>] [-force] [-of_objects <args>] [-quiet] [-verbose] <file>
_tcl.Entry(_builder.write_qor_suggestions(file, strategy_dir, tcl_output_dir, force, of_objects, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Set switching activity on specified objects or default types<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: set_switching_activity [-toggle_rate <arg>] [-default_toggle_rate <arg>] [-type <args>] [-all] [-static_probability <arg>] [-default_static_probability <arg>] [-signal_rate <arg>] [-hier] [-deassert_resets] [-quiet] [-verbose] [<objects>...]
/// <br/>
/// <para>
/// Sets the signal rate and the switching probability to be used when performing power estimation<br/>
/// on the current synthesized or implemented design. These include simple signal rate and simple<br/>
/// static probability on nets, ports, and pins; and state dependent static probabilities on cells.<br/>
/// Note: This command operates silently and does not return direct feedback of its operation.<br/>
/// The switching activity of a design affects both the static and dynamic power consumption. The<br/>
/// static power is often dependent on logic state transitions, and the dynamic power is directly<br/>
/// proportional to the toggle rate.<br/>
/// The set_switching_activity command can be used to specify default activity rates for the<br/>
/// whole design, or to define the activity of one or more signals in the design or on a specified<br/>
/// module.<br/>
/// The current switching activity attributes can be found by using the<br/>
/// report_switching_activity command. The values can be set to their default values by<br/>
/// using the reset_switching_activity command.<br/>
/// Note: The reset_switching_activity is used to reset switching activity for specified objects. Use the<br/>
/// set_switching_activity -default_toggle_rate or -default_static_probability to<br/>
/// change or reset these values.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example specifies a signal rate and switching probability for all ports, then reports<br/>
/// the switching attributes for those ports:<br/>
/// set_switching_activity -signal_rate 55 -static_probability .33 [get_ports]<br/>
/// report_switching_activity [get_ports]<br/>
/// The following example specifies the default switching probability for the current design:<br/>
/// set_switching_activity -default_static_probability .75<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// This example sets the specified toggle rate and static probability on all registers in the hierarchy<br/>
/// of "CPU/MEM":<br/>
/// set_switching_activity -type register -toggle_rate 0.4 \<br/>
/// -static_probability 0.5 [get_cells CPU/MEM]<br/>
/// This example sets the specified toggle rate and static probability on all registers in the hierarchy<br/>
/// of "CPU/" and underneath hierarchy:<br/>
/// set_switching_activity -type register -toggle_rate 0.4<br/>
/// -static_probability 0.5 -hier [get_cells CPU]<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1688<br/>
/// </para>
/// </summary>
/// <param name="toggle_rate">
/// <para>
/// (Optional)<br/>
/// Toggle rate (%) is the rate at which the output of<br/>
/// synchronous logic element switches compared to a given<br/>
/// clock input. It is modeled as a percentage between 0 - 200%.<br/>
/// A toggle rate of 100% means that on average the output<br/>
/// toggles once during every clock cycle, changing on either<br/>
/// the rising or falling clock edges, and making the effective<br/>
/// output signal frequency half of the clock frequency. Default:<br/>
/// 0.0<br/>
/// </para>
/// </param>
/// <param name="default_toggle_rate">
/// <para>
/// (Optional)<br/>
/// The default toggle rate to be used in power analysis on the<br/>
/// primary inputs of the design. The default toggle rate is set<br/>
/// on those primary input nets whose switching activity is not<br/>
/// specified by the user, simulation data or constraints of the<br/>
/// design. Valid values are: 0 <= value < 200. The default value<br/>
/// is 12.5. Default: 12.5<br/>
/// </para>
/// </param>
/// <param name="type">
/// <para>
/// (Optional)<br/>
/// Specify nodes in a specific category. List of valid type values:<br/>
/// io_output, io_bidir_enable, register, lut_ram, lut, dsp,<br/>
/// bram_enable, bram_wr_enable, gt_txdata, gt_rxdata.<br/>
/// </para>
/// </param>
/// <param name="all">
/// <para>
/// (Optional)<br/>
/// Used together with -type, set switching activity on -type nets<br/>
/// within an instance<br/>
/// </para>
/// </param>
/// <param name="static_probability">(Optional) Static probability value: 0 <= Value <= 1 Default: 0.5</param>
/// <param name="default_static_probability">
/// <para>
/// (Optional)<br/>
/// The default static probability to be used in power analysis<br/>
/// on the design. The default static probability is set on those<br/>
/// primary inputs whose switching activity is not specified by<br/>
/// the user, simulation data or constraints of the design. Valid<br/>
/// values are: 0 <= Value <= 1. The default value is 0.5. Default:<br/>
/// 0.5<br/>
/// </para>
/// </param>
/// <param name="signal_rate">
/// <para>
/// (Optional)<br/>
/// The number of times an element changed state (high-to-low<br/>
/// and low-to-high) per second. Xilinx tools express this as<br/>
/// millions of transitions per second (Mtr/s). Default: 0.0<br/>
/// </para>
/// </param>
/// <param name="hier">
/// <para>
/// (Optional)<br/>
/// Hierarchically sets the switching activity on a hierarchical<br/>
/// instance provided via <objects> option. This option should<br/>
/// be used only with <objects> option<br/>
/// </para>
/// </param>
/// <param name="deassert_resets">
/// <para>
/// (Optional)<br/>
/// A switch to elegantly auto deassert all set,reset,preset and<br/>
/// clear signals that do not have conflicted polarities<br/>
/// </para>
/// </param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
/// <param name="objects">
/// <para>
/// (Optional)<br/>
/// Objects to set switching activity on<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// </para>
/// </param>
public TTCL set_switching_activity(String toggle_rate = null, String default_toggle_rate = null, TCLParameterList type = null, bool?all = null, String static_probability = null, String default_static_probability = null, Int32?signal_rate = null, bool?hier = null, bool?deassert_resets = null, bool?quiet = null, bool?verbose = null, TCLObjectList objects = null)
{
// TCL Syntax: set_switching_activity [-toggle_rate <arg>] [-default_toggle_rate <arg>] [-type <args>] [-all] [-static_probability <arg>] [-default_static_probability <arg>] [-signal_rate <arg>] [-hier] [-deassert_resets] [-quiet] [-verbose] [<objects>...]
_tcl.Entry(_builder.set_switching_activity(toggle_rate, default_toggle_rate, type, all, static_probability, default_static_probability, signal_rate, hier, deassert_resets, quiet, verbose, objects));
return(_tcl);
}
/// <summary>
/// <para>
/// Set operating conditions for power estimation<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: set_operating_conditions [-voltage <args>] [-grade <arg>] [-process <arg>] [-junction_temp <arg>] [-ambient_temp <arg>] [-thetaja <arg>] [-thetasa <arg>] [-airflow <arg>] [-heatsink <arg>] [-thetajb <arg>] [-board <arg>] [-board_temp <arg>] [-board_layers <arg>] [-design_power_budget <arg>] [-supply_current_budget <args>] [-quiet] [-verbose]
/// <br/>
/// <para>
/// Sets the real-world operating conditions that are used when performing analysis of the design.<br/>
/// The environmental operating conditions of the device are used for power analysis when running<br/>
/// the report_power command.<br/>
/// Note: This command operates silently and does not return direct feedback of its operation.<br/>
/// Operating conditions can be restored to their default values with the use of the<br/>
/// reset_operating_conditions command.<br/>
/// Current operating conditions can be reported with the report_operating_conditions<br/>
/// command.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example specifies an industrial grade device with an ambient operating<br/>
/// temperature of 75 degrees C:<br/>
/// set_operating_conditions -grade industrial -ambient_temp 75<br/>
/// The following example sets the supply voltage Vccaux to a value of 1.9:<br/>
/// set_operating_conditions -voltage {Vccaux 1.89}<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// The following example sets the manufacturing process corner to maximum:<br/>
/// set_operating_conditions -process maximum<br/>
/// The following example sets the manufacturing process corner to maximum and the voltage<br/>
/// supply Vccint to 0.875:<br/>
/// set_operating_conditions -process maximum -voltage {Vccint 0.875}<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1663<br/>
/// </para>
/// </summary>
/// <param name="voltage">
/// <para>
/// (Optional)<br/>
/// List of voltage pairs, e.g., {name value}. Supported voltage<br/>
/// supplies vary by family.<br/>
/// </para>
/// </param>
/// <param name="grade">
/// <para>
/// (Optional)<br/>
/// Temperature grade. Supported values vary by family.<br/>
/// Default: commercial<br/>
/// </para>
/// </param>
/// <param name="process">(Optional) Process data: typical or maximum Default: typical</param>
/// <param name="junction_temp">(Optional) Junction Temperature (C): auto|degC Default: auto</param>
/// <param name="ambient_temp">(Optional) Ambient Temperature (C): default|degC Default: default</param>
/// <param name="thetaja">(Optional) ThetaJA (C/W): auto|degC/W Default: auto</param>
/// <param name="thetasa">(Optional) ThetaSA (C/W): auto|degC/W Default: auto</param>
/// <param name="airflow">(Optional) Airflow (LFM): 0 to 750 Default: varies by family</param>
/// <param name="heatsink">
/// <para>
/// (Optional)<br/>
/// Dimensions of heatsink: none, low, medium, high, custom<br/>
/// Default: medium<br/>
/// </para>
/// </param>
/// <param name="thetajb">(Optional) ThetaJB (C/W): auto|degC/W Default: auto</param>
/// <param name="board">(Optional) Board type: jedec, small, medium, large, custom Default: medium</param>
/// <param name="board_temp">(Optional) Board Temperature degC</param>
/// <param name="board_layers">(Optional) Board layers: 4to7, 8to11, 12to15, 16+ Default: 8to11</param>
/// <param name="design_power_budget">(Optional) Design Power Budget (W) Default: Unspecified</param>
/// <param name="supply_current_budget">
/// <para>
/// (Optional)<br/>
/// Sets list of supply current budget 'name value' pairs.<br/>
/// Supported voltage supplies vary by family.<br/>
/// </para>
/// </param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL set_operating_conditions(TCLParameterList voltage = null, String grade = null, String process = null, String junction_temp = null, String ambient_temp = null, String thetaja = null, String thetasa = null, String airflow = null, String heatsink = null, String thetajb = null, String board = null, String board_temp = null, String board_layers = null, String design_power_budget = null, TCLParameterList supply_current_budget = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: set_operating_conditions [-voltage <args>] [-grade <arg>] [-process <arg>] [-junction_temp <arg>] [-ambient_temp <arg>] [-thetaja <arg>] [-thetasa <arg>] [-airflow <arg>] [-heatsink <arg>] [-thetajb <arg>] [-board <arg>] [-board_temp <arg>] [-board_layers <arg>] [-design_power_budget <arg>] [-supply_current_budget <args>] [-quiet] [-verbose]
_tcl.Entry(_builder.set_operating_conditions(voltage, grade, process, junction_temp, ambient_temp, thetaja, thetasa, airflow, heatsink, thetajb, board, board_temp, board_layers, design_power_budget, supply_current_budget, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Reset operating conditions to tool default for power estimation<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: reset_operating_conditions [-voltage <args>] [-grade] [-process] [-junction_temp] [-ambient_temp] [-thetaja] [-thetasa] [-airflow] [-heatsink] [-thetajb] [-board] [-board_temp] [-board_layers] [-design_power_budget] [-supply_current_budget <args>] [-quiet] [-verbose]
/// <br/>
/// <para>
/// Resets the specified operating conditions to their default values. If no operating conditions are<br/>
/// specified, all operating conditions are reset to their default values.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// Operating conditions can be set using the set_operating_conditions command. The<br/>
/// current values can be determined using the report_operating_conditions command. The<br/>
/// environmental operating conditions of the device are used for power analysis when running the<br/>
/// report_power command, but are not used during timing analysis.<br/>
/// Note: This command returns nothing if successful, or returns an error if it fails.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example resets all the operating conditions for the design to their default setting:<br/>
/// reset_operating_conditions<br/>
/// The following example resets the junction, ambient, and board temperature for the design to<br/>
/// their default settings:<br/>
/// reset_operating_conditions -junction_temp -ambient_temp -board_temp<br/>
/// The following example resets the voltage supply Vccint to its default value:<br/>
/// reset_operating_conditions -voltage Vccint<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1504<br/>
/// </para>
/// </summary>
/// <param name="voltage">(Optional) Resets voltage value. Supported voltage supplies vary by family.</param>
/// <param name="grade">(Optional) Resets temperature grade</param>
/// <param name="process">(Optional) Resets process</param>
/// <param name="junction_temp">(Optional) Resets Junction Temperature</param>
/// <param name="ambient_temp">(Optional) Resets Ambient Temperature</param>
/// <param name="thetaja">(Optional) Resets ThetaJA</param>
/// <param name="thetasa">(Optional) Resets ThetaSA</param>
/// <param name="airflow">(Optional) Resets Airflow</param>
/// <param name="heatsink">(Optional) Resets dimensions of heatsink</param>
/// <param name="thetajb">(Optional) Resets ThetaJB</param>
/// <param name="board">(Optional) Resets Board type</param>
/// <param name="board_temp">(Optional) Resets Board Temperature</param>
/// <param name="board_layers">(Optional) Resets Board layers</param>
/// <param name="design_power_budget">(Optional) Design Power Budget (W)</param>
/// <param name="supply_current_budget">
/// <para>
/// (Optional)<br/>
/// Resets list of supply current budget 'name value' pairs.<br/>
/// Supported voltage supplies vary by family.<br/>
/// </para>
/// </param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL reset_operating_conditions(TCLParameterList voltage = null, bool?grade = null, bool?process = null, bool?junction_temp = null, bool?ambient_temp = null, bool?thetaja = null, bool?thetasa = null, bool?airflow = null, bool?heatsink = null, bool?thetajb = null, bool?board = null, bool?board_temp = null, bool?board_layers = null, bool?design_power_budget = null, TCLParameterList supply_current_budget = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: reset_operating_conditions [-voltage <args>] [-grade] [-process] [-junction_temp] [-ambient_temp] [-thetaja] [-thetasa] [-airflow] [-heatsink] [-thetajb] [-board] [-board_temp] [-board_layers] [-design_power_budget] [-supply_current_budget <args>] [-quiet] [-verbose]
_tcl.Entry(_builder.reset_operating_conditions(voltage, grade, process, junction_temp, ambient_temp, thetaja, thetasa, airflow, heatsink, thetajb, board, board_temp, board_layers, design_power_budget, supply_current_budget, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Write out one or more DRC/METHODOLOGY/CDC message waivers in command form<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: write_waivers [-type <arg>] [-objects <args>] [-return_string] [-force] [-quiet] [-verbose] [<file>]
/// <br/>
/// <para>
/// To save waivers from one design session to the next, you must use write_waivers to create<br/>
/// an XDC file of the waiver commands, and read_xdc to read those waivers back into the design<br/>
/// when it is reopened.<br/>
/// </para>
/// <br/>
/// <para>
/// This example writes all waivers in the current design:<br/>
/// write_waivers C:/Data/design_waivers.xdc<br/>
/// The following example writes only DRC type waivers:<br/>
/// write_waivers -type DRC C:/Data/drc_waivers.xdc<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1898<br/>
/// </para>
/// </summary>
/// <param name="file">(Required) Name of file to write waivers</param>
/// <param name="type">(Optional) Type of waiver(s) - ALL, DRC, METHODOLOGY, CDC to write</param>
/// <param name="objects">(Optional) List of DRC/METHODOLOGY/CDC waiver objects to be written</param>
/// <param name="return_string">(Optional) Return report results as a string object</param>
/// <param name="force">(Optional) Overwrite existing file</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL write_waivers(TCLObject file, String type = null, TCLParameterList objects = null, bool?return_string = null, bool?force = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: write_waivers [-type <arg>] [-objects <args>] [-return_string] [-force] [-quiet] [-verbose] [<file>]
_tcl.Entry(_builder.write_waivers(file, type, objects, return_string, force, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Create a DRC/METHODOLOGY/CDC message waiver<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: create_waiver [-type <arg>] [-id <arg>] [-objects <args>] [-from <args>] [-to <args>] [-strings <args>] [-of_objects <args>] [-user <arg>] -description <arg> [-tags <arg>] [-timestamp <arg>] [-scoped] [-quiet] [-verbose]
/// <br/>
/// <para>
/// After report_drc, report_methodology, or report_cdc commands are run, they return<br/>
/// messages of specific violations or conditions found in the design. These violations can prevent<br/>
/// the design from progressing until they have been resolved or addressed in some way. The<br/>
/// create_waiver command lets you select individual violations or specific checks that can be<br/>
/// waived for a design, letting you move forward in the design flow.<br/>
/// IMPORTANT! Use caution when waiving violations. Waivers may let you proceed in the design flow, but<br/>
/// also let you create a design that is fundamentally flawed.<br/>
/// The user creating the waiver is required to provide a user ID and description in the<br/>
/// create_waiver command in order to provide some history of the waiver.<br/>
/// A waiver must be specified for an individual DRC or methodology violation, or for a specific DRC<br/>
/// or methodology check, or for a CDC path. The waiver must be assigned to a specific object, or<br/>
/// specific violation ID, or for paths using -from/-to arguments. The form of the<br/>
/// create_waiver command varies depending on the check, violation, or object being waived, as<br/>
/// shown in the examples below.<br/>
/// TIP: Although many of the arguments are described as optional, some form of identifier is required to<br/>
/// associate the waiver with its target.<br/>
/// To save waivers from one design session to the next, you must use write_waivers to create<br/>
/// an XDC file of the waiver commands, and read_xdc to read those waivers back into the design<br/>
/// when it is reopened.<br/>
/// After creating a waiver, you will need to rerun the DRC, methodology, or CDC report to have the<br/>
/// waiver considered in the analysis. To see what waivers are in place in the current design you can<br/>
/// use the report_waivers command. In addition, the report_drc, report_methodology,<br/>
/// and report_cdc commands have options to run the reports on waived violations or checks.<br/>
/// Use the delete_waivers command to remove waivers from the design.<br/>
/// </para>
/// <br/>
/// <para>
/// This example creates a waiver for a methodology check based on the specified ID:<br/>
/// create_waiver -id TIMING-18 -user samwise -description {waive rule check}<br/>
/// The following example creates a DRC check waiver for the indicated ID on the specified list of<br/>
/// port objects, and provides the timestamp in local time:<br/>
/// create_waiver -type DRC -id UCIO-1 -user samwise -desc {waiving DRC<br/>
/// violation} \<br/>
/// -objects [get_ports {src_in* dest_out*}] \<br/>
/// -timestamp [clock format [clock seconds] -gmt 0]<br/>
/// The following example creates a waiver for specific CDC paths in the design, defined by the -<br/>
/// from/-to arguments:<br/>
/// create_waiver -type CDC -id CDC-6 -user samwise \<br/>
/// -description {Paths to be re-tested later}\<br/>
/// -from [list [get_pins {inst_xpm_grey/src_gray_ff_reg[3]/C \<br/>
/// inst_xpm_grey/src_gray_ff_reg[16]/C \<br/>
/// inst_xpm_grey/src_gray_ff_reg[22]/C \<br/>
/// inst_xpm_grey/src_gray_ff_reg[25]/C}] ] \<br/>
/// -to [list [get_pins {inst_xpm_grey/dest_graysync_ff_reg[0][1]/D \<br/>
/// inst_xpm_grey/dest_graysync_ff_reg[0][6]/D \<br/>
/// inst_xpm_grey/dest_graysync_ff_reg[0][9]/D \<br/>
/// inst_xpm_grey/dest_graysync_ff_reg[0][24]/D}] ]<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 367<br/>
/// </para>
/// </summary>
/// <param name="description">(Required) Description string of the cause for the waiver</param>
/// <param name="type">(Optional) Type of waiver - DRC, METHODOLOGY, CDC</param>
/// <param name="id">
/// <para>
/// (Optional)<br/>
/// ID of the DRC/METHODOLOGY/CDC message being waived,<br/>
/// not needed for -of_objects use<br/>
/// </para>
/// </param>
/// <param name="objects">
/// <para>
/// (Optional)<br/>
/// List of inserted message objects for which a DRC/<br/>
/// METHODOLOGY waiver will be set (i.e. %ELG, %SIG, etc. for<br/>
/// cells or nets, etc., sites, etc., or '*CELL', '*NET', '*SITE', etc.<br/>
/// as wildcards<br/>
/// </para>
/// </param>
/// <param name="from">
/// <para>
/// (Optional)<br/>
/// List of source (driver) pins or ports (or '*PORT', '*PIN' as<br/>
/// wildcard) for which a CDC waiver will be set<br/>
/// </para>
/// </param>
/// <param name="to">
/// <para>
/// (Optional)<br/>
/// List of target (load) pins or ports (or '*PORT', '*PIN' as<br/>
/// wildcard) for which a CDC waiver will be set<br/>
/// </para>
/// </param>
/// <param name="strings">
/// <para>
/// (Optional)<br/>
/// List of inserted message string values for which a DRC/<br/>
/// METHODOLOGY waiver will be set (i.e. %STR for strings, or<br/>
/// '*' as wildcard)<br/>
/// </para>
/// </param>
/// <param name="of_objects">
/// <para>
/// (Optional)<br/>
/// List of DRC/METHODOLOGY/CDC violation objects for which<br/>
/// waiver(s) will be set<br/>
/// </para>
/// </param>
/// <param name="user">
/// <para>
/// (Optional)<br/>
/// Name of the user creating the waiver (required, but if not<br/>
/// specified, the waivers will take the USER name from the<br/>
/// environment if it is available)<br/>
/// </para>
/// </param>
/// <param name="tags">
/// <para>
/// (Optional)<br/>
/// Optional list of one or more tags to aid in subsequent<br/>
/// waiver identification or categorization<br/>
/// </para>
/// </param>
/// <param name="timestamp">
/// <para>
/// (Optional)<br/>
/// Timestamp of waiver - for restaining the original time of a<br/>
/// waiver being (re)created after being written<br/>
/// </para>
/// </param>
/// <param name="scoped">
/// <para>
/// (Optional)<br/>
/// Flag waiver to interpret object wildcards as scoped to the<br/>
/// current_instance that is set<br/>
/// </para>
/// </param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">
/// <para>
/// (Optional)<br/>
/// Suspend message limits during command execution<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// </para>
/// </param>
/// <returns>waiver</returns>
public TTCL create_waiver(String description, String type = null, String id = null, TCLParameterList objects = null, TCLParameterList from = null, TCLParameterList to = null, TCLParameterList strings = null, TCLParameterList of_objects = null, String user = null, String tags = null, String timestamp = null, bool?scoped = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: create_waiver [-type <arg>] [-id <arg>] [-objects <args>] [-from <args>] [-to <args>] [-strings <args>] [-of_objects <args>] [-user <arg>] -description <arg> [-tags <arg>] [-timestamp <arg>] [-scoped] [-quiet] [-verbose]
_tcl.Entry(_builder.create_waiver(description, type, id, objects, from, to, strings, of_objects, user, tags, timestamp, scoped, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Unhighlight objects that are currently highlighted<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: unhighlight_objects [-color_index <arg>] [-rgb <args>] [-color <arg>] [-leaf_cells] [-quiet] [-verbose] [<objects>]
/// <br/>
/// <para>
/// This command is for use in GUI mode. This command unhighlights the specified object or objects<br/>
/// that were previously highlighted by the highlight_objects command.<br/>
/// This command supports the color options as specified below. These options can be used to<br/>
/// unhighlight all objects currently highlighted in the specified color. See the example below.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example unhighlights the specified cell objects:<br/>
/// unhighlight_objects -leaf_cells [get_cells cpuEngine/*]<br/>
/// The following example unhighlights all objects currently highlighted in the color yellow:<br/>
/// unhighlight_objects -color yellow<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1750<br/>
/// </para>
/// </summary>
/// <param name="color_index">(Optional) Color index</param>
/// <param name="rgb">(Optional) RGB color index list</param>
/// <param name="color">(Optional) Valid values are red green blue magenta yellow cyan and orange</param>
/// <param name="leaf_cells">(Optional) Leaf cells</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
/// <param name="objects">(Optional) Objects to unhighlight</param>
public TTCL unhighlight_objects(String color_index = null, TCLParameterList rgb = null, String color = null, bool?leaf_cells = null, bool?quiet = null, bool?verbose = null, TCLObject objects = null)
{
// TCL Syntax: unhighlight_objects [-color_index <arg>] [-rgb <args>] [-color <arg>] [-leaf_cells] [-quiet] [-verbose] [<objects>]
_tcl.Entry(_builder.unhighlight_objects(color_index, rgb, color, leaf_cells, quiet, verbose, objects));
return(_tcl);
}
/// <summary>
/// <para>
/// Get marked objects<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: get_marked_objects [-rgb <args>] [-color <arg>] [-quiet] [-verbose]
/// <br/>
/// <para>
/// Get the marked objects in the current design open in the Vivado IDE. Objects can be marked<br/>
/// with the mark_objects command.<br/>
/// You can get all marked objects in the design, or specify marked objects by color, or by RGB value.<br/>
/// Note: This Tcl command works only when Vivado is run in GUI mode.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example gets all the marked objects in the current design:<br/>
/// get_marked_objects<br/>
/// The following example gets the object in the current design that are marked in the specified<br/>
/// color:<br/>
/// get_marked_objects -color yellow<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 827<br/>
/// </para>
/// </summary>
/// <param name="rgb">(Optional) RGB color index list</param>
/// <param name="color">(Optional) Valid values are red green blue magenta yellow cyan and orange</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
/// <returns>list of marked objects</returns>
public TTCL get_marked_objects(TCLParameterList rgb = null, String color = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: get_marked_objects [-rgb <args>] [-color <arg>] [-quiet] [-verbose]
_tcl.Entry(_builder.get_marked_objects(rgb, color, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Generate simulation scripts of the design and launch steps for the target simulator.<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: launch_simulation [-step <arg>] [-simset <arg>] [-mode <arg>] [-type <arg>] [-scripts_only] [-of_objects <args>] [-absolute_path] [-install_path <arg>] [-gcc_install_path <arg>] [-noclean_dir] [-quiet] [-verbose]
/// <br/>
/// <para>
/// Launch a simulator to perform analysis and verification of a design.<br/>
/// The launch_simulation command creates a script file for the target simulator and then<br/>
/// executes this file in the simulation run directory. The simulation results are saved in the log files<br/>
/// created in the run directory.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// To run simulation for a specific simulator, you must first define the target simulator by setting the<br/>
/// TARGET_SIMULATOR property on the design project:<br/>
/// set_property TARGET_SIMULATOR <name> [current_project]<br/>
/// The TARGET_SIMULATOR property can have a value of XSim, ModelSim, IES, Xcelium, VCS,<br/>
/// Riviera, or ActiveHDL. The default value is XSim, the Vivado simulator.<br/>
/// The target simulator can also be defined from the Vivado IDE. Create or open a project, select<br/>
/// Tools → Settings → Simulation menu item, and select the Target simulator from the drop-down<br/>
/// menu. The available choices are: Vivado simulator, ModelSim Simulator, Questa Advanced<br/>
/// Simulator, Incisive Enterprise Simulator (IES), Xcelium Parallel Simulator, Verilog Compiler<br/>
/// Simulator (VCS), Riviera-PRO Simulator, and Active-HDL Simulator.<br/>
/// TIP: Some of these simulators are only available on Linux and some are only available on Windows.<br/>
/// The launch_simulation command uses a three-step process comprised of compile,<br/>
/// elaborate, and simulate steps. A script file for the target simulator is created for each step in the<br/>
/// process, (compile.bat, elaborate.bat, simulate.bat), and written to the simulation run<br/>
/// directory.<br/>
/// TIP: On Linux the script files are named with the .sh suffix instead of .bat.<br/>
/// By default, launch_simulation will run these script files in sequence to run the simulation.<br/>
/// You can create the scripts without running them by using the -scripts_only option.<br/>
/// This command returns a transcript of its process, or returns an error if it fails.<br/>
/// </para>
/// <br/>
/// <para>
/// The following commands run behavioral simulation of the design using the Vivado simulator:<br/>
/// set_property target_simulator "XSim" [current_project]<br/>
/// launch_simulation<br/>
/// The following commands run post-synthesis functional simulation of the design using the<br/>
/// ModelSim Simulator:<br/>
/// set_property target_simulator "ModelSim" [current_project]<br/>
/// launch_simulation -mode "post-synthesis" -type "functional"<br/>
/// The following commands run post-implementation functional simulation of the design using the<br/>
/// Cadence IES Simulator:<br/>
/// set_property target_simulator "IES" [current_project]<br/>
/// launch_simulation -mode "post-implementation" -type "functional"<br/>
/// The following commands run post-implementation timing simulation of the design using the<br/>
/// Synopsys VCS Simulator:<br/>
/// set_property target_simulator "VCS" [current_project]<br/>
/// launch_simulation -mode "post-implementation" -type "timing"<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// The following command generates behavioral simulation scripts for the target simulator in the<br/>
/// simulation run directory:<br/>
/// launch_simulation -scripts_only<br/>
/// The following commands run behavioral simulation flow of the design for the "my_simset"<br/>
/// simulation fileset for the target simulator in the simulation run directory:<br/>
/// launch_simulation -simset [get_filesets my_simset]<br/>
/// The following command runs behavioral simulation flow for the char_fifo.xci IP for the<br/>
/// target simulator in the simulation run directory, and does not clean up prior simulation files:<br/>
/// launch_simulation -noclean_dir -of_objects [get_files char_fifo.xci]<br/>
/// The following command generates absolute paths for the source files in the generated script files:<br/>
/// launch_simulation -absolute_path<br/>
/// The following command will pick the simulator tools from the specified installation path instead<br/>
/// of from the PATH variable:<br/>
/// launch_simulation -install_path /tools/ius/13.20.005/tools/bin<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1017<br/>
/// </para>
/// </summary>
/// <param name="step">
/// <para>
/// (Optional)<br/>
/// Launch a simulation step. Values: all, compile, elaborate,<br/>
/// simulate. Default:all (launch all steps). Default: all<br/>
/// </para>
/// </param>
/// <param name="simset">(Optional) Name of the simulation fileset</param>
/// <param name="mode">
/// <para>
/// (Optional)<br/>
/// Simulation mode. Values: behavioral, post-synthesis, post-implementation Default: behavioral<br/>
/// </para>
/// </param>
/// <param name="type">
/// <para>
/// (Optional)<br/>
/// Netlist type. Values: functional, timing. This is only<br/>
/// applicable when mode is set to post-synthesis or post-implementation<br/>
/// </para>
/// </param>
/// <param name="scripts_only">(Optional) Only generate scripts</param>
/// <param name="of_objects">
/// <para>
/// (Optional)<br/>
/// Generate compile order file for this object (applicable with -<br/>
/// scripts_only option only)<br/>
/// </para>
/// </param>
/// <param name="absolute_path">(Optional) Make design source file paths in 'absolute' format</param>
/// <param name="install_path">(Optional) Custom installation directory path</param>
/// <param name="gcc_install_path">
/// <para>
/// (Optional)<br/>
/// Specify GNU compiler installation directory path for the g+<br/>
/// +/gcc executables<br/>
/// </para>
/// </param>
/// <param name="noclean_dir">(Optional) Do not remove simulation run directory files</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL launch_simulation(launch_simulation_step?step = null, String simset = null, launch_simulation_mode?mode = null, launch_simulation_type?type = null, bool?scripts_only = null, TCLParameterList of_objects = null, bool?absolute_path = null, String install_path = null, String gcc_install_path = null, bool?noclean_dir = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: launch_simulation [-step <arg>] [-simset <arg>] [-mode <arg>] [-type <arg>] [-scripts_only] [-of_objects <args>] [-absolute_path] [-install_path <arg>] [-gcc_install_path <arg>] [-noclean_dir] [-quiet] [-verbose]
_tcl.Entry(_builder.launch_simulation(step, simset, mode, type, scripts_only, of_objects, absolute_path, install_path, gcc_install_path, noclean_dir, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Set property on object(s)<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: set_property [-dict <args>] [-quiet] [-verbose] <name> <value> <objects>...
/// <br/>
/// <para>
/// Assigns the defined property <name> and <value> to the specified <objects>.<br/>
/// This command can be used to define any property on an object in the design. Each object has a<br/>
/// set of predefined properties that have expected values, or a range of values. The set_property<br/>
/// command can be used to define the values for these properties. To determine the defined set of<br/>
/// properties on an object, use report_property, list_property, or<br/>
/// list_property_values.<br/>
/// You can also define custom properties for an object, by specifying a unique <name> and <value><br/>
/// pair for the object. If an object has custom properties, these will also be reported by the<br/>
/// report_property and list_property commands.<br/>
/// This command returns nothing if successful, and an error if it fails.<br/>
/// TIP: You can use the get_property command to validate any properties that have been set on an<br/>
/// object.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// </para>
/// <br/>
/// <para>
/// Create a user-defined boolean property, TRUTH, for cell objects, and set the property on a cell:<br/>
/// create_property -type bool truth cell<br/>
/// set_property truth false [lindex [get_cells] 1]<br/>
/// Use the -dict option to specify multiple properties at one time on the current design:<br/>
/// set_property -dict "POST_CRC enable POST_CRC_ACTION correct_and_continue"<br/>
/// \<br/>
/// [current_design]<br/>
/// The following example sets the TOP property of the current fileset to define the top module of<br/>
/// the project:<br/>
/// set_property top fftTop [current_fileset]<br/>
/// set_property top_file {C:/Data/sources/fftTop.v} [current_fileset]<br/>
/// Note: Defining the top module requires the TOP property to be set to the desired hierarchical block in the<br/>
/// source fileset of the current project. In the preceding example TOP is the property name, fftTop is the<br/>
/// value, and current_fileset is the object. In addition, the TOP_FILE property should be defined to point to<br/>
/// the data source for the top module.<br/>
/// This example shows how to set a property value that includes the dash character, '-'. The dash<br/>
/// can cause the tool to interpret the value as a new command argument, rather than part of the<br/>
/// value being specified, and will cause an error as shown. In this case, you must use the explicit<br/>
/// form of the positional arguments in the set_property command:<br/>
/// set_property {XELAB.MORE_OPTIONS} {-pulse_e_style ondetect} \<br/>
/// [get_filesets sim_1]<br/>
/// ERROR: [Common 17-170] Unknown option '-pulse_e_style ondetect',<br/>
/// please type 'set_property -help' for usage info.<br/>
/// set_property -name {XELAB.MORE_OPTIONS} -value {-pulse_e_style ondetect}\<br/>
/// -objects [get_filesets sim_1]<br/>
/// The following example sets the internal VREF property value for the specified IO Bank:<br/>
/// set_property internal_vref {0.75} [get_iobanks 0]<br/>
/// The following example defines a DCI Cascade by setting the DCI_CASCADE property for the<br/>
/// specified IO Bank:<br/>
/// set_property DCI_CASCADE {14} [get_iobanks 0 ]<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// The following example configures the synth_1 run, setting options for Vivado Synthesis 2013,<br/>
/// and then launches the synthesis run:<br/>
/// set_property flow {Vivado Synthesis 2016} \<br/>
/// [get_runs synth_1]<br/>
/// set_property STEPS.SYNTH_DESIGN.ARGS.GATED_CLOCK_CONVERSION on \<br/>
/// [get_runs synth_1]<br/>
/// set_property STEPS.SYNTH_DESIGN.ARGS.FSM_EXTRACTION one_hot \<br/>
/// [get_runs synth_1]<br/>
/// launch_runs synth_1<br/>
/// This example is the same as the prior example, except that it uses the -dict option to set all the<br/>
/// properties on the synthesis run in a single set_property command:<br/>
/// set_property -dict [ list flow {Vivado Synthesis 2016} \<br/>
/// STEPS.SYNTH_DESIGN.ARGS.GATED_CLOCK_CONVERSION on \<br/>
/// STEPS.SYNTH_DESIGN.ARGS.FSM_EXTRACTION \<br/>
/// one_hot ] [get_runs synth_1]<br/>
/// launch_runs synth_1<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1682<br/>
/// </para>
/// </summary>
/// <param name="name">(Required) Name of property to set. Not valid with -dict option</param>
/// <param name="value">(Required) Value of property to set. Not valid with -dict option</param>
/// <param name="objects">(Required) Objects to set properties on</param>
/// <param name="dict">(Optional) list of name/value pairs of properties to set</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL set_property(TCLObject name, TCLObject value, TCLObjectList objects, TCLParameterList dict = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: set_property [-dict <args>] [-quiet] [-verbose] <name> <value> <objects>...
_tcl.Entry(_builder.set_property(name, value, objects, dict, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Create property for class of objects(s)<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: create_property [-description <arg>] [-type <arg>] [-enum_values <args>] [-default_value <arg>] [-file_types <args>] [-display_text <arg>] [-quiet] [-verbose] <name> <class>
/// <br/>
/// <para>
/// Creates a new property of the <type> specified with the user-defined <name> for the specified<br/>
/// <class> of objects. The property that is created can be assigned to an object of the specified class<br/>
/// with the set_property command, but is not automatically associated with all objects of that<br/>
/// class.<br/>
/// The report_property -all command will not report the newly created property for an<br/>
/// object of the specified class until the property has been assigned to that object.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// </para>
/// <br/>
/// <para>
/// The following example defines a property called PURPOSE for cell objects:<br/>
/// create_property PURPOSE cell<br/>
/// Note: Because the -type was not specified, the value will default to strings.<br/>
/// The following example creates a pin property called COUNT which holds an Integer value:<br/>
/// create_property -type int COUNT pin<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 347<br/>
/// </para>
/// </summary>
/// <param name="name">(Required) Name of property to create</param>
/// <param name="class">
/// <para>
/// (Required)<br/>
/// Object type to create property for; valid values are: design,<br/>
/// net, cell, pin, port, pblock, interface, fileset<br/>
/// </para>
/// </param>
/// <param name="description">(Optional) Description of property</param>
/// <param name="type">
/// <para>
/// (Optional)<br/>
/// Type of property to create; valid values are: string, int, long,<br/>
/// double, bool, enum, file Default: string<br/>
/// </para>
/// </param>
/// <param name="enum_values">(Optional) Enumeration values</param>
/// <param name="default_value">(Optional) Default value of type string</param>
/// <param name="file_types">(Optional) File type extensions (without the dot)</param>
/// <param name="display_text">(Optional) Text to display when selecting the file in file browser</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
/// <returns>The property that was created if success, "" if failure</returns>
public TTCL create_property(TCLObject name, TCLObject @class, String description = null, String type = null, TCLParameterList enum_values = null, String default_value = null, TCLParameterList file_types = null, String display_text = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: create_property [-description <arg>] [-type <arg>] [-enum_values <args>] [-default_value <arg>] [-file_types <args>] [-display_text <arg>] [-quiet] [-verbose] <name> <class>
_tcl.Entry(_builder.create_property(name, @class, description, type, enum_values, default_value, file_types, display_text, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Add power sources to power Rail<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: add_to_power_rail [-power_sources <args>] [-quiet] [-verbose] <power_rail>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 59<br/>
/// </para>
/// </summary>
/// <param name="power_rail">(Required) Power rail to add sources to</param>
/// <param name="power_sources">(Optional) List of power_sources to add. Can be power rails and/or power supplies</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL add_to_power_rail(TCLObject power_rail, TCLParameterList power_sources = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: add_to_power_rail [-power_sources <args>] [-quiet] [-verbose] <power_rail>
_tcl.Entry(_builder.add_to_power_rail(power_rail, power_sources, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Move, resize, add and remove Pblock site-range constraints<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: resize_pblock [-add <args>] [-remove <args>] [-from <args>] [-to <args>] [-replace] [-locs <arg>] [-quiet] [-verbose] <pblock>
/// <br/>
/// <para>
/// Place, resize, move, or remove the specified Pblock. The Pblock must have been created using<br/>
/// the create_pblock command.<br/>
/// A Pblock consists of a group of cells that can be assigned to one or more independent or<br/>
/// overlapping rectangles. Using the various options defined below, you can add sites to a rectangle,<br/>
/// or remove sites from a rectangle, or define a new rectangle to be associated with an existing<br/>
/// Pblock.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example resizes the Pblock by adding a range of SLICEs, and removing other<br/>
/// SLICEs, but keeps all instances placed at their current location:<br/>
/// resize_pblock block3 -add SLICE_X6Y67:SLICE_X11Y71 \<br/>
/// -remove SLICE_X6Y71:SLICE_X7Y71 -locs keep_all<br/>
/// This example create a Pblock region, and defines the Pblock area by adding a range of<br/>
/// CLOCKREGIONs:<br/>
/// create_pblock pblock_1<br/>
/// resize_pblock pblock_1 -add {CLOCKREGION_X0Y10:CLOCKREGION_X1Y11}<br/>
/// The following example moves the specified Pblock by adding a range of SLICEs, removing the<br/>
/// existing range of SLICEs, and trims any placed logic that falls outside the new Pblock. Then it<br/>
/// adds a new range of SLICEs and block ram to the specified Pblock in a second separate rectangle:<br/>
/// resize_pblock block3 -add SLICE_X3Y8:SLICE_X10Y3 \<br/>
/// -remove SLICE_X6Y67:SLICE_X11Y71 -locs trim<br/>
/// resize_pblock block3 -add {SLICE_X6Y67:SLICE_X11Y71 \<br/>
/// RAMB18_X0Y2:RAMB18_X1Y4}<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1527<br/>
/// </para>
/// </summary>
/// <param name="pblock">(Required) Pblock to resize</param>
/// <param name="add">(Optional) Add site ranges(s)</param>
/// <param name="remove">(Optional) Remove site ranges(s)</param>
/// <param name="from">(Optional) Site range(s) to move</param>
/// <param name="to">(Optional) Site range destination(s)</param>
/// <param name="replace">(Optional) Remove all existing ranges</param>
/// <param name="locs">(Optional) LOC treatment Default: keep_all</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL resize_pblock(TCLObject pblock, TCLParameterList add = null, TCLParameterList remove = null, TCLParameterList from = null, TCLParameterList to = null, bool?replace = null, String locs = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: resize_pblock [-add <args>] [-remove <args>] [-from <args>] [-to <args>] [-replace] [-locs <arg>] [-quiet] [-verbose] <pblock>
_tcl.Entry(_builder.resize_pblock(pblock, add, remove, from, to, replace, locs, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Tie off unused cell pins<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: tie_unused_pins [-of_objects <args>] [-quiet] [-verbose]
/// <br/>
/// <para>
/// Tie up or down the unconnected pins of cells in the open synthesized or implemented design.<br/>
/// The command uses an internal process to identify whether a pin should be tied up or down.<br/>
/// This command is intended to tie up or down the unconnected pins of cells added to the netlist<br/>
/// with the create_cell command.<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1744<br/>
/// </para>
/// </summary>
/// <param name="of_objects">(Optional) tie unused pins of specified cell(s)</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL tie_unused_pins(TCLParameterList of_objects = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: tie_unused_pins [-of_objects <args>] [-quiet] [-verbose]
_tcl.Entry(_builder.tie_unused_pins(of_objects, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Connect a net to pins or ports<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: connect_net [-hierarchical] [-basename <arg>] [-net <args>] [-objects <args>] [-net_object_list <args>] [-dict <args>] [-quiet] [-verbose]
/// <br/>
/// <para>
/// This command allows the user to connect a specified net to one or more pins or ports in the<br/>
/// netlist of an open Synthesized or Implemented Design.<br/>
/// The connect_net command will also connect nets across levels of hierarchy in the design, by<br/>
/// adding pins and hierarchical nets as needed to complete the connection. Added nets and pins can<br/>
/// be assigned a custom basename to make them easy to identify, or will be assigned a basename<br/>
/// by the Vivado tool.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// TIP: You can specify multiple nets, and a list of pins and ports to connect those nets to, using a single<br/>
/// connect_net command with the -net_object_list or -dict options, to significantly speed the<br/>
/// addition of multiple nets to the current design.<br/>
/// Netlist editing changes the in-memory view of the netlist in the current design. It does not<br/>
/// change the files in the source fileset, or change the persistent design on the disk. Changes made<br/>
/// to the netlist may be saved to a design checkpoint using the write_checkpoint command, or<br/>
/// may be exported to a netlist file such as Verilog, VHDL, or EDIF, using the appropriate write_*<br/>
/// command.<br/>
/// Note: Netlist editing is not allowed on the elaborated RTL design.<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 206<br/>
/// </para>
/// </summary>
/// <param name="objects">(Required) List of pin and port objects to connect</param>
/// <param name="hierarchical">
/// <para>
/// (Optional)<br/>
/// Allow hierarchical connection, creating nets and pins as<br/>
/// needed (see -basename).<br/>
/// </para>
/// </param>
/// <param name="basename">
/// <para>
/// (Optional)<br/>
/// base name to use for net / pin names needed when doing<br/>
/// hierarchical connection (see -hier). Default value is inferred<br/>
/// from the name of the net being connected (see -net).<br/>
/// </para>
/// </param>
/// <param name="net">(Optional) Net to connect to given objects.</param>
/// <param name="net_object_list">
/// <para>
/// (Optional)<br/>
/// optional, a list of net and pin/port list pairs, each pin or port<br/>
/// list element is connected to the corresponding net, e.g.<br/>
/// { net_a { pin_b port_c } net_d pin_e }. Cannot be used with -<br/>
/// net, -objects list is ignored when -net_object_list is used.<br/>
/// </para>
/// </param>
/// <param name="dict">
/// <para>
/// (Optional)<br/>
/// alternative to -net_object_list, faster, but requires a list of<br/>
/// net and pin/port object pairs (must be a list of objects, not<br/>
/// names or other TCL objects), each pin or port list element is<br/>
/// connected to the corresponding net, e.g. { $net_1 $pin_1<br/>
/// $net_2 $pin_2 }. Cannot be used with -net, -objects list is<br/>
/// ignored when -dict is used.<br/>
/// </para>
/// </param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL connect_net(TCLParameterList objects, bool?hierarchical = null, String basename = null, TCLParameterList net = null, TCLParameterList net_object_list = null, TCLParameterList dict = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: connect_net [-hierarchical] [-basename <arg>] [-net <args>] [-objects <args>] [-net_object_list <args>] [-dict <args>] [-quiet] [-verbose]
_tcl.Entry(_builder.connect_net(objects, hierarchical, basename, net, net_object_list, dict, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Unmark items that are currently marked<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: unmark_objects [-rgb <args>] [-color <arg>] [-quiet] [-verbose] [<objects>]
/// <br/>
/// <para>
/// Unmarks the specified object or objects that were previously marked by the mark_objects<br/>
/// command. This command is for use in GUI mode.<br/>
/// This command supports the color options as specified below. However, these options are not<br/>
/// necessary to unmark a specific object, but can be used to unmark all objects currently marked in<br/>
/// the specified color. See the example below.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example unmarks the selected objects:<br/>
/// unmark_objects [get_selected_objects]<br/>
/// The following example unmarks all objects currently marked in the color yellow:<br/>
/// unmark_objects -color yellow<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1752<br/>
/// </para>
/// </summary>
/// <param name="rgb">(Optional) RGB color index list</param>
/// <param name="color">(Optional) Valid values are red green blue magenta yellow cyan and orange</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
/// <param name="objects">(Optional) Objects to unmark</param>
public TTCL unmark_objects(TCLParameterList rgb = null, String color = null, bool?quiet = null, bool?verbose = null, TCLObject objects = null)
{
// TCL Syntax: unmark_objects [-rgb <args>] [-color <arg>] [-quiet] [-verbose] [<objects>]
_tcl.Entry(_builder.unmark_objects(rgb, color, quiet, verbose, objects));
return(_tcl);
}
/// <summary>
/// <para>
/// Get one or more DRC/METHODOLOGY/CDC message waivers<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: get_waivers [-type <arg>] [-id <arg>] [-of_objects <args>] [-regexp] [-filter <arg>] [-nocase] [-quiet] [-verbose] [<patterns>]
/// <br/>
/// <para>
/// The create_waiver command lets you select individual DRC, methodology, or CDC violations<br/>
/// or rule checks that can be waived for a design, letting you move forward in the design flow. The<br/>
/// get_waivers command lets you query the defined waiver objects in the current design.<br/>
/// A waiver must be specified for an individual DRC or methodology violation, or for a specific DRC<br/>
/// or methodology check, or for a CDC path. The waiver must be assigned to a specific object, or<br/>
/// specific violation ID, or for paths using -from/-to arguments. You can format the<br/>
/// get_waivers command to return the specific types of waivers you are looking for, or waivers<br/>
/// associated with specific objects.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// You can report the waivers defined in the current design with report_waivers, and remove<br/>
/// waivers from the design using delete_waivers.<br/>
/// </para>
/// <br/>
/// <para>
/// This example gets any waivers in the current design:<br/>
/// get_waivers<br/>
/// The following example gets all DRC check waivers:<br/>
/// get_waivers -type DRC *<br/>
/// The following example gets all waivers associated with the specified objects:<br/>
/// get_waivers -of_objects [get_ports {src_in* dest_out*}]<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 957<br/>
/// </para>
/// </summary>
/// <param name="type">(Optional) Type of waiver - DRC, METHODOLOGY, CDC, ALL</param>
/// <param name="id">(Optional) ID of the DRC/METHODOLOGY/CDC message being waived</param>
/// <param name="of_objects">
/// <para>
/// (Optional)<br/>
/// List of objects (cells, nets, pins, sites, etc.) for which DRC/<br/>
/// METHODLOGY/CDC waiver(s) were set<br/>
/// </para>
/// </param>
/// <param name="regexp">(Optional) Patterns are full regular expressions</param>
/// <param name="filter">(Optional) Filter list with expression</param>
/// <param name="nocase">(Optional) Perform case-insensitive matching (valid only when -regexp specified)</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
/// <param name="patterns">
/// <para>
/// (Optional)<br/>
/// Match waiver names against patterns Default: * Values: The<br/>
/// default search pattern is the wildcard *, or .* when -regexp<br/>
/// is specified.<br/>
/// </para>
/// </param>
/// <returns>waivers</returns>
public TTCL get_waivers(String type = null, String id = null, TCLParameterList of_objects = null, bool?regexp = null, String filter = null, bool?nocase = null, bool?quiet = null, bool?verbose = null, TCLObject patterns = null)
{
// TCL Syntax: get_waivers [-type <arg>] [-id <arg>] [-of_objects <args>] [-regexp] [-filter <arg>] [-nocase] [-quiet] [-verbose] [<patterns>]
_tcl.Entry(_builder.get_waivers(type, id, of_objects, regexp, filter, nocase, quiet, verbose, patterns));
return(_tcl);
}
/// <summary>
/// <para>
/// Connect debug slave instances to the master instance. A valid master is a debug bridge or debug<br/>
/// hub instance configured in "From BSCAN To DebugHUB" mode. A valid slave could be any of the<br/>
/// following debug cores (Ex: ILA, VIO, JTAG_to_AXI). connect_debug_cores can only connect<br/>
/// master and slave instances that exist in the same region (either in Reconfigurable Partition or<br/>
/// static)<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: connect_debug_cores -master <args> -slaves <args> [-quiet] [-verbose]
/// <br/>
/// <para>
/// Connect debug slave instances to the specified master instance. The command can add the<br/>
/// specified slaves into an existing debug chain, where the specified slaves will be connected to the<br/>
/// debug hub or bridge, without affecting debug slaves that are already in the connection chain.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// Debug masters include both the Debug Hub and Debug Bridge. The Vivado Debug Hub core<br/>
/// provides an interface between the JTAG Boundary Scan (BSCAN) interface of the Xilinx device<br/>
/// and the Vivado Debug cores, including the Integrated Logic Analyzer (ILA), Virtual Input/Output<br/>
/// (VIO), and the JTAG-to-AXI. The Vivado Debug Bridge is a debug controller that provides<br/>
/// multiple options to communicate with the debug cores in both flat designs, or Partial<br/>
/// Reconfiguration (PR) designs. The Debug Bridge can be configured to debug designs using a<br/>
/// JTAG cable, or remotely through Ethernet, PCIe, or other interfaces using a Xilinx Virtual Cable<br/>
/// (XVC), without the need for a JTAG cable. Refer to the Vivado Design Suite User Guide: Vivado<br/>
/// Programming and Debugging (UG908) for more information.<br/>
/// IMPORTANT! For Partial Reconfiguration (PR) designs, the connect_debug_cores command can<br/>
/// only connect master and slave instances that occur in the Static Region, or in the same Reconfigurable<br/>
/// Partition.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example connects the specified ILA cores to the debug bridge:<br/>
/// connect_debug_cores -master [get_cells inst_count/debug_bridge_0] \<br/>
/// -slaves [list [get_cells inst_count/ila_0] [get_cells inst_count/ila_1] ]<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 198<br/>
/// </para>
/// </summary>
/// <param name="master">
/// <para>
/// (Required)<br/>
/// A valid debug bridge or debug hub instance configured in<br/>
/// "From BSCAN To DebugHUB" mode. Only one master<br/>
/// instance is allowed.<br/>
/// </para>
/// </param>
/// <param name="slaves">
/// <para>
/// (Required)<br/>
/// List of valid slave instances. A valid slave instance is any of<br/>
/// the following debug cores (Ex: ILA, VIO, JTAG_to_AXI)<br/>
/// </para>
/// </param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
/// <returns>debug master and slave instances</returns>
public TTCL connect_debug_cores(TCLParameterList master, TCLParameterList slaves, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: connect_debug_cores -master <args> -slaves <args> [-quiet] [-verbose]
_tcl.Entry(_builder.connect_debug_cores(master, slaves, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Report power optimizations<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: report_power_opt [-cell <args>] [-file <arg>] [-format <arg>] [-name <arg>] [-append] [-return_string] [-quiet] [-verbose]
/// <br/>
/// <para>
/// Report power optimizations that have been performed on the design with the<br/>
/// power_opt_design command.<br/>
/// Note: By default the report is written to the Tcl console or STD output. However, the results can also be<br/>
/// written to a file or returned as a string if desired.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example reports the power optimizations performed on the current design, writing<br/>
/// them to the specified file in an XML format:<br/>
/// report_power_opt -format xml -file C:/Data/power_opt.xml<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1410<br/>
/// </para>
/// </summary>
/// <param name="cell">(Optional) list of instance names Default: empty</param>
/// <param name="file">(Optional) output file</param>
/// <param name="format">
/// <para>
/// (Optional)<br/>
/// Specifies how to format the report. Default is 'text', another<br/>
/// option is 'xml'. Only applies if -file is used. If xml output is<br/>
/// used, -append is not allowed. Default: text<br/>
/// </para>
/// </param>
/// <param name="name">(Optional) Output the results to GUI panel with this name</param>
/// <param name="append">(Optional) append if existing file. Otherwise overwrite existing file.</param>
/// <param name="return_string">(Optional) return report as string</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL report_power_opt(TCLParameterList cell = null, String file = null, String format = null, String name = null, bool?append = null, bool?return_string = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: report_power_opt [-cell <args>] [-file <arg>] [-format <arg>] [-name <arg>] [-append] [-return_string] [-quiet] [-verbose]
_tcl.Entry(_builder.report_power_opt(cell, file, format, name, append, return_string, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Get a list of debug ports in the current design<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: get_debug_ports [-filter <arg>] [-of_objects <args>] [-regexp] [-nocase] [-quiet] [-verbose] [<patterns>]
/// <br/>
/// <para>
/// Gets a list of ports defined on ILA debug cores in the current project that match a specified<br/>
/// search pattern. The default command gets a list of all debug ports in the project.<br/>
/// Debug ports are defined when ILA debug cores are created with the create_debug_core<br/>
/// command. Ports can be added to existing debug cores with the create_debug_port<br/>
/// command.<br/>
/// Note: To improve memory and performance, the get_* commands return a container list of a single type<br/>
/// of objects (e.g. cells, nets, pins, or ports). You can add new objects to the list (using lappend for instance),<br/>
/// but you can only add the same type of object that is currently in the list. Adding a different type of object,<br/>
/// or string, to the list is not permitted and will result in a Tcl error.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// </para>
/// <br/>
/// <para>
/// The following command gets a list of the ports from the ILA debug cores in the current project,<br/>
/// with a PORT_WIDTH property of 8:<br/>
/// get_debug_ports -filter {PORT_WIDTH==8}<br/>
/// The following example gets the properties attached to the specified debug port:<br/>
/// report_property [get_debug_ports myCore/PROBE1]<br/>
/// Note: The debug port is defined by the core_name/port_name combination.<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 672<br/>
/// </para>
/// </summary>
/// <param name="filter">(Optional) Filter list with expression</param>
/// <param name="of_objects">(Optional) Get ports of these debug cores</param>
/// <param name="regexp">(Optional) Patterns are full regular expressions</param>
/// <param name="nocase">(Optional) Perform case-insensitive matching (valid only when -regexp specified)</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
/// <param name="patterns">(Optional) Match debug ports against patterns Default: *</param>
/// <returns>list of debug_port objects</returns>
public TTCL get_debug_ports(String filter = null, TCLParameterList of_objects = null, bool?regexp = null, bool?nocase = null, bool?quiet = null, bool?verbose = null, TCLObject patterns = null)
{
// TCL Syntax: get_debug_ports [-filter <arg>] [-of_objects <args>] [-regexp] [-nocase] [-quiet] [-verbose] [<patterns>]
_tcl.Entry(_builder.get_debug_ports(filter, of_objects, regexp, nocase, quiet, verbose, patterns));
return(_tcl);
}
/// <summary>
/// <para>
/// Reset switching activity on specified objects<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: reset_switching_activity [-default] [-type <args>] [-hier] [-all] [-no_deassert_resets] [-quiet] [-verbose] [<objects>...]
/// <br/>
/// <para>
/// Resets the attributes of the switching activity on specified nets, ports, pins, and cells in the<br/>
/// design.<br/>
/// The switching activity is defined using the set_switching_activity command. The current<br/>
/// switching activity defined for a specific port, pin, net, or cell can be found by using the<br/>
/// report_switching_activity command.<br/>
/// Note: The reset_switching_activity is used to reset switching activity for specified objects. Use<br/>
/// set_switching_activity -default_toggle_rate or -default_static_probability to<br/>
/// change or reset the default values for the current design.<br/>
/// This command operates silently and does not return direct feedback of its operation.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// </para>
/// <br/>
/// <para>
/// The following example resets the signal_rate and static probability value on all output ports:<br/>
/// reset_switching_activity -default [all_outputs]<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1518<br/>
/// </para>
/// </summary>
/// <param name="default">(Optional) Reset default static probability and default toggle rate</param>
/// <param name="type">
/// <para>
/// (Optional)<br/>
/// Specify nodes in a specific category. List of valid type values:<br/>
/// io_output, io_bidir_enable, register, lut_ram, lut, dsp,<br/>
/// bram_enable, bram_wr_enable, gt_txdata, gt_rxdata.<br/>
/// </para>
/// </param>
/// <param name="hier">
/// <para>
/// (Optional)<br/>
/// Hierarchically resets the switching activity on a hierarchical<br/>
/// cells provided as <objects>.<br/>
/// </para>
/// </param>
/// <param name="all">(Optional) Reset switching activity on all nets</param>
/// <param name="no_deassert_resets">
/// <para>
/// (Optional)<br/>
/// A switch to undo the deassertion of resets via command<br/>
/// set_switching_activity -deassert_resets<br/>
/// </para>
/// </param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
/// <param name="objects">(Optional) Objects to reset switching activity on</param>
public TTCL reset_switching_activity(bool? @default = null, TCLParameterList type = null, bool?hier = null, bool?all = null, bool?no_deassert_resets = null, bool?quiet = null, bool?verbose = null, TCLObjectList objects = null)
{
// TCL Syntax: reset_switching_activity [-default] [-type <args>] [-hier] [-all] [-no_deassert_resets] [-quiet] [-verbose] [<objects>...]
_tcl.Entry(_builder.reset_switching_activity(@default, type, hier, all, no_deassert_resets, quiet, verbose, objects));
return(_tcl);
}
/// <summary>
/// <para>
/// Modify routed probe connections to debug cores.<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: modify_debug_ports [-probes <args>] [-quiet] [-verbose]
/// <br/>
/// <para>
/// Modifies a routed design to connect nets to specified ports of debug cores. This command takes<br/>
/// a list of connections to be made to specified debug probes. Each connection is defined as a Tcl<br/>
/// list, enclosed in braces {}, specifying the following three elements separated by spaces:<br/>
/// 1. The logical pin of the debug core to be connected.<br/>
/// 2. The channel index of the specified probe.<br/>
/// 3. The logical net of the signal to be probed.<br/>
/// Multiple probe connections are specified as a list of lists, with each connection itself being a Tcl<br/>
/// list as shown in the example.<br/>
/// The command performs all of the netlist modifications to disconnect existing net connections to<br/>
/// the specified probe ports as needed, connecting each net to be probed to the specified probe<br/>
/// port, and automatically routing the modified connections. Nets that become disconnected during<br/>
/// the process are left unconnected.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// </para>
/// <br/>
/// <para>
/// The following example modifies 3 probe connections:<br/>
/// modify_debug_ports -probes [list {top/x_ila/probe0 0 top/inst_A/net_0} \<br/>
/// {top/x_ila/probe1 1 top/inst_A/net_a} {top/x_ila/probe1 2 top/inst_A/<br/>
/// net_b}]<br/>
/// TIP: The modify_debug_ports command moves a port probe from one signal to another.<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1064<br/>
/// </para>
/// </summary>
/// <param name="probes">
/// <para>
/// (Required)<br/>
/// List of probes to be connected: debug core pin, channel<br/>
/// index, and logical net for each probe connection.<br/>
/// </para>
/// </param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL modify_debug_ports(TCLParameterList probes, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: modify_debug_ports [-probes <args>] [-quiet] [-verbose]
_tcl.Entry(_builder.modify_debug_ports(probes, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Set constraints for power optimization<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: set_power_opt [-include_cells <args>] [-exclude_cells <args>] [-clocks <args>] [-cell_types <args>] [-quiet] [-verbose]
/// <br/>
/// <para>
/// Specify cell instances to include or exclude in power optimization. The specified cells are<br/>
/// optimized using the power_opt_design command.<br/>
/// TIP: Block RAM optimizations are performed by default with the opt_design command. Some or all<br/>
/// BRAM cells can be excluded from the opt_design optimization using the set_power_opt command<br/>
/// as well.<br/>
/// The effect of multiple set_power_opt commands is cumulative, so that you can specify a<br/>
/// broad class of cell types to optimize, include specific hierarchical cells, and then exclude cells<br/>
/// within the included hierarchy to refine the power optimization.<br/>
/// The power optimizations that have been performed can be reported using the<br/>
/// report_power_opt command.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// </para>
/// <br/>
/// <para>
/// The following example sets power optimization for BRAM cells only, and then runs power<br/>
/// optimization:<br/>
/// set_power_opt -cell_types bram<br/>
/// power_opt_design<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// The following example sets power optimization for BRAM and REG type cells, then adds SRLs,<br/>
/// and runs power optimization. Then all cells are cleared, and only SRLs are included, and power<br/>
/// optimization is run again:<br/>
/// set_power_opt -cell_types { bram reg}<br/>
/// set_power_opt -cell_types { srl}<br/>
/// power_opt_design<br/>
/// set_power_opt -cell_types { none}<br/>
/// set_power_opt -cell_types { srl}<br/>
/// power_opt_design<br/>
/// The following example sets power optimization for BRAM cells only, excludes the cpuEngine<br/>
/// block from optimization, but then includes the cpuEngine/cpu_dbg_dat_i block, then performs<br/>
/// power optimization:<br/>
/// set_power_opt -cell_types bram<br/>
/// set_power_opt -exclude_cells cpuEngine<br/>
/// set_power_opt -include_cells cpuEngine/cpu_dbg_dat_i<br/>
/// power_opt_design<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1677<br/>
/// </para>
/// </summary>
/// <param name="include_cells">(Optional) Include only these instances for clock gating. Default: all</param>
/// <param name="exclude_cells">(Optional) Exclude these instances from clock gating. Default: none</param>
/// <param name="clocks">(Optional) Clock gate instances clocked by these clocks only. Default: all clocks</param>
/// <param name="cell_types">
/// <para>
/// (Optional)<br/>
/// Clock gate these cell types only. Specify either [all|none], or<br/>
/// one or more of [bram|reg|srl]. Default: all<br/>
/// </para>
/// </param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL set_power_opt(TCLParameterList include_cells = null, TCLParameterList exclude_cells = null, TCLParameterList clocks = null, TCLParameterList cell_types = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: set_power_opt [-include_cells <args>] [-exclude_cells <args>] [-clocks <args>] [-cell_types <args>] [-quiet] [-verbose]
_tcl.Entry(_builder.set_power_opt(include_cells, exclude_cells, clocks, cell_types, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Methodology Checks<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: report_methodology [-name <arg>] [-cells <args>] [-checks <args>] [-file <arg>] [-rpx <arg>] [-append] [-waived] [-no_waivers] [-slack_lesser_than <arg>] [-return_string] [-quiet] [-verbose]
/// <br/>
/// <para>
/// Check the current design against a specified set of methodology checks and report any errors or<br/>
/// violations that are found.<br/>
/// Methodology checks are a special class of design rule checks (DRC) that are accessible through<br/>
/// this separate Tcl command. The methodology checks are a necessary part of the design flow, and<br/>
/// should be considered mandatory after implementation and prior to generating the bitstream.<br/>
/// TIP: Other than their availability through the separate report_methodology command, the checks<br/>
/// are standard design rule checks in every other way.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// The report_methodology command requires an open design to check the design rules<br/>
/// against. The command returns a report with the results of violations found by the design rule<br/>
/// checks. Violations are returned as Vivado objects that can be listed with the<br/>
/// get_methodology_violations command, and are associated with cells, pins, ports, nets,<br/>
/// and sites in the current design. You can get the cells, nets, and other design objects that are<br/>
/// associated with methodology violation objects, using the -of_objects option of the<br/>
/// get_cells command for instance.<br/>
/// The report_methodology command runs the methodology rule deck, or you can use the -<br/>
/// checks option to specify the set of checks to run. Methodology checks can also be enabled or<br/>
/// disabled in the default rule decks using the IS_ENABLED property on the rule check object:<br/>
/// set_property IS_ENABLED FALSE [get_methodology_checks PDRC-190]<br/>
/// If a rule IS_ENABLED false, the rule will not be run by the report_methodology command.<br/>
/// TIP: You can reset the properties of a methodology rule to the factory default settings using the<br/>
/// reset_methodology_check command.<br/>
/// You can reset the current results of the report_methodology command, clearing any found<br/>
/// violations, using the reset_methodology command.<br/>
/// </para>
/// <br/>
/// <para>
/// The following examples run the default methodology checks against the current design, and<br/>
/// writes the results to the specified file:<br/>
/// report_methodology -file C:/Data/methodology_Rpt1.txt -append<br/>
/// Note: The -append option adds the result to the specified file.<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1389<br/>
/// </para>
/// </summary>
/// <param name="name">(Optional) Output the results to GUI panel with this name</param>
/// <param name="cells">(Optional) Run report_methodology on the specified cell(s).</param>
/// <param name="checks">
/// <para>
/// (Optional)<br/>
/// Report Methodology checks (see get_methodology_checks<br/>
/// for available checks)<br/>
/// </para>
/// </param>
/// <param name="file">
/// <para>
/// (Optional)<br/>
/// Filename to output results to. (send output to console if -file<br/>
/// is not used)<br/>
/// </para>
/// </param>
/// <param name="rpx">(Optional) Report filename for persisted results.</param>
/// <param name="append">(Optional) Append the results to file, do not overwrite the results file</param>
/// <param name="waived">(Optional) Output result is Waived checks</param>
/// <param name="no_waivers">(Optional) Disable waivers for checks</param>
/// <param name="slack_lesser_than">(Optional) Set SYNTH rules Slack Threshold value in 'ns' (float) Default: 2.0</param>
/// <param name="return_string">(Optional) return report as string</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL report_methodology(String name = null, TCLParameterList cells = null, TCLParameterList checks = null, String file = null, String rpx = null, bool?append = null, bool?waived = null, bool?no_waivers = null, String slack_lesser_than = null, bool?return_string = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: report_methodology [-name <arg>] [-cells <args>] [-checks <args>] [-file <arg>] [-rpx <arg>] [-append] [-waived] [-no_waivers] [-slack_lesser_than <arg>] [-return_string] [-quiet] [-verbose]
_tcl.Entry(_builder.report_methodology(name, cells, checks, file, rpx, append, waived, no_waivers, slack_lesser_than, return_string, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Recommend QoR Suggestions<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: report_qor_suggestions [-file <arg>] [-name <arg>] [-append] [-return_string] [-max_strategies <arg>] [-max_paths <arg>] [-no_split] [-report_all_suggestions] [-cells <args>] [-of_objects <args>] [-quiet] [-verbose]
/// <br/>
/// <para>
/// Report design and tool option recommendations related to improving the quality of results (QoR).<br/>
/// The report looks at timing constraints, netlist characteristics, failing timing paths, and congestion<br/>
/// information to determine suggestions that can enhance the QoR. The report can be generated<br/>
/// after synthesis, or after any implementation step, but requires a design to be open.<br/>
/// The report_qor_suggestions command creates QoR suggestion objects related to the<br/>
/// suggestions identified. These suggestion objects can be enabled for use by the Vivado tools to<br/>
/// improve the quality of synthesis and implementation results. Some of these suggestions can be<br/>
/// automatically applied, and some may require more manual intervention to implement design<br/>
/// changes, or write Tcl design constraints.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// Suggestion objects can be obtained using the get_qor_suggestions command. The QoR<br/>
/// objects have properties that define what step they are APPLICABLE_FOR, if they are ENABLED<br/>
/// to be used, if they can be automatically applied (AUTO), or what step the suggestions was<br/>
/// GENERATED_AT. A suggestion must be ENABLED and the APPLICABLE_FOR synthesis or<br/>
/// implementation step run in order for a suggestion to be applied to the design.<br/>
/// You can write the suggestions from the design into an RQS file using the<br/>
/// write_qor_suggestions command. After resetting the design flow to the appropriate step,<br/>
/// you can read suggestions back into the design using the read_qor_suggestions command,<br/>
/// and then run the synthesis or implementation step to apply the enabled suggestions.<br/>
/// The recommended method for working with QoR suggestions is:<br/>
/// 1. Run the report to create recommendations (report_qor_suggestions)<br/>
/// 2. Write the suggestions to an RQS file on disk (write_qor_suggestions).<br/>
/// 3. Reset the design to the appropriate step.<br/>
/// 4. Read the RQS file into the design to restore the suggestions (read_qor_suggestions).<br/>
/// 5. Run the synthesis or implementation step to apply the suggestion (synth_design,<br/>
/// opt_design...).<br/>
/// For strategy suggestions, a machine learning based analysis is conducted and the best 3<br/>
/// strategies are reported. This analysis is only conducted on a routed design that has been<br/>
/// implemented with<br/>
/// • either default or explore directives for opt_design and<br/>
/// • either all default or all explore directives for place_design, phys_opt_design, and<br/>
/// route_design commands.<br/>
/// Strategy suggestions do not apply to synthesis. Unlike the non-strategy suggestions, only one<br/>
/// strategy suggestion can be applied to each run.<br/>
/// The recommended method for working with QoR strategy suggestions is:<br/>
/// 1. Run the report to create strategies and other<br/>
/// recommendations(report_qor_suggestions).<br/>
/// 2. Write the suggestions to a directory disk. There is one RQS file per strategy<br/>
/// (write_qor_suggestions -strategy_dir).<br/>
/// 3. Update all the directive settings to -directive RQS for opt_design, place_design,<br/>
/// phys_opt_design, and route_design commands.<br/>
/// 4. For each run, read one RQS file into the design. This will contain the strategy suggestion and<br/>
/// all exported non-strategy suggestions(read_qor_suggestions).<br/>
/// 5. Run the implementation step from the opt_design command to apply the strategy and all<br/>
/// the design suggestions.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// </para>
/// <br/>
/// <para>
/// The following example reports suggestions after analyzing the worst 10 paths:<br/>
/// report_qor_suggestions -max_paths 10<br/>
/// This example reports existing suggestions in the design from a prior run of<br/>
/// report_qor_suggestions:<br/>
/// report_qor_suggestions -of_objects [get_qor_suggestions]<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1426<br/>
/// </para>
/// </summary>
/// <param name="file">
/// <para>
/// (Optional)<br/>
/// Filename to output results to. (send output to console if -file<br/>
/// is not used)<br/>
/// </para>
/// </param>
/// <param name="name">(Optional) Output the results to GUI panel with this name</param>
/// <param name="append">(Optional) Append the results to file, don't overwrite the results file</param>
/// <param name="return_string">(Optional) Return report as string</param>
/// <param name="max_strategies">(Optional) Number of strategies to suggest Default: 3</param>
/// <param name="max_paths">(Optional) Number of paths to consider for suggestion analysis Default: 100</param>
/// <param name="no_split">(Optional) Report without spliting the lines in tables</param>
/// <param name="report_all_suggestions">(Optional) Report all suggestions</param>
/// <param name="cells">(Optional) Report QOR suggestions for a given cell</param>
/// <param name="of_objects">(Optional) List of QoR suggestion objects</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL report_qor_suggestions(String file = null, String name = null, bool?append = null, bool?return_string = null, Int32?max_strategies = null, Int32?max_paths = null, bool?no_split = null, bool?report_all_suggestions = null, TCLParameterList cells = null, TCLParameterList of_objects = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: report_qor_suggestions [-file <arg>] [-name <arg>] [-append] [-return_string] [-max_strategies <arg>] [-max_paths <arg>] [-no_split] [-report_all_suggestions] [-cells <args>] [-of_objects <args>] [-quiet] [-verbose]
_tcl.Entry(_builder.report_qor_suggestions(file, name, append, return_string, max_strategies, max_paths, no_split, report_all_suggestions, cells, of_objects, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Disconnect a net from pins or ports<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: disconnect_net [-prune] [-net <arg>] [-objects <args>] [-pinlist <args>] [-quiet] [-verbose]
/// <br/>
/// <para>
/// This command allows the user to disconnect a specified net from one or more pins or ports in the<br/>
/// netlist of an open Synthesized or Implemented Design.<br/>
/// Netlist editing changes the in-memory view of the netlist in the current design. It does not<br/>
/// change the files in the source fileset, or change the persistent design on the disk. Changes made<br/>
/// to the netlist may be saved to a design checkpoint using the write_checkpoint command, or<br/>
/// may be exported to a netlist file such as Verilog, VHDL, or EDIF, using the appropriate write_*<br/>
/// command.<br/>
/// Note: Netlist editing is not allowed on the elaborated RTL design.<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 498<br/>
/// </para>
/// </summary>
/// <param name="prune">
/// <para>
/// (Optional)<br/>
/// When performing disconnect, remove the net and any<br/>
/// pin/net chain up to the pin on any primitive instance as long<br/>
/// as each object in the chain has only 1 remaining connection.<br/>
/// </para>
/// </param>
/// <param name="net">
/// <para>
/// (Optional)<br/>
/// Net to disconnect - optional, net attached to first pin or port<br/>
/// object is used if not specified.<br/>
/// </para>
/// </param>
/// <param name="objects">
/// <para>
/// (Optional)<br/>
/// List of pin and port names to disconnect. String expressions<br/>
/// are supported.<br/>
/// </para>
/// </param>
/// <param name="pinlist">(Optional) List of pin and port objects to disconnect.</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL disconnect_net(bool?prune = null, String net = null, TCLParameterList objects = null, TCLParameterList pinlist = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: disconnect_net [-prune] [-net <arg>] [-objects <args>] [-pinlist <args>] [-quiet] [-verbose]
_tcl.Entry(_builder.disconnect_net(prune, net, objects, pinlist, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Automatically place a set of ports<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: place_ports [-skip_unconnected_ports] [-check_only] [-iobank <args>] [-quiet] [-verbose] [<ports>...]
/// <br/>
/// <para>
/// Assign ports to the pins of the Xilinx FPGA package, by automatically or manually placing ports.<br/>
/// • Automatically places ports on an available I/O or clocking site, or into the specified I/O banks.<br/>
/// • Manually assigns ports to the specified package_pin when both the port and pin are specified.<br/>
/// The place_ports command will not replace ports that are currently placed by the user, or<br/>
/// ports that are placed and fixed.<br/>
/// Note: This command operates silently and does not return direct feedback of its operation.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example places the port objects returned by the get_ports command, onto I/O<br/>
/// bank 13 of the device, as returned by get_iobanks:<br/>
/// place_ports -iobank [get_iobanks 13] [get_ports DataOut_pad_1_o]<br/>
/// The follow example uses port_name package_pin pairs to manually place multiple ports:<br/>
/// place_ports {LEDS_n[2] AA11 LEDS_n[3] AA10 LEDS_n[0] Y11 LEDS_n[1] Y10}<br/>
/// The following example places all input ports onto I/O banks 12, 13, 14 and 15 of the device:<br/>
/// place_ports -iobank [get_iobanks {12 13 14 15}] [all_inputs]<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1129<br/>
/// </para>
/// </summary>
/// <param name="skip_unconnected_ports">(Optional) Do not place unconnected ports</param>
/// <param name="check_only">(Optional) Only check IO/Clock placement DRCs</param>
/// <param name="iobank">(Optional) Limit placement to the following banks</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
/// <param name="ports">
/// <para>
/// (Optional)<br/>
/// Ports to place (if omitted, all ports will be placed). If the<br/>
/// arguments are interleaved objects of ports and package<br/>
/// pins, then manual placement is performed<br/>
/// </para>
/// </param>
public TTCL place_ports(bool?skip_unconnected_ports = null, bool?check_only = null, TCLParameterList iobank = null, bool?quiet = null, bool?verbose = null, TCLObjectList ports = null)
{
// TCL Syntax: place_ports [-skip_unconnected_ports] [-check_only] [-iobank <args>] [-quiet] [-verbose] [<ports>...]
_tcl.Entry(_builder.place_ports(skip_unconnected_ports, check_only, iobank, quiet, verbose, ports));
return(_tcl);
}
/// <summary>
/// <para>
/// Get the routed or estimated delays in picoseconds on a net from the driver to each load pin.<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: get_net_delays -of_objects <args> [-regexp] [-nocase] [-patterns <arg>] [-filter <arg>] [-to <args>] [-interconnect_only] [-quiet] [-verbose]
/// <br/>
/// <para>
/// Get delay objects for the specified nets in the current design, from the driver to each load pin, or<br/>
/// to specified load pins, through specific pins.<br/>
/// The delay object contains properties defining the maximum and minimum delays for the fast and<br/>
/// slow process corners. Use the get_property command to extract the property of interest from<br/>
/// the delay object. Delay property values on the delay object are specified in picoseconds.<br/>
/// TIP: In most cases the Vivado tools return delay values specified in nanoseconds, but the delay object uses<br/>
/// picoseconds.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// The values returned are calculated or estimated depending upon whether the net is routed.<br/>
/// Delay values can include the actual delay of routed interconnect, or estimated net delays for<br/>
/// unrouted nets. The net delay can also include delay through logic elements or device sites, or just<br/>
/// include the interconnect delay.<br/>
/// Note: To improve memory and performance, the get_* commands return a container list of a single type<br/>
/// of objects (e.g. cells, nets, pins, or ports). You can add new objects to the list (using lappend for instance),<br/>
/// but you can only add the same type of object that is currently in the list. Adding a different type of object,<br/>
/// or string, to the list is not permitted and will result in a Tcl error.<br/>
/// The get_net_delays command returns the delay objects for the specified nets, or returns an<br/>
/// error if it fails.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example gets the interconnect delay values for the specified net, and returns it in<br/>
/// the form of a delay object:<br/>
/// report_property -all [lindex [get_net_delays -interconnect_only \<br/>
/// -of_objects [get_nets control_reg[*]]] 16 ]<br/>
/// TIP: The FAST_MAX, FAST_MIN, SLOW_MAX, and SLOW_MIN properties on the delay object are<br/>
/// reported in picoseconds.<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 838<br/>
/// </para>
/// </summary>
/// <param name="of_objects">(Required) Get 'net_delay' objects of these types: 'net'.</param>
/// <param name="regexp">(Optional) Patterns are full regular expressions</param>
/// <param name="nocase">(Optional) Perform case-insensitive matching. (valid only when -regexp specified)</param>
/// <param name="patterns">(Optional) Match the 'net_delay' objects against patterns. Default: *</param>
/// <param name="filter">(Optional) Filter list with expression</param>
/// <param name="to">(Optional) Get the delay of the net to the given terminal(s) or port(s).</param>
/// <param name="interconnect_only">
/// <para>
/// (Optional)<br/>
/// Include only interconnect delays. The default is to include<br/>
/// the intra-site delay.<br/>
/// </para>
/// </param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
/// <returns>net_delays</returns>
public TTCL get_net_delays(TCLParameterList of_objects, bool?regexp = null, bool?nocase = null, String patterns = null, String filter = null, TCLParameterList to = null, bool?interconnect_only = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: get_net_delays -of_objects <args> [-regexp] [-nocase] [-patterns <arg>] [-filter <arg>] [-to <args>] [-interconnect_only] [-quiet] [-verbose]
_tcl.Entry(_builder.get_net_delays(of_objects, regexp, nocase, patterns, filter, to, interconnect_only, quiet, verbose));
return(_tcl);
}
