public void Initialize()
{
Stat = new Stat();
// Crossbar
Xbar = new Xbar();
// ddr3
DDR3DRAM ddr3 = new DDR3DRAM(Config.mem.ddr3_type,
Config.mem.clock_factor, Config.mem.tRTRS, Config.mem.tWR,
Config.mem.tWTR, Config.mem.tBL, Config.mem.bank_max,
Config.mem.subarray_max, Config.mem.col_max,
Config.mem.tRA, Config.mem.tWA, Config.mem.tREFI,
Config.mem.tRFC, Config.mem.tRP, Config.mem.tRCD);
uint cmax = Config.mem.chan_max;
uint rmax = Config.mem.rank_max;
// randomized page table
const ulong page_size = 4 * 1024;
PageRandomizer prand = new PageRandomizer(page_size, ddr3.ROW_MAX);
Req.Prand = prand;
// sequential page table
PageSequencer pseq = new PageSequencer(page_size, cmax, rmax, ddr3.BANK_MAX);
Req.Pseq = pseq;
// Contiguous physical page allocation
ContiguousAllocator pcontig = new ContiguousAllocator(page_size, cmax * rmax * ddr3.ROW_MAX * ddr3.DEVICE_WIDTH);
Req.Pcontig = pcontig;
// memory mapping
MemMap.Init(Config.mem.map_type, Config.mem.chan_max, Config.mem.rank_max, Config.mem.col_per_subrow, ddr3);
// Cache hierarchy
if (Config.proc.cache_enabled)
{
Caches = new CacheHierarchy(Config.N);
}
// processors
Procs = new Proc.Proc[Config.N];
for (int p = 0; p < Config.N; p++)
{
Procs[p] = new Proc.Proc(Config.traceFileNames[p], Caches);
}
// memory controllers
Mctrls = new MemCtrl.MemCtrl[cmax];
for (int i = 0; i < Mctrls.Length; i++)
{
Mctrls[i] = new MemCtrl.MemCtrl(rmax, ddr3);
// Add ref handles to processors
for (int p = 0; p < Config.N; p++)
{
Procs[p].mctrls[i] = Mctrls[i];
Mctrls[i].ProcHandles[p] = Procs[p];
}
}
// memory schedulers
MemSched.MemSched[] rscheds = new MemSched.MemSched[cmax];
for (int i = 0; i < cmax; i++)
{
Object[] args = { Mctrls[i], Mctrls };
rscheds[i] = Activator.CreateInstance(Config.sched.typeof_sched_algo, args) as MemSched.MemSched;
}
MemSched.MemSched[] wscheds = new MemSched.MemSched[cmax];
for (int i = 0; i < cmax; i++)
{
Object[] args = { Mctrls[i], Mctrls };
wscheds[i] = Activator.CreateInstance(Config.sched.typeof_wbsched_algo, args) as MemSched.MemSched;
}
for (int i = 0; i < cmax; i++)
{
Mctrls[i].Rsched = rscheds[i];
Mctrls[i].Wsched = wscheds[i];
rscheds[i].Initialize();
wscheds[i].Initialize();
}
// WB mode
Mwbmode = Activator.CreateInstance(Config.mctrl.typeof_wbmode_algo, new Object[] { Mctrls }) as MemWBMode.MemWBMode;
for (int i = 0; i < cmax; i++)
{
Mctrls[i].Mwbmode = Mwbmode;
}
// BLP tracker
Blptracker = new BLPTracker(Mctrls);
}
public void RunAll()
{
bool[] isDone = new bool[Config.N];
for (int i = 0; i < Config.N; i++)
{
isDone[i] = false;
}
bool isWarmup = Config.proc.cache_enabled && (Config.warmup_cycle_max > 0);
bool finished = false;
while (!finished)
{
finished = true;
// Processors
int pid = rand.Next(Config.N);
for (int i = 0; i < Config.N; i++)
{
Proc.Proc currProc = Procs[pid];
if (isDone[pid] == false)
{
currProc.tick();
}
pid = (pid + 1) % Config.N;
}
// Memory controllers
for (int i = 0; i < Config.mem.chan_max; i++)
{
Mctrls[i].Tick();
}
// BLP tracker
Blptracker.Tick();
// XBAR
Xbar.Tick();
// Progress simulation time
cycles++;
// Warming up the cache
if (cycles >= Config.warmup_cycle_max && isWarmup)
{
isWarmup = false;
reset_stats();
}
if (isWarmup)
{
finished = false;
continue;
}
// Case #1: instruction constrained simulation
switch (Config.sim_type)
{
case Config.SIM_TYPE.INST:
for (int p = 0; p < Config.N; p++)
{
if (isDone[p])
{
continue;
}
if (Stat.procs[p].ipc.Count >= Config.sim_inst_max)
{
// Simulation is now finished for this processor
finish_proc(p);
isDone[p] = true;
}
else
{
// Simulation is still unfinished for this processor
finished = false;
}
}
break;
case Config.SIM_TYPE.CYCLE:
if (cycles >= Config.sim_cycle_max)
{
finish_proc();
finished = true;
}
else
{
finished = false;
}
break;
case Config.SIM_TYPE.COMPLETION:
for (int p = 0; p < Config.N; p++)
{
if (isDone[p])
{
continue;
}
if (Procs[p].trace.finished)
{
// Simulation is now finished for this processor
finish_proc(p);
isDone[p] = true;
}
else
{
// Simulation is still unfinished for this processor
finished = false;
}
}
break;
}
}
}
