public TraceFetcher()
{
name = "TraceFetcher";
if (Config.trace_type == Trace_Type.Detailed)
{
// reader = ClassActivition.CreateInstance<FileReader>("PIMSim.TraceReader.DetailedTxtReader");
reader = new DetailedTxtReader();
}
else
{
if (Config.text_type == Text_Type.Txt)
{
reader = new PCTxtReader();
}
else
{
//gzipreader
}
}
port = new TraceFetcherMasterPorts("TraceFetcher Data Port", PortManager.Allocate());
port.owner = this;
}
/// <summary>
/// Processor Construction Function
/// </summary>
/// <param name="insp_"> Shared Instruction Partitioner </param>
/// <param name="pid_"> Processor ID</param>
public Proc(ref InsPartition insp_, int pid_)
{
//passing parameters
pid = pid_;
ins_p = insp_;
IPC = Config.IPC;
//init private cache
L1Cache = new Cache(false);
//init instruction window
ins_w = new InstructionWindow(Config.ins_w_size, pid);
//queue init
if (Config.use_cache)
{
cache_req_queue = new Queue <ProcRequest>();
}
MSHR = new List <ProcRequest>(Config.mshr_size);
if (Config.writeback)
{
writeback_req = new List <ProcRequest>();
}
//restrict
cal_restrict = new Counter(Config.IPC, Config.IPC);
mem_restrict = new Counter(1, 1);
//alu
alu = new ALU();
//init callback
read_callback = new ReadCallBack(handle_read_callback);
write_callback = new WriteCallBack(handle_write_callback);
ins_port = new InspCPUSlavePort("CPU Insrtuction Cache", PortManager.Allocate());
ins_port.owner = this;
}
public InsPartition()
{
n = Config.N;
all_ins = new List <Queue <Input> >();
eof = new List <bool>();
for (int i = 0; i < n; i++)
{
all_ins.Add(new Queue <Input>());
eof.Add(false);
divide_host_reqs.Add(0);
divide_host_sent.Add(0);
}
pim_ins = new List <Queue <Input> >();
for (int i = 0; i < PIMConfigs.pim_cu_count; i++)
{
pim_ins.Add(new Queue <Input>());
divide_pim_reqs.Add(0);
divide_pim_sent.Add(0);
}
ins_port = new TraceFetcherSlavePort("Insp Ins Port", PortManager.Allocate());
ins_port.owner = this;
data_port = new InspCPUMasterPort("Insp Data Port", PortManager.Allocate());
data_port.owner = this;
}
