private void SetControlRegister(byte data) { mirrorMode = (MirrorMode)(data & 0x03); prgBankMode = (PRGBankMode)((data >> 2) & 0x03); chrBankMode = (CHRBankMode)((data >> 4) & 0x01); }
public override bool MapCPUAddressWrite(uint address, byte data, out uint newAddress) { if (address >= 0x6000 && address <= 0x7FFF) { newAddress = MapperHandled; cartridgeRAM[address & 0x1FFF] = data; return(true); } if (address >= 0x8000) { if ((data & 0x80) != 0) { // Reset load register loadRegister = 0x00; loadRegisterCount = 0; prgBankMode = PRGBankMode.FixedHigh; newAddress = 0; return(false); } loadRegister >>= 1; loadRegister |= (byte)((data & 0x01) << 4); loadRegisterCount++; if (loadRegisterCount == 5) { if (address <= 0x9FFF) { SetControlRegister((byte)(loadRegister & 0x1F)); } else if (address <= 0xBFFF) { chrBankSelectedLo = (byte)(loadRegister & 0x1F); } else if (address <= 0xDFFF) { chrBankSelectedHi = (byte)(loadRegister & 0x1F); } else { switch (prgBankMode) { case PRGBankMode.Single1: case PRGBankMode.Single2: prgBankSelectedLo = (byte)((loadRegister & 0x0E) >> 1); break; case PRGBankMode.FixedLow: prgBankSelectedLo = 0; prgBankSelectedHi = (byte)(loadRegister & 0x0F); break; case PRGBankMode.FixedHigh: prgBankSelectedLo = (byte)(loadRegister & 0x0F); prgBankSelectedHi = (byte)(prgBankCount - 1); break; } } loadRegister = 0x00; loadRegisterCount = 0; } } newAddress = 0; return(false); }