public static void Msr(ILEmitterCtx context) { OpCodeSystem64 op = (OpCodeSystem64)context.CurrOp; context.EmitLdarg(TranslatedSub.StateArgIdx); context.EmitLdintzr(op.Rt); string propName; switch (GetPackedId(op)) { case 0b11_011_0100_0100_000: propName = nameof(CpuThreadState.Fpcr); break; case 0b11_011_0100_0100_001: propName = nameof(CpuThreadState.Fpsr); break; case 0b11_011_1101_0000_010: propName = nameof(CpuThreadState.TpidrEl0); break; default: throw new NotImplementedException($"Unknown MSR at {op.Position:x16}"); } PropertyInfo propInfo = typeof(CpuThreadState).GetProperty(propName); if (propInfo.PropertyType != typeof(long) && propInfo.PropertyType != typeof(ulong)) { context.Emit(OpCodes.Conv_U4); } context.EmitCallPropSet(typeof(CpuThreadState), propName); }
public static void Sys(ILEmitterCtx context) { //This instruction is used to do some operations on the CPU like cache invalidation, //address translation and the like. //We treat it as no-op here since we don't have any cache being emulated anyway. OpCodeSystem64 op = (OpCodeSystem64)context.CurrOp; switch (GetPackedId(op)) { case 0b11_011_0111_0100_001: { //DC ZVA for (int offs = 0; offs < (4 << CpuThreadState.DczSizeLog2); offs += 8) { context.EmitLdarg(TranslatedSub.MemoryArgIdx); context.EmitLdintzr(op.Rt); context.EmitLdc_I(offs); context.Emit(OpCodes.Add); context.EmitLdc_I8(0); InstEmitMemoryHelper.EmitWriteCall(context, 3); } break; } //No-op case 0b11_011_0111_1110_001: //DC CIVAC break; } }
private static int GetPackedId(OpCodeSystem64 op) { int id; id = op.Op2 << 0; id |= op.CRm << 3; id |= op.CRn << 7; id |= op.Op1 << 11; id |= op.Op0 << 14; return(id); }