private Tile GetTile(NetlistContainer container, NetPin pin)
{
Instance instance = container.GetInstanceByName(pin.InstanceName);
Tile instanceTile = FPGA.FPGA.Instance.GetTile(instance.Location);
return(instanceTile);
}
public void SetPins()
{
foreach (TCLRoutingTreeNode node in RoutingTree.GetAllRoutingNodes().Where(n => !n.VirtualNode))
{
Tile t = node.Tile;
foreach (Slice s in t.Slices)
{
bool inport = s.PortMapping.IsSliceInPort(node.Port);
bool outport = s.PortMapping.IsSliceOutPort(node.Port);
if ((inport || outport) && node.Port.Name.Contains('_'))
{
NetPin pin = null;
if (inport)
{
pin = new NetInpin();
}
else
{
pin = new NetOutpin();
}
pin.SlicePort = node.Port.Name.Substring(node.Port.Name.LastIndexOf('_'));
pin.InstanceName = s.SliceName;
bool pinExistsAlready = NetPins.FirstOrDefault(np => np.InstanceName.Equals(pin.InstanceName) && np.SlicePort.Equals(pin.SlicePort)) != null;
if (!pinExistsAlready)
{
Add(pin);
}
}
}
}
}
/// <summary>
/// copy and relocate the net
/// </summary>
/// <param name="other"></param>
public static TCLNet Relocate(TCLNet other,LibraryElement libElement,Tile anchor)
{
TCLNet copiedNet = new TCLNet(other.Name);
copiedNet.RoutingTree = new TCLRoutingTree(other.RoutingTree);
foreach (TCLRoutingTreeNode node in copiedNet.RoutingTree.GetAllRoutingNodes().Where(n => n.Tile != null))
{
string targetLocation = "";
bool success = libElement.GetTargetLocation(node.Tile.Location, anchor, out targetLocation);
Tile targetTile = FPGA.FPGA.Instance.GetTile(targetLocation);
node.Tile = targetTile;
}
copiedNet.m_footerComment.Append(other.FooterComment);
copiedNet.Properties = new TCLProperties(other.Properties);
copiedNet.m_netPins = new List <NetPin>();
foreach (NetPin pin in other.NetPins)
{
NetPin copiedPin = NetPin.Copy(pin);
copiedNet.m_netPins.Add(copiedPin);
string targetLocation = "";
bool success = libElement.GetTargetLocation(pin.TileName, anchor, out targetLocation);
Tile targetTile = FPGA.FPGA.Instance.GetTile(targetLocation);
pin.TileName = targetTile.Location;
}
copiedNet.IsBlockerNet = other.IsBlockerNet;
copiedNet.NodeNet = other.NodeNet;
if (other.OutpinInstance != null)
{
copiedNet.OutpinInstance = new TCLInstance((TCLInstance)other.OutpinInstance);
}
return(copiedNet);
}
private NetPin Trim(NetPin np)
{
np.InstanceName = np.InstanceName.Replace("\"", "");
np.SlicePort = np.SlicePort.Replace("\"", "");
np.SlicePort = np.SlicePort.Replace(",", "");
return(np);
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);
NetlistContainer netlistContainer = GetNetlistContainer();
foreach (XDLNet n in netlistContainer.Nets)
{
foreach (XDLPip pip in n.Pips)
{
Tile t = FPGA.FPGA.Instance.GetTile(pip.Location);
if (!IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB))
{
continue;
}
foreach (Slice s in t.Slices)
{
bool inport = s.PortMapping.IsSliceInPort(new Port(pip.To));
bool outport = s.PortMapping.IsSliceOutPort(new Port(pip.To));
if ((inport | outport) && pip.To.Contains('_'))
{
NetPin pin = null;
if (inport)
{
pin = new NetInpin();
}
else
{
pin = new NetOutpin();
}
string[] atoms = pip.To.Split('_');
pin.SlicePort = atoms[1];
if (netlistContainer.Instances.Any(i => i.SliceName.Equals(s.SliceName)))
{
// there should be only one instance on the slice
XDLInstance inst = (XDLInstance)netlistContainer.Instances.First(i => i.SliceName.Equals(s.SliceName));
pin.InstanceName = inst.Name;
}
else
{
pin.InstanceName = s.SliceName;
}
bool pinExistsAlready = n.NetPins.FirstOrDefault(np => np.InstanceName.Equals(pin.InstanceName) && np.SlicePort.Equals(pin.SlicePort)) != null;
if (!pinExistsAlready)
{
n.Add(pin);
}
}
}
}
}
}
public XDLInstance GetInstance(NetPin np)
{
if (HasInstanceByName(np.InstanceName))
{
//XDLInstance result = this.m_instances[np.InstanceName];
//return result;
return((XDLInstance)m_instances[np.InstanceName]);
}
else
{
throw new ArgumentNullException("Can not resolve " + np.InstanceName);
}
}
/// <summary>
/// Copy TODO use Clone
/// </summary>
/// <param name="other"></param>
public static TCLNet Copy(TCLNet other)
{
TCLNet copy = new TCLNet(other.Name);
copy.RoutingTree = new TCLRoutingTree(other.RoutingTree);
copy.m_footerComment.Append(other.FooterComment);
copy.Properties = new TCLProperties(other.Properties);
copy.m_netPins = new List <NetPin>();
foreach (NetPin pin in other.NetPins)
{
copy.m_netPins.Add(NetPin.Copy(pin));
}
copy.IsBlockerNet = other.IsBlockerNet;
copy.NodeNet = other.NodeNet;
if (other.OutpinInstance != null)
{
copy.OutpinInstance = new TCLInstance((TCLInstance)other.OutpinInstance);
}
return(copy);
}
private bool IsInside(NetlistContainer container, NetPin pin)
{
Tile instanceTile = GetTile(container, pin);
return(TileSelectionManager.Instance.IsSelected(instanceTile.TileKey));
}
public static bool AddXDLOutpin(Net blockerNet, Tile t, int sliceNumber)
{
foreach (Port sliceOutPort in GetAllDrivers(t, sliceNumber))
{
foreach (Port target in t.SwitchMatrix.GetDrivenPorts(sliceOutPort).Where(drivenPort => !t.IsPortBlocked(drivenPort) && !BlockerSettings.Instance.SkipPort(drivenPort)))
{
List <Location> locations = new List <Location>();
foreach (Location loc in Navigator.GetDestinations(t, target))
{
locations.Add(loc);
}
if (locations.Count < 1)
{
continue;
}
Tile neighbour = locations[0].Tile;
Port driverOnNeighbourTile = locations[0].Pip;
if (neighbour.IsPortBlocked(driverOnNeighbourTile))
{
continue;
}
Port beginPip = neighbour.SwitchMatrix.GetDrivenPorts(driverOnNeighbourTile).FirstOrDefault(p => !neighbour.IsPortBlocked(p));
if (beginPip == null)
{
continue;
}
// arc on CLB
if (blockerNet is XDLNet)
{
((XDLNet)blockerNet).Add(t, sliceOutPort, target);
}
else
{
// TODO
}
BlockPort(t, sliceOutPort);
BlockPort(t, target);
// ouptin on CLB
NetOutpin outpin = new NetOutpin();
outpin.InstanceName = t.Slices[sliceNumber].SliceName;
outpin.SlicePort = NetPin.GetSlicePortString(sliceOutPort.Name);
blockerNet.Add(outpin);
// arc in INT
if (blockerNet is XDLNet)
{
((XDLNet)blockerNet).Add(neighbour, driverOnNeighbourTile, beginPip);
}
else
{
// TODO
}
BlockPort(neighbour, driverOnNeighbourTile);
BlockPort(neighbour, beginPip);
return(true);
}
}
return(false);
}
private void RelocateNetsForXDL(LibraryElement libElement, Tile anchorCLB, XDLContainer netlistContainer)
{
foreach (XDLNet net in libElement.Containter.Nets)
{
// insert instance prefix
XDLNet relocatedNet = new XDLNet(InstanceName + net.Name);
relocatedNet.HeaderExtension = net.HeaderExtension;
foreach (NetPin pin in net.NetPins)
{
NetPin copy = NetPin.Copy(pin);
if (InsertPrefix)
{
// insert instance prefix
// remove greedy between double quotes
string oldInstanceName = pin.InstanceName;
string newInstanceName = "\"" + InstanceName + Regex.Replace(oldInstanceName, "\"", "") + "\"";
//xdlCode = Regex.Replace(xdlCode, oldInstanceName, newInstanceName);
copy.InstanceName = newInstanceName;
copy.InstanceName = copy.InstanceName.Replace("\"", "");
}
relocatedNet.Add(copy);
}
//foreach (NetSegment seg in originalNet.GetAllSegments())
foreach (XDLPip pip in net.Pips)
{
string targetLocation;
bool success = libElement.GetTargetLocation(pip.Location, anchorCLB, out targetLocation);
Tile targetTile = null;
if (FPGA.FPGA.Instance.Contains(targetLocation))
{
targetTile = FPGA.FPGA.Instance.GetTile(targetLocation);
}
else
{
throw new ArgumentException("Error during relocation of pip " + pip + " to " + targetLocation);
}
XDLPip relocatedSegment = null;
if (targetTile.SwitchMatrix.Contains(pip.From, pip.To))
{
// we do not need to transform identifiers
relocatedSegment = new XDLPip(targetTile.Location, pip.From, pip.Operator, pip.To);
}
else
{
// naming fun
relocatedSegment = FPGATypes.RelocatePip(targetTile, pip, relocatedNet);
}
if (relocatedSegment == null)
{
throw new ArgumentException("Could not relocate " + pip.ToString() + " to tile " + targetLocation);
}
if (!targetTile.SwitchMatrix.Contains(relocatedSegment.From, relocatedSegment.To))
{
throw new ArgumentException("Could not relocate " + pip.ToString() + " to tile " + targetLocation);
}
relocatedNet.Add(relocatedSegment);
}
if (netlistContainer.Nets.Any(n => n.Name.Equals(relocatedNet.Name)))
{
throw new ArgumentException("A net named " + relocatedNet.Name + " is alredy inserted to netlist " + netlistContainer.Name + ". Did you try to join two instances of the same macro in one?");
}
netlistContainer.Add(relocatedNet);
}
}
private bool Remove(NetPin np, XDLContainer netlistContainer)
{
return(TileSelectionManager.Instance.IsSelected(FPGA.FPGA.Instance.GetTile(netlistContainer.GetInstance(np).Location).TileKey));
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);
// what to route
NetlistContainer netlist = GetNetlistContainer();
XDLNet netToRoute = (XDLNet)netlist.GetNet(NetName);
int outpinCount = netToRoute.NetPins.Count(np => np is NetOutpin);
if (outpinCount != 1)
{
throw new ArgumentException("Can not route nets with " + outpinCount + " outpins");
}
NetPin outpin = netToRoute.NetPins.First(np => np is NetOutpin);
// start to route from here
List <Location> startLocations = new List <Location>();
List <Location> targetLocations = new List <Location>();
// route from outpin
string startTileName = netlist.GetInstanceByName(outpin.InstanceName).Location;
Tile startTile = FPGA.FPGA.Instance.GetTile(startTileName);
Slice startSlice = startTile.GetSliceByName(netlist.GetInstanceByName(outpin.InstanceName).SliceName);
Port startPip = startSlice.PortMapping.Ports.Where(p => p.Name.EndsWith(outpin.SlicePort)).First();
Location outpinLocation = new Location(startTile, startPip);
startLocations.Add(outpinLocation);
Queue <Location> targetQueue = new Queue <Location>(targetLocations);
foreach (NetPin inpin in netToRoute.NetPins.Where(np => np is NetInpin).OrderBy(np => np.InstanceName))
{
string targetTileName = netlist.GetInstanceByName(inpin.InstanceName).Location;
Tile targetTile = FPGA.FPGA.Instance.GetTile(targetTileName);
Slice targetSlice = targetTile.GetSliceByName(netlist.GetInstanceByName(inpin.InstanceName).SliceName);
Port targetPip = targetSlice.PortMapping.Ports.Where(p => p.Name.EndsWith(inpin.SlicePort)).First();
Location inpinLocation = new Location(targetTile, targetPip);
targetQueue.Enqueue(inpinLocation);
}
while (targetQueue.Count > 0)
{
// start with new routing
foreach (XDLPip pip in netToRoute.Pips)
{
Tile newStartTile = FPGA.FPGA.Instance.GetTile(pip.Location);
startLocations.Add(new Location(newStartTile, new Port(pip.From)));
}
// dequeue next target
Location targetLocation = targetQueue.Dequeue();
Watch.Start("route");
List <Location> revPath = Route(SearchMode, true, startLocations, targetLocation, 0, 100, false).FirstOrDefault();
Watch.Stop("route");
// extend net
if (revPath != null)
{
XDLNet extension = new XDLNet(revPath);
netToRoute.Add(extension);
}
}
// block the added pips
netToRoute.BlockUsedResources();
}