public MemAddr inst_wnd_head_addr() { ulong block_addr = inst_wnd.head(); ulong paddr = block_addr << Config.proc.block_size_bits; MemAddr addr = MemMap.Translate(paddr); return(addr); }
public void Set(int pid, ReqType type, ulong paddr) { // state Pid = pid; Type = type; // address TracePaddr = paddr; if (Config.mctrl.page_randomize) { Paddr = Prand.get_paddr(paddr); } else if (Config.mctrl.page_sequence) { Paddr = Pseq.get_paddr(paddr); } else if (Config.mctrl.page_contiguous) { Paddr = Pcontig.get_paddr(paddr); } else { Paddr = paddr; } BlockAddr = Paddr >> Config.proc.block_size_bits; Addr = MemMap.Translate(Paddr); Stat.procs[pid].allocated_physical_pages.collect(); reset_timing(); // Word offset ulong pwo = (Paddr & (63)) >> 2; Dbg.AssertPrint(pwo == ((paddr & (63)) >> 2), "Word offset should be the same for both virtual and physical addresses."); Dbg.AssertPrint(pwo < 16, "There should be only 8 words in a cacheline=" + pwo); WordOffset = (int)pwo; }