public void ANDLW()
{
_mem.SetupGet(p => p.WReg).Returns(6);
int literal = 10;
ResultInfo op_result = _opService.ANDLW(literal);
Assert.AreEqual(1, op_result.Cycles);
Assert.AreEqual(1, op_result.PCIncrement);
Assert.IsTrue(op_result.CheckZ);
Assert.AreEqual(2, op_result.OperationResults[0].Value);
Assert.AreEqual(MemoryConstants.WRegPlaceholder, op_result.OperationResults[0].Address);
_mem.Verify(p => p.WReg);
}
private ResultInfo AnalyzeNibble2Literal()
{
int nibble2 = (int)_command & 0b_0000_1111_0000_0000;
int literal = (int)_command & 0b_0000_0000_1111_1111;
switch (nibble2)
{
case 0b_1001_0000_0000:
return(_literalControlOperations.ANDLW(literal));
case 0b_1000_0000_0000:
return(_literalControlOperations.IORLW(literal));
case 0b_1010_0000_0000:
return(_literalControlOperations.XORLW(literal));
case 0b_1110_0000_0000: //ab hier addlw
case 0b_1111_0000_0000:
return(_literalControlOperations.ADDLW(literal));
case 0b_1100_0000_0000: //ab hier sublw
case 0b_1101_0000_0000:
return(_literalControlOperations.SUBLW(literal));
case 0b_0000_0000_0000: //ab hier movlw
case 0b_0001_0000_0000:
case 0b_0010_0000_0000:
case 0b_0011_0000_0000:
return(_literalControlOperations.MOVLW(literal));
case 0b_0100_0000_0000: //ab hier retlw
case 0b_0101_0000_0000:
case 0b_0110_0000_0000:
case 0b_0111_0000_0000:
return(_literalControlOperations.RETLW(literal));
default:
return(null);
}
}