public int GetResourceRequirement(IdentifierManager.RegexTypes resType)
{
if (!Chains.ContainsKey(resType))
{
return(0);
}
return(Chains[resType].Sum());
}
public char GetCharForResourceType(IdentifierManager.RegexTypes resType)
{
if (!m_res2StringMapping.ContainsKey(resType))
{
Tile any = FPGA.FPGA.Instance.GetAllTiles().FirstOrDefault(t => Regex.IsMatch(t.Location, IdentifierManager.Instance.GetRegex(resType)));
m_res2StringMapping.Add(resType, any.Location[0]);
}
return(m_res2StringMapping[resType]);
}
private Dictionary <int, int> GetBins(IdentifierManager.RegexTypes resourceType, string resourceString, int height)
{
Dictionary <int, int> bins = new Dictionary <int, int>();
char name = m_resStringInfo.GetCharForResourceType(resourceType);
for (int i = 0; i < resourceString.Count(c => c.Equals(name)); i++)
{
bins[i] = height;
}
return(bins);
}
private void PrintAreaConstraintForResourceType(IdentifierManager.RegexTypes filterType, int[] sliceIndeces, string groupName)
{
int incr1 = 0;
int incr2 = 1; // why = 1?
//int incr2 = 0;
bool success = Print(incr1, incr2, FPGATypes.Placement.LowerLeft, FPGATypes.Placement.UpperRight, filterType, sliceIndeces, groupName);
if (!success)
{
incr1 = 1;
incr2 = 0;
success = Print(incr1, incr2, FPGATypes.Placement.LowerLeft, FPGATypes.Placement.UpperRight, filterType, sliceIndeces, groupName);
if (!success)
{
//String filter = IdentifierManager.Instance.GetRegex(filterType);
//this.OutputManager.WriteUCFOutput("# could not find (LowerLeft and UpperRight) nor (UpperLeft nor LowerRight) for tile type " + filter + " in current selection. # generated_by_GoAhead");
}
}
}
public static bool IsOrientedMatch(string block, IdentifierManager.RegexTypes type)
{
if (IdentifierManager.Instance.HasRegexp(type))
{
return(IdentifierManager.Instance.IsMatch(block, type));
}
Regex defaultRegex = new Regex("");
switch (type)
{
case IdentifierManager.RegexTypes.CLB_left:
defaultRegex = ClbLeft;
break;
case IdentifierManager.RegexTypes.CLB_right:
defaultRegex = ClbRight;
break;
case IdentifierManager.RegexTypes.Interconnect_left:
defaultRegex = IntLeft;
break;
case IdentifierManager.RegexTypes.Interconnect_right:
defaultRegex = IntRight;
break;
case IdentifierManager.RegexTypes.BRAM_left:
defaultRegex = BRAMLeft;
break;
case IdentifierManager.RegexTypes.BRAM_right:
defaultRegex = BRAMRight;
break;
}
return(defaultRegex.IsMatch(block));
}
private bool Print(int incr1, int incr2, FPGATypes.Placement placement1, FPGATypes.Placement placement2, IdentifierManager.RegexTypes filterType, int[] sliceIndeces, string groupName)
{
string filter = IdentifierManager.Instance.GetRegex(filterType);
Tile tile1 = TileSelectionManager.Instance.GetSelectedTile(filter, placement1);
Tile tile2 = TileSelectionManager.Instance.GetSelectedTile(filter, placement2);
if (tile1 == null || tile2 == null)
{
return(false);
}
if (tile1.Slices.Count == 0 || tile2.Slices.Count == 0)
{
return(false);
}
switch (FPGA.FPGA.Instance.BackendType)
{
case FPGATypes.BackendType.ISE:
// Virtex 6 hard coded
if (FPGA.FPGA.Instance.Family == FPGATypes.FPGAFamily.Virtex6 && filterType == IdentifierManager.RegexTypes.BRAM)
{
if (tile1.Slices.Count != 3 || tile2.Slices.Count != 3)
{
throw new ArgumentException("Unexpected number of slices in Virtex6 RAM tile");
}
string lowerLeftSlice = tile1.Slices[0].ToString();
string upperRightSlice = tile2.Slices[1].ToString();
string firstLine = "AREA_GROUP \"" + groupName + "\"" + " RANGE = " + lowerLeftSlice + ":" + upperRightSlice + "; # generated_by_GoAhead";
OutputManager.WriteUCFOutput(firstLine);
string lowerLeftRAMB36Slice = tile1.Slices[2].ToString();
string upperRightRAMB36Slice = tile2.Slices[2].ToString();
string secondLine = "AREA_GROUP \"" + groupName + "\"" + " RANGE = " + lowerLeftRAMB36Slice + ":" + upperRightRAMB36Slice + "; # generated_by_GoAhead";
OutputManager.WriteUCFOutput(secondLine);
}
else if (FPGA.FPGA.Instance.Family == FPGATypes.FPGAFamily.Virtex6 && filterType == IdentifierManager.RegexTypes.DSP)
{
if (tile1.Slices.Count != 3 || tile2.Slices.Count != 3)
{
throw new ArgumentException("Unexpected number of slices in Virtex6 DSP tile");
}
string lowerLeftSlice = tile1.Slices[0].ToString();
string upperRightSlice = tile2.Slices[1].ToString();
string firstLine = "AREA_GROUP \"" + groupName + "\"" + " RANGE = " + lowerLeftSlice + ":" + upperRightSlice + "; # generated_by_GoAhead";
OutputManager.WriteUCFOutput(firstLine);
}
else
{
// other devices "genericly"
for (int i = 0; i < sliceIndeces.Length; i += 2)
{
string lowerLeftSlice = tile1.Slices[sliceIndeces[i + incr1]].ToString();
string upperRightSlice = tile2.Slices[sliceIndeces[i + incr2]].ToString();
string secondLine = "AREA_GROUP \"" + groupName + "\"" + " RANGE = " + lowerLeftSlice + ":" + upperRightSlice + "; # generated_by_GoAhead";
OutputManager.WriteUCFOutput(secondLine);
}
}
break;
case FPGATypes.BackendType.Vivado:
for (int i = 0; i < sliceIndeces.Length; i += 2) // why < Length?
{
string lowerLeftSlice = tile1.Slices[sliceIndeces[i + incr1]].ToString();
string upperRightSlice = tile2.Slices[sliceIndeces[i + incr2]].ToString();
string secondLine = "resize_pblock [get_pblocks " + groupName + "] -add {" + lowerLeftSlice + ":" + upperRightSlice + "}; # generated_by_GoAhead";
OutputManager.WriteTCLOutput(secondLine);
}
break;
}
return(true);
}
